diff options
Diffstat (limited to 'src/spdk/dpdk/examples/performance-thread/common/arch')
6 files changed, 286 insertions, 0 deletions
diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.c b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.c new file mode 100644 index 00000000..7c5c9165 --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#include <rte_common.h> +#include <ctx.h> + +void +ctx_switch(struct ctx *new_ctx __rte_unused, struct ctx *curr_ctx __rte_unused) +{ + /* SAVE CURRENT CONTEXT */ + asm volatile ( + /* Save SP */ + "mov x3, sp\n" + "str x3, [x1, #0]\n" + + /* Save FP and LR */ + "stp x29, x30, [x1, #8]\n" + + /* Save Callee Saved Regs x19 - x28 */ + "stp x19, x20, [x1, #24]\n" + "stp x21, x22, [x1, #40]\n" + "stp x23, x24, [x1, #56]\n" + "stp x25, x26, [x1, #72]\n" + "stp x27, x28, [x1, #88]\n" + + /* + * Save bottom 64-bits of Callee Saved + * SIMD Regs v8 - v15 + */ + "stp d8, d9, [x1, #104]\n" + "stp d10, d11, [x1, #120]\n" + "stp d12, d13, [x1, #136]\n" + "stp d14, d15, [x1, #152]\n" + ); + + /* RESTORE NEW CONTEXT */ + asm volatile ( + /* Restore SP */ + "ldr x3, [x0, #0]\n" + "mov sp, x3\n" + + /* Restore FP and LR */ + "ldp x29, x30, [x0, #8]\n" + + /* Restore Callee Saved Regs x19 - x28 */ + "ldp x19, x20, [x0, #24]\n" + "ldp x21, x22, [x0, #40]\n" + "ldp x23, x24, [x0, #56]\n" + "ldp x25, x26, [x0, #72]\n" + "ldp x27, x28, [x0, #88]\n" + + /* + * Restore bottom 64-bits of Callee Saved + * SIMD Regs v8 - v15 + */ + "ldp d8, d9, [x0, #104]\n" + "ldp d10, d11, [x0, #120]\n" + "ldp d12, d13, [x0, #136]\n" + "ldp d14, d15, [x0, #152]\n" + ); +} diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.h b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.h new file mode 100644 index 00000000..74c2e7a7 --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/ctx.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef CTX_H +#define CTX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CPU context registers + */ +struct ctx { + void *sp; /* 0 */ + void *fp; /* 8 */ + void *lr; /* 16 */ + + /* Callee Saved Generic Registers */ + void *r19; /* 24 */ + void *r20; /* 32 */ + void *r21; /* 40 */ + void *r22; /* 48 */ + void *r23; /* 56 */ + void *r24; /* 64 */ + void *r25; /* 72 */ + void *r26; /* 80 */ + void *r27; /* 88 */ + void *r28; /* 96 */ + + /* + * Callee Saved SIMD Registers. Only the bottom 64-bits + * of these registers needs to be saved. + */ + void *v8; /* 104 */ + void *v9; /* 112 */ + void *v10; /* 120 */ + void *v11; /* 128 */ + void *v12; /* 136 */ + void *v13; /* 144 */ + void *v14; /* 152 */ + void *v15; /* 160 */ +}; + + +void +ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx); + + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_CTX_H_ */ diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/stack.h b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/stack.h new file mode 100644 index 00000000..722c4733 --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/arm64/stack.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2017 Cavium, Inc + */ + +#ifndef STACK_H +#define STACK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lthread_int.h" + +/* + * Sets up the initial stack for the lthread. + */ +static inline void +arch_set_stack(struct lthread *lt, void *func) +{ + void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size); + + /* + * Align stack_top to 16 bytes. Arm64 has the constraint that the + * stack pointer must always be quad-word aligned. + */ + stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL); + + /* + * First Stack Frame + */ + stack_top[0] = NULL; + stack_top[-1] = NULL; + + /* + * Initialize the context + */ + lt->ctx.fp = &stack_top[-1]; + lt->ctx.sp = &stack_top[-2]; + + /* + * Here only the address of _lthread_exec is saved as the link + * register value. The argument to _lthread_exec i.e the address of + * the lthread struct is not saved. This is because the first + * argument to ctx_switch is the address of the new context, + * which also happens to be the address of required lthread struct. + * So while returning from ctx_switch into _thread_exec, parameter + * register x0 will always contain the required value. + */ + lt->ctx.lr = func; +} + +#ifdef __cplusplus +} +#endif + +#endif /* STACK_H_ */ diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.c b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.c new file mode 100644 index 00000000..d63fd9fc --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.c @@ -0,0 +1,37 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright 2015 Intel Corporation. + * Copyright 2012 Hasan Alayli <halayli@gmail.com> + */ + +#if defined(__x86_64__) +__asm__ ( +".text\n" +".p2align 4,,15\n" +".globl ctx_switch\n" +".globl _ctx_switch\n" +"ctx_switch:\n" +"_ctx_switch:\n" +" movq %rsp, 0(%rsi) # save stack_pointer\n" +" movq %rbp, 8(%rsi) # save frame_pointer\n" +" movq (%rsp), %rax # save insn_pointer\n" +" movq %rax, 16(%rsi)\n" +" movq %rbx, 24(%rsi)\n # save rbx,r12-r15\n" +" movq 24(%rdi), %rbx\n" +" movq %r15, 56(%rsi)\n" +" movq %r14, 48(%rsi)\n" +" movq 48(%rdi), %r14\n" +" movq 56(%rdi), %r15\n" +" movq %r13, 40(%rsi)\n" +" movq %r12, 32(%rsi)\n" +" movq 32(%rdi), %r12\n" +" movq 40(%rdi), %r13\n" +" movq 0(%rdi), %rsp # restore stack_pointer\n" +" movq 16(%rdi), %rax # restore insn_pointer\n" +" movq 8(%rdi), %rbp # restore frame_pointer\n" +" movq %rax, (%rsp)\n" +" ret\n" + ); +#else +#pragma GCC error "__x86_64__ is not defined" +#endif diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.h b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.h new file mode 100644 index 00000000..c6a46c52 --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/ctx.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Intel Corporation + */ + + +#ifndef CTX_H +#define CTX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CPU context registers + */ +struct ctx { + void *rsp; /* 0 */ + void *rbp; /* 8 */ + void *rip; /* 16 */ + void *rbx; /* 24 */ + void *r12; /* 32 */ + void *r13; /* 40 */ + void *r14; /* 48 */ + void *r15; /* 56 */ +}; + + +void +ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx); + + +#ifdef __cplusplus +} +#endif + +#endif /* RTE_CTX_H_ */ diff --git a/src/spdk/dpdk/examples/performance-thread/common/arch/x86/stack.h b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/stack.h new file mode 100644 index 00000000..7cdd5c7a --- /dev/null +++ b/src/spdk/dpdk/examples/performance-thread/common/arch/x86/stack.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2015 Intel Corporation. + * Copyright(c) Cavium, Inc. 2017. + * All rights reserved + * Copyright (C) 2012, Hasan Alayli <halayli@gmail.com> + * Portions derived from: https://github.com/halayli/lthread + * With permissions from Hasan Alayli to use them as BSD-3-Clause + */ + +#ifndef STACK_H +#define STACK_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lthread_int.h" + +/* + * Sets up the initial stack for the lthread. + */ +static inline void +arch_set_stack(struct lthread *lt, void *func) +{ + char *stack_top = (char *)(lt->stack) + lt->stack_size; + void **s = (void **)stack_top; + + /* set initial context */ + s[-3] = NULL; + s[-2] = (void *)lt; + lt->ctx.rsp = (void *)(stack_top - (4 * sizeof(void *))); + lt->ctx.rbp = (void *)(stack_top - (3 * sizeof(void *))); + lt->ctx.rip = func; +} + +#ifdef __cplusplus +} +#endif + +#endif /* STACK_H_ */ |