1 files changed, 135 insertions, 0 deletions
diff --git a/src/spdk/dpdk/test/test-pipeline/pipeline_stub.c b/src/spdk/dpdk/test/test-pipeline/pipeline_stub.c
new file mode 100644
index 00000000..b6750d51
--- /dev/null
+++ b/src/spdk/dpdk/test/test-pipeline/pipeline_stub.c
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2016 Intel Corporation
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+
+#include <rte_log.h>
+#include <rte_port_ring.h>
+#include <rte_table_stub.h>
+#include <rte_pipeline.h>
+
+#include "main.h"
+
+void
+app_main_loop_worker_pipeline_stub(void) {
+	struct rte_pipeline_params pipeline_params = {
+		.name = "pipeline",
+		.socket_id = rte_socket_id(),
+	};
+
+	struct rte_pipeline *p;
+	uint32_t port_in_id[APP_MAX_PORTS];
+	uint32_t port_out_id[APP_MAX_PORTS];
+	uint32_t table_id[APP_MAX_PORTS];
+	uint32_t i;
+
+	RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with stub "
+		"tables)\n", rte_lcore_id());
+
+	/* Pipeline configuration */
+	p = rte_pipeline_create(&pipeline_params);
+	if (p == NULL)
+		rte_panic("Unable to configure the pipeline\n");
+
+	/* Input port configuration */
+	for (i = 0; i < app.n_ports; i++) {
+		struct rte_port_ring_reader_params port_ring_params = {
+			.ring = app.rings_rx[i],
+		};
+
+		struct rte_pipeline_port_in_params port_params = {
+			.ops = &rte_port_ring_reader_ops,
+			.arg_create = (void *) &port_ring_params,
+			.f_action = NULL,
+			.arg_ah = NULL,
+			.burst_size = app.burst_size_worker_read,
+		};
+
+		if (rte_pipeline_port_in_create(p, &port_params,
+			&port_in_id[i]))
+			rte_panic("Unable to configure input port for "
+				"ring %d\n", i);
+	}
+
+	/* Output port configuration */
+	for (i = 0; i < app.n_ports; i++) {
+		struct rte_port_ring_writer_params port_ring_params = {
+			.ring = app.rings_tx[i],
+			.tx_burst_sz = app.burst_size_worker_write,
+		};
+
+		struct rte_pipeline_port_out_params port_params = {
+			.ops = &rte_port_ring_writer_ops,
+			.arg_create = (void *) &port_ring_params,
+			.f_action = NULL,
+			.arg_ah = NULL,
+		};
+
+		if (rte_pipeline_port_out_create(p, &port_params,
+			&port_out_id[i]))
+			rte_panic("Unable to configure output port for "
+				"ring %d\n", i);
+	}
+
+	/* Table configuration */
+	for (i = 0; i < app.n_ports; i++) {
+		struct rte_pipeline_table_params table_params = {
+			.ops = &rte_table_stub_ops,
+			.arg_create = NULL,
+			.f_action_hit = NULL,
+			.f_action_miss = NULL,
+			.arg_ah = NULL,
+			.action_data_size = 0,
+		};
+
+		if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
+			rte_panic("Unable to configure table %u\n", i);
+	}
+
+	/* Interconnecting ports and tables */
+	for (i = 0; i < app.n_ports; i++)
+		if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
+				table_id[i]))
+			rte_panic("Unable to connect input port %u to "
+				"table %u\n", port_in_id[i],  table_id[i]);
+
+	/* Add entries to tables */
+	for (i = 0; i < app.n_ports; i++) {
+		struct rte_pipeline_table_entry entry = {
+			.action = RTE_PIPELINE_ACTION_PORT,
+			{.port_id = port_out_id[i ^ 1]},
+		};
+		struct rte_pipeline_table_entry *default_entry_ptr;
+
+		if (rte_pipeline_table_default_entry_add(p, table_id[i], &entry,
+			&default_entry_ptr))
+			rte_panic("Unable to add default entry to table %u\n",
+				table_id[i]);
+	}
+
+	/* Enable input ports */
+	for (i = 0; i < app.n_ports; i++)
+		if (rte_pipeline_port_in_enable(p, port_in_id[i]))
+			rte_panic("Unable to enable input port %u\n",
+				port_in_id[i]);
+
+	/* Check pipeline consistency */
+	if (rte_pipeline_check(p) < 0)
+		rte_panic("Pipeline consistency check failed\n");
+
+	/* Run-time */
+#if APP_FLUSH == 0
+	for ( ; ; )
+		rte_pipeline_run(p);
+#else
+	for (i = 0; ; i++) {
+		rte_pipeline_run(p);
+
+		if ((i & APP_FLUSH) == 0)
+			rte_pipeline_flush(p);
+	}
+#endif
+}