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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP34xx/OMAP36xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&cm_clocks {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
ssi_ssr_fck: ssi_ssr_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
};
ssi_sst_fck: ssi_sst_fck_3430es2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&ssi_ssr_fck>;
clock-mult = <1>;
clock-div = <2>;
};
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <0>;
};
usim_gate_fck: usim_gate_fck@c00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&omap_96m_fck>;
ti,bit-shift = <9>;
reg = <0x0c00>;
};
sys_d2_ck: sys_d2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_ck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d2_fck: omap_96m_d2_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d4_fck: omap_96m_d4_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <4>;
};
omap_96m_d8_fck: omap_96m_d8_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <8>;
};
omap_96m_d10_fck: omap_96m_d10_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <10>;
};
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <20>;
};
usim_mux_fck: usim_mux_fck@c40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
ti,bit-shift = <3>;
reg = <0x0c40>;
ti,index-starts-at-one;
};
usim_fck: usim_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
usim_ick: usim_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
reg = <0x0c10>;
ti,bit-shift = <9>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
<&gpt1_ick>, <&usim_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&ssi_ick>;
};
};
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