summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/r8a7792.dtsi
blob: f5b299bfcb23796cccc0f108ca888a0ece5eb95e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car V2H (R8A77920) SoC
 *
 * Copyright (C) 2016 Cogent Embedded Inc.
 */

#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7792-sysc.h>

/ {
	compatible = "renesas,r8a7792";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &iic3;
		spi0 = &qspi;
		spi1 = &msiof0;
		spi2 = &msiof1;
		vin0 = &vin0;
		vin1 = &vin1;
		vin2 = &vin2;
		vin3 = &vin3;
		vin4 = &vin4;
		vin5 = &vin5;
	};

	/* External CAN clock */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "renesas,apmu";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
			power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
			next-level-cache = <&L2_CA15>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
			power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
			next-level-cache = <&L2_CA15>;
		};

		L2_CA15: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			power-domains = <&sysc R8A7792_PD_CA15_SCU>;
		};
	};

	/* External root clock */
	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a7792-wdt",
				     "renesas,rcar-gen2-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 29>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 23>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 28>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055100 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055100 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 905>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 905>;
		};

		gpio7: gpio@e6055200 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055200 0 0x50>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 224 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 904>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 904>;
		};

		gpio8: gpio@e6055300 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055300 0 0x50>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 256 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 921>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 921>;
		};

		gpio9: gpio@e6055400 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 288 17>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 919>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 919>;
		};

		gpio10: gpio@e6055500 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055500 0 0x50>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 320 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 914>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 914>;
		};

		gpio11: gpio@e6055600 {
			compatible = "renesas,gpio-r8a7792",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055600 0 0x50>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 352 30>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 913>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 913>;
		};

		pfc: pinctrl@e6060000 {
			compatible = "renesas,pfc-r8a7792";
			reg = <0 0xe6060000 0 0x144>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a7792-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		apmu@e6152000 {
			compatible = "renesas,r8a7792-apmu", "renesas,apmu";
			reg = <0 0xe6152000 0 0x188>;
			cpus = <&cpu0 &cpu1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a7792-rst";
			reg = <0 0xe6160000 0 0x0100>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a7792-sysc";
			reg = <0 0xe6180000 0 0x0200>;
			#power-domain-cells = <1>;
		};

		irqc: interrupt-controller@e61c0000 {
			compatible = "renesas,irqc-r8a7792", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 407>;
		};

		icram0:	sram@e63a0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63a0000 0 0x12000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63a0000 0x12000>;
		};

		icram1:	sram@e63c0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63c0000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63c0000 0x1000>;

			smp-sram@0 {
				compatible = "renesas,smp-sram";
				reg = <0 0x100>;
			};
		};

		/* I2C doesn't need pinmux */
		i2c0: i2c@e6508000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 931>;
			i2c-scl-internal-delay-ns = <6>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@e6518000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6518000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 930>;
			i2c-scl-internal-delay-ns = <6>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@e6530000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6530000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 929>;
			i2c-scl-internal-delay-ns = <6>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@e6540000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6540000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 928>;
			i2c-scl-internal-delay-ns = <6>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@e6520000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6520000 0 0x40>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 927>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 927>;
			i2c-scl-internal-delay-ns = <6>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@e6528000 {
			compatible = "renesas,i2c-r8a7792",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6528000 0 0x40>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 925>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 925>;
			i2c-scl-internal-delay-ns = <110>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		iic3: i2c@e60b0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7792",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe60b0000 0 0x425>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 926>;
			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
			       <&dmac1 0x77>, <&dmac1 0x78>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 926>;
			status = "disabled";
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a7792",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x20000>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		dmac1: dma-controller@e6720000 {
			compatible = "renesas,dmac-r8a7792",
				     "renesas,rcar-dmac";
			reg = <0 0xe6720000 0 0x20000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a7792",
				     "renesas,etheravb-rcar-gen2";
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		qspi: spi@e6b10000 {
			compatible = "renesas,qspi-r8a7792", "renesas,qspi";
			reg = <0 0xe6b10000 0 0x2c>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 917>;
			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
			       <&dmac1 0x17>, <&dmac1 0x18>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 917>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a7792",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e60000 0 64>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 721>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
			       <&dmac1 0x29>, <&dmac1 0x2a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 721>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a7792",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e68000 0 64>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 720>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
			       <&dmac1 0x2d>, <&dmac1 0x2e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 720>;
			status = "disabled";
		};

		scif2: serial@e6e58000 {
			compatible = "renesas,scif-r8a7792",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e58000 0 64>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 719>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
			       <&dmac1 0x2b>, <&dmac1 0x2c>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 719>;
			status = "disabled";
		};

		scif3: serial@e6ea8000 {
			compatible = "renesas,scif-r8a7792",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6ea8000 0 64>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 718>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
			       <&dmac1 0x2f>, <&dmac1 0x30>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 718>;
			status = "disabled";
		};

		hscif0: serial@e62c0000 {
			compatible = "renesas,hscif-r8a7792",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c0000 0 96>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 717>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
			       <&dmac1 0x39>, <&dmac1 0x3a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 717>;
			status = "disabled";
		};

		hscif1: serial@e62c8000 {
			compatible = "renesas,hscif-r8a7792",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c8000 0 96>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 716>,
				 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
			       <&dmac1 0x4d>, <&dmac1 0x4e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 716>;
			status = "disabled";
		};

		msiof0: spi@e6e20000 {
			compatible = "renesas,msiof-r8a7792",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6e20000 0 0x0064>;
			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 000>;
			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
			       <&dmac1 0x51>, <&dmac1 0x52>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 000>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof1: spi@e6e10000 {
			compatible = "renesas,msiof-r8a7792",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6e10000 0 0x0064>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 208>;
			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
			       <&dmac1 0x55>, <&dmac1 0x56>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 208>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@e6e80000 {
			compatible = "renesas,can-r8a7792",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e80000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 916>,
				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 916>;
			status = "disabled";
		};

		can1: can@e6e88000 {
			compatible = "renesas,can-r8a7792",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e88000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>,
				 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			status = "disabled";
		};

		vin0: video@e6ef0000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef0000 0 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 811>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 811>;
			status = "disabled";
		};

		vin1: video@e6ef1000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef1000 0 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 810>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 810>;
			status = "disabled";
		};

		vin2: video@e6ef2000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef2000 0 0x1000>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 809>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 809>;
			status = "disabled";
		};

		vin3: video@e6ef3000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef3000 0 0x1000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 808>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 808>;
			status = "disabled";
		};

		vin4: video@e6ef4000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef4000 0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 805>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 805>;
			status = "disabled";
		};

		vin5: video@e6ef5000 {
			compatible = "renesas,vin-r8a7792",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef5000 0 0x1000>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 804>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 804>;
			status = "disabled";
		};

		sdhi0: mmc@ee100000 {
			compatible = "renesas,sdhi-r8a7792",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee100000 0 0x328>;
			interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
			       <&dmac1 0xcd>, <&dmac1 0xce>;
			dma-names = "tx", "rx", "tx", "rx";
			clocks = <&cpg CPG_MOD 314>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 314>;
			status = "disabled";
		};

		gic: interrupt-controller@f1001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0 0xf1001000 0 0x1000>,
			      <0 0xf1002000 0 0x2000>,
			      <0 0xf1004000 0 0x2000>,
			      <0 0xf1006000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
				      IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		vsp@fe928000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe928000 0 0x8000>;
			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 131>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 131>;
		};

		vsp@fe930000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe930000 0 0x8000>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 128>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 128>;
		};

		vsp@fe938000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe938000 0 0x8000>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 127>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 127>;
		};

		jpu: jpeg-codec@fe980000 {
			compatible = "renesas,jpu-r8a7792",
				     "renesas,rcar-gen2-jpu";
			reg = <0 0xfe980000 0 0x10300>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 106>;
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 106>;
		};

		du: display@feb00000 {
			compatible = "renesas,du-r8a7792";
			reg = <0 0xfeb00000 0 0x40000>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
			clock-names = "du.0", "du.1";
			resets = <&cpg 724>;
			reset-names = "du.0";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					du_out_rgb0: endpoint {
					};
				};
				port@1 {
					reg = <1>;
					du_out_rgb1: endpoint {
					};
				};
			};
		};

		prr: chipid@ff000044 {
			compatible = "renesas,prr";
			reg = <0 0xff000044 0 4>;
		};

		cmt0: timer@ffca0000 {
			compatible = "renesas,r8a7792-cmt0",
				     "renesas,rcar-gen2-cmt0";
			reg = <0 0xffca0000 0 0x1004>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 124>;
			clock-names = "fck";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 124>;

			status = "disabled";
		};

		cmt1: timer@e6130000 {
			compatible = "renesas,r8a7792-cmt1",
				     "renesas,rcar-gen2-cmt1";
			reg = <0 0xe6130000 0 0x1004>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 329>;
			clock-names = "fck";
			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
			resets = <&cpg 329>;

			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};
};