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[
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x1",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_CONFLICT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Speculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writes.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"SampleAfterValue": "2000003",
"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation for transactional writes."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x4",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"SampleAfterValue": "100003",
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x8",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x10",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x20",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
"EventCode": "0x54",
"Counter": "0,1,2,3",
"UMask": "0x40",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"EventCode": "0x5d",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TX_EXEC.MISC2",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"EventCode": "0x5d",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TX_EXEC.MISC3",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded"
},
{
"CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
"CounterMask": "2"
},
{
"CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3",
"UMask": "0x6",
"PEBScounters": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"SampleAfterValue": "2000003",
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"CounterMask": "6"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
"EventCode": "0xB0",
"Counter": "0,1,2,3",
"UMask": "0x10",
"PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "100003",
"BriefDescription": "Demand Data Read requests who miss L3 cache"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"EventCode": "0xc3",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "100003",
"BriefDescription": "Number of machine clears due to memory ordering conflicts."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.START",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution started."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times HLE commit succeeded.",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution successfully committed",
"Data_LA": "1"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times HLE abort was triggered.",
"EventCode": "0xc8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.ABORTED",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x8",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts)."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.START",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution started."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.COMMIT",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution successfully committed"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times RTM abort was triggered.",
"EventCode": "0xc9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution aborted.",
"Data_LA": "1"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x8",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003",
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x4",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"SampleAfterValue": "100003",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x8",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"SampleAfterValue": "50021",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x10",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"MSRIndex": "0x3F6",
"SampleAfterValue": "20011",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x20",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6",
"SampleAfterValue": "100007",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x40",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"SampleAfterValue": "2003",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x80",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"SampleAfterValue": "1009",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x100",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6",
"SampleAfterValue": "503",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"TakenAlone": "1"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x200",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"SampleAfterValue": "101",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
"TakenAlone": "1"
}
]
|
