diff options
Diffstat (limited to 'src/spdk/dpdk/drivers/net/enetc')
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/Makefile | 23 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/base/enetc_hw.h | 277 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/enetc.h | 114 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/enetc_ethdev.c | 960 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/enetc_logs.h | 42 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/enetc_rxtx.c | 401 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/meson.build | 13 | ||||
| -rw-r--r-- | src/spdk/dpdk/drivers/net/enetc/rte_pmd_enetc_version.map | 3 |
8 files changed, 1833 insertions, 0 deletions
diff --git a/src/spdk/dpdk/drivers/net/enetc/Makefile b/src/spdk/dpdk/drivers/net/enetc/Makefile new file mode 100644 index 000000000..7276026e3 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/Makefile @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_enetc.a + +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) +CFLAGS += -I$(RTE_SDK)/drivers/common/dpaax +EXPORT_MAP := rte_pmd_enetc_version.map +SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_ethdev.c +SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_rxtx.c + +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool +LDLIBS += -lrte_ethdev -lrte_net +LDLIBS += -lrte_bus_pci +LDLIBS += -lrte_common_dpaax + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/src/spdk/dpdk/drivers/net/enetc/base/enetc_hw.h b/src/spdk/dpdk/drivers/net/enetc/base/enetc_hw.h new file mode 100644 index 000000000..66fad58e5 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/base/enetc_hw.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2020 NXP + */ + +#ifndef _ENETC_HW_H_ +#define _ENETC_HW_H_ +#include <rte_io.h> + +#define BIT(x) ((uint64_t)1 << ((x))) + +/* ENETC device IDs */ +#define ENETC_DEV_ID_VF 0xef00 +#define ENETC_DEV_ID 0xe100 + +/* BD RING ALIGNMENT */ +#define ENETC_BD_RING_ALIGN 128 + +/* ENETC register block BAR */ +#define ENETC_BAR_REGS 0x0 + +/* SI regs, offset: 0h */ +#define ENETC_SIMR 0x0 +#define ENETC_SIMR_EN BIT(31) + +#define ENETC_SICAR0 0x40 +#define ENETC_SICAR0_COHERENT 0x2B2B6727 +#define ENETC_SIPMAR0 0x80 +#define ENETC_SIPMAR1 0x84 + +#define ENETC_SICAPR0 0x900 +#define ENETC_SICAPR1 0x904 + +#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) +#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) + +#define ENETC_SICCAPR 0x1200 + +/* enum for BD type */ +enum enetc_bdr_type {TX, RX}; + +#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \ + + (off)) +/* RX BDR reg offsets */ +#define ENETC_RBMR 0x0 /* RX BDR mode register*/ +#define ENETC_RBMR_EN BIT(31) + +#define ENETC_RBSR 0x4 /* Rx BDR status register*/ +#define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/ +#define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/ +#define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */ +#define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/ +#define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/ +#define ENETC_RBLENR 0x20 /* Rx BDR length register*/ +#define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/ +#define ENETC_RBIER_RXTIE BIT(0) +#define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/ +#define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/ +#define ENETC_RBICIR0_ICEN BIT(31) + + +#define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */ +#define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */ +#define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */ +#define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */ +#define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */ +#define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */ +#define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */ +#define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */ +#define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */ +#define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */ +#define ENETC_TBLENR 0x20 + +#define ENETC_TBCISR_IDX_MASK 0xffff +#define ENETC_TBIER_TXFIE BIT(1) + +#define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) +#define ENETC_TBMR_EN BIT(31) + +/* Port regs, offset: 1_0000h */ +#define ENETC_PORT_BASE 0x10000 +#define ENETC_PMR 0x00000 +#define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18)) +#define ENETC_PSR 0x00004 /* RO */ +#define ENETC_PSIPMR 0x00018 +#define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */ +#define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 16)) +#define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20) +#define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20) +#define ENETC_PCAPR0 0x00900 +#define ENETC_PCAPR1 0x00904 +#define ENETC_PM0_RX_FIFO 0x801C +#define ENETC_PM0_IF_MODE 0x8300 +#define ENETC_PM1_IF_MODE 0x9300 +#define ENETC_PMO_IFM_RG BIT(2) +#define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11)) +#define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1)) +#define ENETC_PM0_IFM_XGMII BIT(12) + +#define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10) +#define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff) +#define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16) + +#define ENETC_PM0_CMD_CFG 0x08008 +#define ENETC_PM0_TX_EN BIT(0) +#define ENETC_PM0_RX_EN BIT(1) +#define ENETC_PM0_CRC BIT(6) + +#define ENETC_PAR_PORT_CFG 0x03050 +#define L3_CKSUM BIT(0) +#define L4_CKSUM BIT(1) + +#define ENETC_PM0_MAXFRM 0x08014 +#define ENETC_SET_TX_MTU(val) ((val) << 16) +#define ENETC_SET_MAXFRM(val) ((val) & 0xffff) +#define ENETC_PTXMBAR 0x0608 +/* n = TC index [0..7] */ +#define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) + +#define ENETC_PM0_STATUS 0x08304 +#define ENETC_LINK_MODE 0x0000000000080000ULL +#define ENETC_LINK_STATUS 0x0000000000010000ULL +#define ENETC_LINK_SPEED_MASK 0x0000000000060000ULL +#define ENETC_LINK_SPEED_10M 0x0ULL +#define ENETC_LINK_SPEED_100M 0x0000000000020000ULL +#define ENETC_LINK_SPEED_1G 0x0000000000040000ULL + +/* Global regs, offset: 2_0000h */ +#define ENETC_GLOBAL_BASE 0x20000 +#define ENETC_G_EIPBRR0 0x00bf8 +#define ENETC_G_EIPBRR1 0x00bfc + +/* MAC Counters */ +/* Config register to reset counters*/ +#define ENETC_PM0_STAT_CONFIG 0x080E0 +/* Receive frames counter without error */ +#define ENETC_PM0_RFRM 0x08120 +/* Receive packets counter, good + bad */ +#define ENETC_PM0_RPKT 0x08160 +/* Received octets, good + bad */ +#define ENETC_PM0_REOCT 0x08120 +/* Transmit octets, good + bad */ +#define ENETC_PM0_TEOCT 0x08200 +/* Transmit frames counter without error */ +#define ENETC_PM0_TFRM 0x08220 +/* Transmit packets counter, good + bad */ +#define ENETC_PM0_TPKT 0x08260 +/* Dropped not Truncated packets counter */ +#define ENETC_PM0_RDRNTP 0x081C8 +/* Dropped + trucated packets counter */ +#define ENETC_PM0_RDRP 0x08158 +/* Receive packets error counter */ +#define ENETC_PM0_RERR 0x08138 +/* Transmit packets error counter */ +#define ENETC_PM0_TERR 0x08238 + +/* Stats Reset Bit*/ +#define ENETC_CLEAR_STATS BIT(2) + +#define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n)) +#define ENETC_G_EPFBLPR1_XGMII 0x80000000 + +/* general register accessors */ +#define enetc_rd_reg(reg) rte_read32((void *)(reg)) +#define enetc_wr_reg(reg, val) rte_write32((val), (void *)(reg)) +#define enetc_rd(hw, off) enetc_rd_reg((size_t)(hw)->reg + (off)) +#define enetc_wr(hw, off, val) enetc_wr_reg((size_t)(hw)->reg + (off), val) +/* port register accessors - PF only */ +#define enetc_port_rd(hw, off) enetc_rd_reg((size_t)(hw)->port + (off)) +#define enetc_port_wr(hw, off, val) \ + enetc_wr_reg((size_t)(hw)->port + (off), val) +/* global register accessors - PF only */ +#define enetc_global_rd(hw, off) \ + enetc_rd_reg((size_t)(hw)->global + (off)) +#define enetc_global_wr(hw, off, val) \ + enetc_wr_reg((size_t)(hw)->global + (off), val) +/* BDR register accessors, see ENETC_BDR() */ +#define enetc_bdr_rd(hw, t, n, off) \ + enetc_rd(hw, ENETC_BDR(t, n, off)) +#define enetc_bdr_wr(hw, t, n, off, val) \ + enetc_wr(hw, ENETC_BDR(t, n, off), val) + +#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) +#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) +#define enetc_txbdr_wr(hw, n, off, val) \ + enetc_bdr_wr(hw, TX, n, off, val) +#define enetc_rxbdr_wr(hw, n, off, val) \ + enetc_bdr_wr(hw, RX, n, off, val) + +#define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr))) + +#define ENETC_TXBD_FLAGS_IE BIT(13) +#define ENETC_TXBD_FLAGS_F BIT(15) + +/* ENETC Parsed values (Little Endian) */ +#define ENETC_PARSE_ERROR 0x8000 +#define ENETC_PKT_TYPE_ETHER 0x0060 +#define ENETC_PKT_TYPE_IPV4 0x0000 +#define ENETC_PKT_TYPE_IPV6 0x0020 +#define ENETC_PKT_TYPE_IPV4_TCP \ + (0x0010 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_TCP \ + (0x0010 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_UDP \ + (0x0011 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_UDP \ + (0x0011 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_SCTP \ + (0x0013 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_SCTP \ + (0x0013 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_ICMP \ + (0x0003 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_ICMP \ + (0x0003 | ENETC_PKT_TYPE_IPV6) + +/* PCI device info */ +struct enetc_hw { + void *reg; /* SI registers, used by all PCI functions */ + void *port; /* Port registers, PF only */ + void *global; /* IP global registers, PF only */ +}; + +struct enetc_eth_mac_info { + uint8_t addr[RTE_ETHER_ADDR_LEN]; + uint8_t perm_addr[RTE_ETHER_ADDR_LEN]; + uint8_t get_link_status; +}; + +struct enetc_eth_hw { + struct rte_eth_dev *ndev; + struct enetc_hw hw; + uint16_t device_id; + uint16_t vendor_id; + uint8_t revision_id; + struct enetc_eth_mac_info mac; +}; + +/* Transmit Descriptor */ +struct enetc_tx_desc { + uint64_t addr; + uint16_t frm_len; + uint16_t buf_len; + uint32_t flags_errors; +}; + +/* TX Buffer Descriptors (BD) */ +struct enetc_tx_bd { + uint64_t addr; + uint16_t buf_len; + uint16_t frm_len; + uint16_t err_csum; + uint16_t flags; +}; + +/* RX buffer descriptor */ +union enetc_rx_bd { + struct { + uint64_t addr; + uint8_t reserved[8]; + } w; + struct { + uint16_t inet_csum; + uint16_t parse_summary; + uint32_t rss_hash; + uint16_t buf_len; + uint16_t vlan_opt; + union { + struct { + uint16_t flags; + uint16_t error; + }; + uint32_t lstatus; + }; + } r; +}; + +#endif diff --git a/src/spdk/dpdk/drivers/net/enetc/enetc.h b/src/spdk/dpdk/drivers/net/enetc/enetc.h new file mode 100644 index 000000000..14ef3bc18 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/enetc.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2019 NXP + */ + +#ifndef _ENETC_H_ +#define _ENETC_H_ + +#include <rte_time.h> + +#include "base/enetc_hw.h" + +#define PCI_VENDOR_ID_FREESCALE 0x1957 + +/* Max TX rings per ENETC. */ +#define MAX_TX_RINGS 2 + +/* Max RX rings per ENTEC. */ +#define MAX_RX_RINGS 1 + +/* Max BD counts per Ring. */ +#define MAX_BD_COUNT 64000 +/* Min BD counts per Ring. */ +#define MIN_BD_COUNT 32 +/* BD ALIGN */ +#define BD_ALIGN 8 + +/* minimum frame size supported */ +#define ENETC_MAC_MINFRM_SIZE 68 +/* maximum frame size supported */ +#define ENETC_MAC_MAXFRM_SIZE 9600 + +/* + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) + +/* + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((uint32_t)(n)) + +#define ENETC_TXBD(BDR, i) (&(((struct enetc_tx_bd *)((BDR).bd_base))[i])) +#define ENETC_RXBD(BDR, i) (&(((union enetc_rx_bd *)((BDR).bd_base))[i])) + +struct enetc_swbd { + struct rte_mbuf *buffer_addr; +}; + +struct enetc_bdr { + void *bd_base; /* points to Rx or Tx BD ring */ + struct enetc_swbd *q_swbd; + union { + void *tcir; + void *rcir; + }; + int bd_count; /* # of BDs */ + int next_to_use; + int next_to_clean; + uint16_t index; + uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */ + union { + void *tcisr; /* Tx */ + int next_to_alloc; /* Rx */ + }; + struct rte_mempool *mb_pool; /* mbuf pool to populate RX ring. */ + struct rte_eth_dev *ndev; +}; + +/* + * Structure to store private data for each driver instance (for each port). + */ +struct enetc_eth_adapter { + struct rte_eth_dev *ndev; + struct enetc_eth_hw hw; +}; + +#define ENETC_DEV_PRIVATE(adapter) \ + ((struct enetc_eth_adapter *)adapter) + +#define ENETC_DEV_PRIVATE_TO_HW(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->hw) + +#define ENETC_DEV_PRIVATE_TO_STATS(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->stats) + +#define ENETC_DEV_PRIVATE_TO_INTR(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->intr) + +/* + * RX/TX ENETC function prototypes + */ +uint16_t enetc_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); +uint16_t enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts); + + +int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt); + +static inline int +enetc_bd_unused(struct enetc_bdr *bdr) +{ + if (bdr->next_to_clean > bdr->next_to_use) + return bdr->next_to_clean - bdr->next_to_use - 1; + + return bdr->bd_count + bdr->next_to_clean - bdr->next_to_use - 1; +} +#endif /* _ENETC_H_ */ diff --git a/src/spdk/dpdk/drivers/net/enetc/enetc_ethdev.c b/src/spdk/dpdk/drivers/net/enetc/enetc_ethdev.c new file mode 100644 index 000000000..1716e11dd --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/enetc_ethdev.c @@ -0,0 +1,960 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2020 NXP + */ + +#include <stdbool.h> +#include <rte_ethdev_pci.h> +#include <rte_random.h> +#include <dpaax_iova_table.h> + +#include "enetc_logs.h" +#include "enetc.h" + +int enetc_logtype_pmd; + +static int +enetc_dev_start(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t val; + + PMD_INIT_FUNC_TRACE(); + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); + + /* Enable port */ + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN); + + /* set auto-speed for RGMII */ + if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_RGAUTO); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_RGAUTO); + } + if (enetc_global_rd(enetc_hw, + ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) { + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_XGMII); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_XGMII); + } + + return 0; +} + +static void +enetc_dev_stop(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t val; + + PMD_INIT_FUNC_TRACE(); + /* Disable port */ + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN)); + + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); +} + +static const uint32_t * +enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP, + RTE_PTYPE_L4_SCTP, + RTE_PTYPE_L4_ICMP, + RTE_PTYPE_UNKNOWN + }; + + return ptypes; +} + +/* return 0 means link status changed, -1 means not changed */ +static int +enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + struct rte_eth_link link; + uint32_t status; + + PMD_INIT_FUNC_TRACE(); + + memset(&link, 0, sizeof(link)); + + status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS); + + if (status & ENETC_LINK_MODE) + link.link_duplex = ETH_LINK_FULL_DUPLEX; + else + link.link_duplex = ETH_LINK_HALF_DUPLEX; + + if (status & ENETC_LINK_STATUS) + link.link_status = ETH_LINK_UP; + else + link.link_status = ETH_LINK_DOWN; + + switch (status & ENETC_LINK_SPEED_MASK) { + case ENETC_LINK_SPEED_1G: + link.link_speed = ETH_SPEED_NUM_1G; + break; + + case ENETC_LINK_SPEED_100M: + link.link_speed = ETH_SPEED_NUM_100M; + break; + + default: + case ENETC_LINK_SPEED_10M: + link.link_speed = ETH_SPEED_NUM_10M; + } + + return rte_eth_linkstatus_set(dev, &link); +} + +static void +print_ethaddr(const char *name, const struct rte_ether_addr *eth_addr) +{ + char buf[RTE_ETHER_ADDR_FMT_SIZE]; + + rte_ether_format_addr(buf, RTE_ETHER_ADDR_FMT_SIZE, eth_addr); + ENETC_PMD_NOTICE("%s%s\n", name, buf); +} + +static int +enetc_hardware_init(struct enetc_eth_hw *hw) +{ + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t *mac = (uint32_t *)hw->mac.addr; + uint32_t high_mac = 0; + uint16_t low_mac = 0; + + PMD_INIT_FUNC_TRACE(); + /* Calculating and storing the base HW addresses */ + hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE); + hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); + + /* WA for Rx lock-up HW erratum */ + enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1); + + /* set ENETC transaction flags to coherent, don't allocate. + * BD writes merge with surrounding cache line data, frame data writes + * overwrite cache line. + */ + enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT); + + /* Enabling Station Interface */ + enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN); + + *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0)); + high_mac = (uint32_t)*mac; + mac++; + *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0)); + low_mac = (uint16_t)*mac; + + if ((high_mac | low_mac) == 0) { + char *first_byte; + + ENETC_PMD_NOTICE("MAC is not available for this SI, " + "set random MAC\n"); + mac = (uint32_t *)hw->mac.addr; + *mac = (uint32_t)rte_rand(); + first_byte = (char *)mac; + *first_byte &= 0xfe; /* clear multicast bit */ + *first_byte |= 0x02; /* set local assignment bit (IEEE802) */ + + enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), *mac); + mac++; + *mac = (uint16_t)rte_rand(); + enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), *mac); + print_ethaddr("New address: ", + (const struct rte_ether_addr *)hw->mac.addr); + } + + return 0; +} + +static int +enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_dev_info *dev_info) +{ + PMD_INIT_FUNC_TRACE(); + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = MAX_BD_COUNT, + .nb_min = MIN_BD_COUNT, + .nb_align = BD_ALIGN, + }; + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = MAX_BD_COUNT, + .nb_min = MIN_BD_COUNT, + .nb_align = BD_ALIGN, + }; + dev_info->max_rx_queues = MAX_RX_RINGS; + dev_info->max_tx_queues = MAX_TX_RINGS; + dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE; + dev_info->rx_offload_capa = + (DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_KEEP_CRC | + DEV_RX_OFFLOAD_JUMBO_FRAME); + + return 0; +} + +static int +enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc) +{ + int size; + + size = nb_desc * sizeof(struct enetc_swbd); + txr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); + if (txr->q_swbd == NULL) + return -ENOMEM; + + size = nb_desc * sizeof(struct enetc_tx_bd); + txr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); + if (txr->bd_base == NULL) { + rte_free(txr->q_swbd); + txr->q_swbd = NULL; + return -ENOMEM; + } + + txr->bd_count = nb_desc; + txr->next_to_clean = 0; + txr->next_to_use = 0; + + return 0; +} + +static void +enetc_free_bdr(struct enetc_bdr *rxr) +{ + rte_free(rxr->q_swbd); + rte_free(rxr->bd_base); + rxr->q_swbd = NULL; + rxr->bd_base = NULL; +} + +static void +enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) +{ + int idx = tx_ring->index; + phys_addr_t bd_address; + + bd_address = (phys_addr_t) + rte_mem_virt2iova((const void *)tx_ring->bd_base); + enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, + lower_32_bits((uint64_t)bd_address)); + enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, + upper_32_bits((uint64_t)bd_address)); + enetc_txbdr_wr(hw, idx, ENETC_TBLENR, + ENETC_RTBLENR_LEN(tx_ring->bd_count)); + + enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0); + enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0); + tx_ring->tcir = (void *)((size_t)hw->reg + + ENETC_BDR(TX, idx, ENETC_TBCIR)); + tx_ring->tcisr = (void *)((size_t)hw->reg + + ENETC_BDR(TX, idx, ENETC_TBCISR)); +} + +static int +enetc_tx_queue_setup(struct rte_eth_dev *dev, + uint16_t queue_idx, + uint16_t nb_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_txconf *tx_conf) +{ + int err = 0; + struct enetc_bdr *tx_ring; + struct rte_eth_dev_data *data = dev->data; + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(data->dev_private); + + PMD_INIT_FUNC_TRACE(); + if (nb_desc > MAX_BD_COUNT) + return -1; + + tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); + if (tx_ring == NULL) { + ENETC_PMD_ERR("Failed to allocate TX ring memory"); + err = -ENOMEM; + return -1; + } + + err = enetc_alloc_txbdr(tx_ring, nb_desc); + if (err) + goto fail; + + tx_ring->index = queue_idx; + tx_ring->ndev = dev; + enetc_setup_txbdr(&priv->hw.hw, tx_ring); + data->tx_queues[queue_idx] = tx_ring; + + if (!tx_conf->tx_deferred_start) { + /* enable ring */ + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, + ENETC_TBMR, ENETC_TBMR_EN); + dev->data->tx_queue_state[tx_ring->index] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + dev->data->tx_queue_state[tx_ring->index] = + RTE_ETH_QUEUE_STATE_STOPPED; + } + + return 0; +fail: + rte_free(tx_ring); + + return err; +} + +static void +enetc_tx_queue_release(void *txq) +{ + if (txq == NULL) + return; + + struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq; + struct enetc_eth_hw *eth_hw = + ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private); + struct enetc_hw *hw; + struct enetc_swbd *tx_swbd; + int i; + uint32_t val; + + /* Disable the ring */ + hw = ð_hw->hw; + val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR); + val &= (~ENETC_TBMR_EN); + enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val); + + /* clean the ring*/ + i = tx_ring->next_to_clean; + tx_swbd = &tx_ring->q_swbd[i]; + while (tx_swbd->buffer_addr != NULL) { + rte_pktmbuf_free(tx_swbd->buffer_addr); + tx_swbd->buffer_addr = NULL; + tx_swbd++; + i++; + if (unlikely(i == tx_ring->bd_count)) { + i = 0; + tx_swbd = &tx_ring->q_swbd[i]; + } + } + + enetc_free_bdr(tx_ring); + rte_free(tx_ring); +} + +static int +enetc_alloc_rxbdr(struct enetc_bdr *rxr, + uint16_t nb_rx_desc) +{ + int size; + + size = nb_rx_desc * sizeof(struct enetc_swbd); + rxr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); + if (rxr->q_swbd == NULL) + return -ENOMEM; + + size = nb_rx_desc * sizeof(union enetc_rx_bd); + rxr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); + if (rxr->bd_base == NULL) { + rte_free(rxr->q_swbd); + rxr->q_swbd = NULL; + return -ENOMEM; + } + + rxr->bd_count = nb_rx_desc; + rxr->next_to_clean = 0; + rxr->next_to_use = 0; + rxr->next_to_alloc = 0; + + return 0; +} + +static void +enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, + struct rte_mempool *mb_pool) +{ + int idx = rx_ring->index; + uint16_t buf_size; + phys_addr_t bd_address; + + bd_address = (phys_addr_t) + rte_mem_virt2iova((const void *)rx_ring->bd_base); + enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, + lower_32_bits((uint64_t)bd_address)); + enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, + upper_32_bits((uint64_t)bd_address)); + enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, + ENETC_RTBLENR_LEN(rx_ring->bd_count)); + + rx_ring->mb_pool = mb_pool; + rx_ring->rcir = (void *)((size_t)hw->reg + + ENETC_BDR(RX, idx, ENETC_RBCIR)); + enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring))); + buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) - + RTE_PKTMBUF_HEADROOM); + enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size); + enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); +} + +static int +enetc_rx_queue_setup(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint16_t nb_rx_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool) +{ + int err = 0; + struct enetc_bdr *rx_ring; + struct rte_eth_dev_data *data = dev->data; + struct enetc_eth_adapter *adapter = + ENETC_DEV_PRIVATE(data->dev_private); + uint64_t rx_offloads = data->dev_conf.rxmode.offloads; + + PMD_INIT_FUNC_TRACE(); + if (nb_rx_desc > MAX_BD_COUNT) + return -1; + + rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); + if (rx_ring == NULL) { + ENETC_PMD_ERR("Failed to allocate RX ring memory"); + err = -ENOMEM; + return err; + } + + err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc); + if (err) + goto fail; + + rx_ring->index = rx_queue_id; + rx_ring->ndev = dev; + enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool); + data->rx_queues[rx_queue_id] = rx_ring; + + if (!rx_conf->rx_deferred_start) { + /* enable ring */ + enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR, + ENETC_RBMR_EN); + dev->data->rx_queue_state[rx_ring->index] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + dev->data->rx_queue_state[rx_ring->index] = + RTE_ETH_QUEUE_STATE_STOPPED; + } + + rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ? + RTE_ETHER_CRC_LEN : 0); + + return 0; +fail: + rte_free(rx_ring); + + return err; +} + +static void +enetc_rx_queue_release(void *rxq) +{ + if (rxq == NULL) + return; + + struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; + struct enetc_eth_hw *eth_hw = + ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private); + struct enetc_swbd *q_swbd; + struct enetc_hw *hw; + uint32_t val; + int i; + + /* Disable the ring */ + hw = ð_hw->hw; + val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR); + val &= (~ENETC_RBMR_EN); + enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val); + + /* Clean the ring */ + i = rx_ring->next_to_clean; + q_swbd = &rx_ring->q_swbd[i]; + while (i != rx_ring->next_to_use) { + rte_pktmbuf_free(q_swbd->buffer_addr); + q_swbd->buffer_addr = NULL; + q_swbd++; + i++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + q_swbd = &rx_ring->q_swbd[i]; + } + } + + enetc_free_bdr(rx_ring); + rte_free(rx_ring); +} + +static +int enetc_stats_get(struct rte_eth_dev *dev, + struct rte_eth_stats *stats) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + + /* Total received packets, bad + good, if we want to get counters of + * only good received packets then use ENETC_PM0_RFRM, + * ENETC_PM0_TFRM registers. + */ + stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT); + stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT); + stats->ibytes = enetc_port_rd(enetc_hw, ENETC_PM0_REOCT); + stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT); + /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without + * truncated packets + */ + stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP); + stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR); + stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR); + + return 0; +} + +static int +enetc_stats_reset(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + + enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS); + + return 0; +} + +static void +enetc_dev_close(struct rte_eth_dev *dev) +{ + uint16_t i; + + PMD_INIT_FUNC_TRACE(); + enetc_dev_stop(dev); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + enetc_rx_queue_release(dev->data->rx_queues[i]); + dev->data->rx_queues[i] = NULL; + } + dev->data->nb_rx_queues = 0; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + enetc_tx_queue_release(dev->data->tx_queues[i]); + dev->data->tx_queues[i] = NULL; + } + dev->data->nb_tx_queues = 0; +} + +static int +enetc_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + + /* Setting to enable promiscuous mode*/ + psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); + + return 0; +} + +static int +enetc_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + /* Setting to disable promiscuous mode for SI0*/ + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + psipmr &= (~ENETC_PSIPMR_SET_UP(0)); + + if (dev->data->all_multicast == 0) + psipmr &= (~ENETC_PSIPMR_SET_MP(0)); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); + + return 0; +} + +static int +enetc_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + + /* Setting to enable allmulticast mode for SI0*/ + psipmr |= ENETC_PSIPMR_SET_MP(0); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); + + return 0; +} + +static int +enetc_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + if (dev->data->promiscuous == 1) + return 0; /* must remain in all_multicast mode */ + + /* Setting to disable all multicast mode for SI0*/ + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) & + ~(ENETC_PSIPMR_SET_MP(0)); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); + + return 0; +} + +static int +enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; + + /* check that mtu is within the allowed range */ + if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE) + return -EINVAL; + + /* + * Refuse mtu that requires the support of scattered packets + * when this feature has not been enabled before. + */ + if (dev->data->min_rx_buf_size && + !dev->data->scattered_rx && frame_size > + dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { + ENETC_PMD_ERR("SG not enabled, will not fit in one buffer"); + return -EINVAL; + } + + if (frame_size > RTE_ETHER_MAX_LEN) + dev->data->dev_conf.rxmode.offloads &= + DEV_RX_OFFLOAD_JUMBO_FRAME; + else + dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_JUMBO_FRAME; + + enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE); + enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE); + + dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + + /*setting the MTU*/ + enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) | + ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE)); + + return 0; +} + +static int +enetc_dev_configure(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + struct rte_eth_conf *eth_conf = &dev->data->dev_conf; + uint64_t rx_offloads = eth_conf->rxmode.offloads; + uint32_t checksum = L3_CKSUM | L4_CKSUM; + + PMD_INIT_FUNC_TRACE(); + + if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { + uint32_t max_len; + + max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; + + enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, + ENETC_SET_MAXFRM(max_len)); + enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), + ENETC_MAC_MAXFRM_SIZE); + enetc_port_wr(enetc_hw, ENETC_PTXMBAR, + 2 * ENETC_MAC_MAXFRM_SIZE); + dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - + RTE_ETHER_CRC_LEN; + } + + if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) { + int config; + + config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + config |= ENETC_PM0_CRC; + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config); + } + + if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) + checksum &= ~L3_CKSUM; + + if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM)) + checksum &= ~L4_CKSUM; + + enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum); + + + return 0; +} + +static int +enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *rx_ring; + uint32_t rx_data; + + rx_ring = dev->data->rx_queues[qidx]; + if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { + rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, + ENETC_RBMR); + rx_data = rx_data | ENETC_RBMR_EN; + enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, + rx_data); + dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; + } + + return 0; +} + +static int +enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *rx_ring; + uint32_t rx_data; + + rx_ring = dev->data->rx_queues[qidx]; + if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { + rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, + ENETC_RBMR); + rx_data = rx_data & (~ENETC_RBMR_EN); + enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, + rx_data); + dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; + } + + return 0; +} + +static int +enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *tx_ring; + uint32_t tx_data; + + tx_ring = dev->data->tx_queues[qidx]; + if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { + tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, + ENETC_TBMR); + tx_data = tx_data | ENETC_TBMR_EN; + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, + tx_data); + dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; + } + + return 0; +} + +static int +enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *tx_ring; + uint32_t tx_data; + + tx_ring = dev->data->tx_queues[qidx]; + if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { + tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, + ENETC_TBMR); + tx_data = tx_data & (~ENETC_TBMR_EN); + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, + tx_data); + dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; + } + + return 0; +} + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_enetc_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +/* Features supported by this driver */ +static const struct eth_dev_ops enetc_ops = { + .dev_configure = enetc_dev_configure, + .dev_start = enetc_dev_start, + .dev_stop = enetc_dev_stop, + .dev_close = enetc_dev_close, + .link_update = enetc_link_update, + .stats_get = enetc_stats_get, + .stats_reset = enetc_stats_reset, + .promiscuous_enable = enetc_promiscuous_enable, + .promiscuous_disable = enetc_promiscuous_disable, + .allmulticast_enable = enetc_allmulticast_enable, + .allmulticast_disable = enetc_allmulticast_disable, + .dev_infos_get = enetc_dev_infos_get, + .mtu_set = enetc_mtu_set, + .rx_queue_setup = enetc_rx_queue_setup, + .rx_queue_start = enetc_rx_queue_start, + .rx_queue_stop = enetc_rx_queue_stop, + .rx_queue_release = enetc_rx_queue_release, + .tx_queue_setup = enetc_tx_queue_setup, + .tx_queue_start = enetc_tx_queue_start, + .tx_queue_stop = enetc_tx_queue_stop, + .tx_queue_release = enetc_tx_queue_release, + .dev_supported_ptypes_get = enetc_supported_ptypes_get, +}; + +/** + * Initialisation of the enetc device + * + * @param eth_dev + * - Pointer to the structure rte_eth_dev + * + * @return + * - On success, zero. + * - On failure, negative value. + */ +static int +enetc_dev_init(struct rte_eth_dev *eth_dev) +{ + int error = 0; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + eth_dev->dev_ops = &enetc_ops; + eth_dev->rx_pkt_burst = &enetc_recv_pkts; + eth_dev->tx_pkt_burst = &enetc_xmit_pkts; + + /* Retrieving and storing the HW base address of device */ + hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; + hw->device_id = pci_dev->id.device_id; + + error = enetc_hardware_init(hw); + if (error != 0) { + ENETC_PMD_ERR("Hardware initialization failed"); + return -1; + } + + /* Allocate memory for storing MAC addresses */ + eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", + RTE_ETHER_ADDR_LEN, 0); + if (!eth_dev->data->mac_addrs) { + ENETC_PMD_ERR("Failed to allocate %d bytes needed to " + "store MAC addresses", + RTE_ETHER_ADDR_LEN * 1); + error = -ENOMEM; + return -1; + } + + /* Copy the permanent MAC address */ + rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, + ð_dev->data->mac_addrs[0]); + + /* Set MTU */ + enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM, + ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN)); + eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - + RTE_ETHER_CRC_LEN; + + if (rte_eal_iova_mode() == RTE_IOVA_PA) + dpaax_iova_table_populate(); + + ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", + eth_dev->data->port_id, pci_dev->id.vendor_id, + pci_dev->id.device_id); + return 0; +} + +static int +enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); + + if (rte_eal_iova_mode() == RTE_IOVA_PA) + dpaax_iova_table_depopulate(); + + return 0; +} + +static int +enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct enetc_eth_adapter), + enetc_dev_init); +} + +static int +enetc_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit); +} + +static struct rte_pci_driver rte_enetc_pmd = { + .id_table = pci_id_enetc_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = enetc_pci_probe, + .remove = enetc_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map); +RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci"); + +RTE_INIT(enetc_pmd_init_log) +{ + enetc_logtype_pmd = rte_log_register("pmd.net.enetc"); + if (enetc_logtype_pmd >= 0) + rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE); +} diff --git a/src/spdk/dpdk/drivers/net/enetc/enetc_logs.h b/src/spdk/dpdk/drivers/net/enetc/enetc_logs.h new file mode 100644 index 000000000..0976d42de --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/enetc_logs.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#ifndef _ENETC_LOGS_H_ +#define _ENETC_LOGS_H_ + +extern int enetc_logtype_pmd; + +#define ENETC_PMD_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, enetc_logtype_pmd, "enetc_net: " \ + fmt "\n", ##args) + +#define ENETC_PMD_DEBUG(fmt, args...) \ + rte_log(RTE_LOG_DEBUG, enetc_logtype_pmd, "enetc_net: %s(): "\ + fmt "\n", __func__, ##args) + +#define PMD_INIT_FUNC_TRACE() ENETC_PMD_DEBUG(">>") + +#define ENETC_PMD_CRIT(fmt, args...) \ + ENETC_PMD_LOG(CRIT, fmt, ## args) +#define ENETC_PMD_INFO(fmt, args...) \ + ENETC_PMD_LOG(INFO, fmt, ## args) +#define ENETC_PMD_NOTICE(fmt, args...) \ + ENETC_PMD_LOG(NOTICE, fmt, ## args) +#define ENETC_PMD_ERR(fmt, args...) \ + ENETC_PMD_LOG(ERR, fmt, ## args) +#define ENETC_PMD_WARN(fmt, args...) \ + ENETC_PMD_LOG(WARNING, fmt, ## args) + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define ENETC_PMD_DP_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt, ## args) + +#define ENETC_PMD_DP_DEBUG(fmt, args...) \ + ENETC_PMD_DP_LOG(DEBUG, fmt, ## args) +#define ENETC_PMD_DP_INFO(fmt, args...) \ + ENETC_PMD_DP_LOG(INFO, fmt, ## args) +#define ENETC_PMD_DP_WARN(fmt, args...) \ + ENETC_PMD_DP_LOG(WARNING, fmt, ## args) + +#endif /* _ENETC_LOGS_H_*/ diff --git a/src/spdk/dpdk/drivers/net/enetc/enetc_rxtx.c b/src/spdk/dpdk/drivers/net/enetc/enetc_rxtx.c new file mode 100644 index 000000000..412322523 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/enetc_rxtx.c @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018-2020 NXP + */ + +#include <stdbool.h> +#include <stdint.h> +#include <unistd.h> + +#include "rte_ethdev.h" +#include "rte_malloc.h" +#include "rte_memzone.h" + +#include "base/enetc_hw.h" +#include "enetc.h" +#include "enetc_logs.h" + +#define ENETC_CACHE_LINE_RXBDS (RTE_CACHE_LINE_SIZE / \ + sizeof(union enetc_rx_bd)) +#define ENETC_RXBD_BUNDLE 16 /* Number of buffers to allocate at once */ + +static int +enetc_clean_tx_ring(struct enetc_bdr *tx_ring) +{ + int tx_frm_cnt = 0; + struct enetc_swbd *tx_swbd, *tx_swbd_base; + int i, hwci, bd_count; + struct rte_mbuf *m[ENETC_RXBD_BUNDLE]; + + /* we don't need barriers here, we just want a relatively current value + * from HW. + */ + hwci = (int)(rte_read32_relaxed(tx_ring->tcisr) & + ENETC_TBCISR_IDX_MASK); + + tx_swbd_base = tx_ring->q_swbd; + bd_count = tx_ring->bd_count; + i = tx_ring->next_to_clean; + tx_swbd = &tx_swbd_base[i]; + + /* we're only reading the CI index once here, which means HW may update + * it while we're doing clean-up. We could read the register in a loop + * but for now I assume it's OK to leave a few Tx frames for next call. + * The issue with reading the register in a loop is that we're stalling + * here trying to catch up with HW which keeps sending traffic as long + * as it has traffic to send, so in effect we could be waiting here for + * the Tx ring to be drained by HW, instead of us doing Rx in that + * meantime. + */ + while (i != hwci) { + /* It seems calling rte_pktmbuf_free is wasting a lot of cycles, + * make a list and call _free when it's done. + */ + if (tx_frm_cnt == ENETC_RXBD_BUNDLE) { + rte_pktmbuf_free_bulk(m, tx_frm_cnt); + tx_frm_cnt = 0; + } + + m[tx_frm_cnt] = tx_swbd->buffer_addr; + tx_swbd->buffer_addr = NULL; + + i++; + tx_swbd++; + if (unlikely(i == bd_count)) { + i = 0; + tx_swbd = tx_swbd_base; + } + + tx_frm_cnt++; + } + + if (tx_frm_cnt) + rte_pktmbuf_free_bulk(m, tx_frm_cnt); + + tx_ring->next_to_clean = i; + + return 0; +} + +uint16_t +enetc_xmit_pkts(void *tx_queue, + struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + struct enetc_swbd *tx_swbd; + int i, start, bds_to_use; + struct enetc_tx_bd *txbd; + struct enetc_bdr *tx_ring = (struct enetc_bdr *)tx_queue; + + i = tx_ring->next_to_use; + + bds_to_use = enetc_bd_unused(tx_ring); + if (bds_to_use < nb_pkts) + nb_pkts = bds_to_use; + + start = 0; + while (nb_pkts--) { + tx_ring->q_swbd[i].buffer_addr = tx_pkts[start]; + txbd = ENETC_TXBD(*tx_ring, i); + tx_swbd = &tx_ring->q_swbd[i]; + txbd->frm_len = tx_pkts[start]->pkt_len; + txbd->buf_len = txbd->frm_len; + txbd->flags = rte_cpu_to_le_16(ENETC_TXBD_FLAGS_F); + txbd->addr = (uint64_t)(uintptr_t) + rte_cpu_to_le_64((size_t)tx_swbd->buffer_addr->buf_iova + + tx_swbd->buffer_addr->data_off); + i++; + start++; + if (unlikely(i == tx_ring->bd_count)) + i = 0; + } + + /* we're only cleaning up the Tx ring here, on the assumption that + * software is slower than hardware and hardware completed sending + * older frames out by now. + * We're also cleaning up the ring before kicking off Tx for the new + * batch to minimize chances of contention on the Tx ring + */ + enetc_clean_tx_ring(tx_ring); + + tx_ring->next_to_use = i; + enetc_wr_reg(tx_ring->tcir, i); + return start; +} + +int +enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt) +{ + struct enetc_swbd *rx_swbd; + union enetc_rx_bd *rxbd; + int i, j, k = ENETC_RXBD_BUNDLE; + struct rte_mbuf *m[ENETC_RXBD_BUNDLE]; + struct rte_mempool *mb_pool; + + i = rx_ring->next_to_use; + mb_pool = rx_ring->mb_pool; + rx_swbd = &rx_ring->q_swbd[i]; + rxbd = ENETC_RXBD(*rx_ring, i); + for (j = 0; j < buff_cnt; j++) { + /* bulk alloc for the next up to 8 BDs */ + if (k == ENETC_RXBD_BUNDLE) { + k = 0; + int m_cnt = RTE_MIN(buff_cnt - j, ENETC_RXBD_BUNDLE); + + if (rte_pktmbuf_alloc_bulk(mb_pool, m, m_cnt)) + return -1; + } + + rx_swbd->buffer_addr = m[k]; + rxbd->w.addr = (uint64_t)(uintptr_t) + rx_swbd->buffer_addr->buf_iova + + rx_swbd->buffer_addr->data_off; + /* clear 'R" as well */ + rxbd->r.lstatus = 0; + rx_swbd++; + rxbd++; + i++; + k++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + rxbd = ENETC_RXBD(*rx_ring, 0); + rx_swbd = &rx_ring->q_swbd[i]; + } + } + + if (likely(j)) { + rx_ring->next_to_alloc = i; + rx_ring->next_to_use = i; + enetc_wr_reg(rx_ring->rcir, i); + } + + return j; +} + +static inline void enetc_slow_parsing(struct rte_mbuf *m, + uint64_t parse_results) +{ + m->ol_flags &= ~(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD); + + switch (parse_results) { + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV4: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4; + m->ol_flags |= PKT_RX_IP_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV6: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6; + m->ol_flags |= PKT_RX_IP_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV4_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_TCP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV6_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_TCP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV4_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_UDP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV6_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_UDP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV4_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_SCTP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV6_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_SCTP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV4_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_ICMP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + case ENETC_PARSE_ERROR | ENETC_PKT_TYPE_IPV6_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_ICMP; + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | + PKT_RX_L4_CKSUM_BAD; + return; + /* More switch cases can be added */ + default: + m->packet_type = RTE_PTYPE_UNKNOWN; + m->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN | + PKT_RX_L4_CKSUM_UNKNOWN; + } +} + + +static inline void __rte_hot +enetc_dev_rx_parse(struct rte_mbuf *m, uint16_t parse_results) +{ + ENETC_PMD_DP_DEBUG("parse summary = 0x%x ", parse_results); + m->ol_flags |= PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD; + + switch (parse_results) { + case ENETC_PKT_TYPE_ETHER: + m->packet_type = RTE_PTYPE_L2_ETHER; + return; + case ENETC_PKT_TYPE_IPV4: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4; + return; + case ENETC_PKT_TYPE_IPV6: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6; + return; + case ENETC_PKT_TYPE_IPV4_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_TCP; + return; + case ENETC_PKT_TYPE_IPV6_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_TCP; + return; + case ENETC_PKT_TYPE_IPV4_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_UDP; + return; + case ENETC_PKT_TYPE_IPV6_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_UDP; + return; + case ENETC_PKT_TYPE_IPV4_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_SCTP; + return; + case ENETC_PKT_TYPE_IPV6_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_SCTP; + return; + case ENETC_PKT_TYPE_IPV4_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | + RTE_PTYPE_L4_ICMP; + return; + case ENETC_PKT_TYPE_IPV6_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | + RTE_PTYPE_L4_ICMP; + return; + /* More switch cases can be added */ + default: + enetc_slow_parsing(m, parse_results); + } + +} + +static int +enetc_clean_rx_ring(struct enetc_bdr *rx_ring, + struct rte_mbuf **rx_pkts, + int work_limit) +{ + int rx_frm_cnt = 0; + int cleaned_cnt, i, bd_count; + struct enetc_swbd *rx_swbd; + union enetc_rx_bd *rxbd; + + /* next descriptor to process */ + i = rx_ring->next_to_clean; + /* next descriptor to process */ + rxbd = ENETC_RXBD(*rx_ring, i); + rte_prefetch0(rxbd); + bd_count = rx_ring->bd_count; + /* LS1028A does not have platform cache so any software access following + * a hardware write will go directly to DDR. Latency of such a read is + * in excess of 100 core cycles, so try to prefetch more in advance to + * mitigate this. + * How much is worth prefetching really depends on traffic conditions. + * With congested Rx this could go up to 4 cache lines or so. But if + * software keeps up with hardware and follows behind Rx PI by a cache + * line or less then it's harmful in terms of performance to cache more. + * We would only prefetch BDs that have yet to be written by ENETC, + * which will have to be evicted again anyway. + */ + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS) % bd_count)); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS * 2) % bd_count)); + + cleaned_cnt = enetc_bd_unused(rx_ring); + rx_swbd = &rx_ring->q_swbd[i]; + while (likely(rx_frm_cnt < work_limit)) { + uint32_t bd_status; + + bd_status = rte_le_to_cpu_32(rxbd->r.lstatus); + if (!bd_status) + break; + + rx_swbd->buffer_addr->pkt_len = rxbd->r.buf_len - + rx_ring->crc_len; + rx_swbd->buffer_addr->data_len = rxbd->r.buf_len - + rx_ring->crc_len; + rx_swbd->buffer_addr->hash.rss = rxbd->r.rss_hash; + rx_swbd->buffer_addr->ol_flags = 0; + enetc_dev_rx_parse(rx_swbd->buffer_addr, + rxbd->r.parse_summary); + rx_pkts[rx_frm_cnt] = rx_swbd->buffer_addr; + cleaned_cnt++; + rx_swbd++; + i++; + if (unlikely(i == rx_ring->bd_count)) { + i = 0; + rx_swbd = &rx_ring->q_swbd[i]; + } + rxbd = ENETC_RXBD(*rx_ring, i); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS) % + bd_count)); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS * 2) % + bd_count)); + + rx_frm_cnt++; + } + + rx_ring->next_to_clean = i; + enetc_refill_rx_ring(rx_ring, cleaned_cnt); + + return rx_frm_cnt; +} + +uint16_t +enetc_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, + uint16_t nb_pkts) +{ + struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; + + return enetc_clean_rx_ring(rx_ring, rx_pkts, nb_pkts); +} diff --git a/src/spdk/dpdk/drivers/net/enetc/meson.build b/src/spdk/dpdk/drivers/net/enetc/meson.build new file mode 100644 index 000000000..bea54bea8 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/meson.build @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if not is_linux + build = false + reason = 'only supported on linux' +endif + +deps += ['common_dpaax'] +sources = files('enetc_ethdev.c', + 'enetc_rxtx.c') + +includes += include_directories('base') diff --git a/src/spdk/dpdk/drivers/net/enetc/rte_pmd_enetc_version.map b/src/spdk/dpdk/drivers/net/enetc/rte_pmd_enetc_version.map new file mode 100644 index 000000000..f9f17e4f6 --- /dev/null +++ b/src/spdk/dpdk/drivers/net/enetc/rte_pmd_enetc_version.map @@ -0,0 +1,3 @@ +DPDK_20.0 { + local: *; +}; |