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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /drivers/nxp/pmu | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b.tar.xz arm-trusted-firmware-be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b.zip |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/nxp/pmu')
-rw-r--r-- | drivers/nxp/pmu/pmu.c | 45 | ||||
-rw-r--r-- | drivers/nxp/pmu/pmu.mk | 26 |
2 files changed, 71 insertions, 0 deletions
diff --git a/drivers/nxp/pmu/pmu.c b/drivers/nxp/pmu/pmu.c new file mode 100644 index 0000000..2a907c8 --- /dev/null +++ b/drivers/nxp/pmu/pmu.c @@ -0,0 +1,45 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <dcfg.h> +#include <lib/mmio.h> +#include <pmu.h> + +void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr) +{ + uint32_t *cltbenr = NULL; + uint32_t cltbenr_val = 0U; + + cltbenr = (uint32_t *)(nxp_pmu_addr + + CLUST_TIMER_BASE_ENBL_OFFSET); + + cltbenr_val = mmio_read_32((uintptr_t)cltbenr); + + cltbenr_val = cltbenr_val + | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); + + mmio_write_32((uintptr_t)cltbenr, cltbenr_val); + + VERBOSE("Enable cluster time base\n"); +} + +/* + * Enable core timebase. In certain Layerscape SoCs, the clock for each core's + * has an enable bit in the PMU Physical Core Time Base Enable + * Register (PCTBENR), which allows the watchdog to operate. + */ + +void enable_core_tb(uintptr_t nxp_pmu_addr) +{ + uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr + + CORE_TIMEBASE_ENBL_OFFSET); + + mmio_write_32((uintptr_t)pctbenr, 0xff); +} diff --git a/drivers/nxp/pmu/pmu.mk b/drivers/nxp/pmu/pmu.mk new file mode 100644 index 0000000..8d2ef07 --- /dev/null +++ b/drivers/nxp/pmu/pmu.mk @@ -0,0 +1,26 @@ +# +# Copyright 2021 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# +#----------------------------------------------------------------------------- +ifeq (${PMU_ADDED},) + +PMU_ADDED := 1 + +PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/pmu + +PMU_SOURCES += $(PLAT_DRIVERS_PATH)/pmu/pmu.c + +ifeq (${BL_COMM_PMU_NEEDED},yes) +BL_COMMON_SOURCES += ${PMU_SOURCES} +else +ifeq (${BL2_PMU_NEEDED},yes) +BL2_SOURCES += ${PMU_SOURCES} +endif +ifeq (${BL31_PMU_NEEDED},yes) +BL31_SOURCES += ${PMU_SOURCES} +endif +endif +endif +#------------------------------------------------ |