diff options
| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
| commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
| tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /include/drivers/st | |
| parent | Initial commit. (diff) | |
| download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip | |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/drivers/st')
37 files changed, 11749 insertions, 0 deletions
diff --git a/include/drivers/st/bsec.h b/include/drivers/st/bsec.h new file mode 100644 index 0000000..60dcf3c --- /dev/null +++ b/include/drivers/st/bsec.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BSEC_H +#define BSEC_H + +#include <stdbool.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +/* + * IP configuration + */ +#define BSEC_OTP_MASK GENMASK(4, 0) +#define BSEC_OTP_BANK_SHIFT 5 +#define BSEC_TIMEOUT_VALUE 0xFFFF + +/* + * Return status + */ +#define BSEC_OK 0U +#define BSEC_ERROR 0xFFFFFFFFU +#define BSEC_DISTURBED 0xFFFFFFFEU +#define BSEC_INVALID_PARAM 0xFFFFFFFCU +#define BSEC_PROG_FAIL 0xFFFFFFFBU +#define BSEC_LOCK_FAIL 0xFFFFFFFAU +#define BSEC_TIMEOUT 0xFFFFFFF9U +#define BSEC_RETRY 0xFFFFFFF8U +#define BSEC_NOT_SUPPORTED 0xFFFFFFF7U +#define BSEC_WRITE_LOCKED 0xFFFFFFF6U +#define BSEC_ERROR_INVALID_FVR 0xFFFFFFF5U + +/* + * OTP MODE + */ +#define BSEC_MODE_OPEN1 0x00U +#define BSEC_MODE_SECURED 0x01U +#define BSEC_MODE_OPEN2 0x02U +#define BSEC_MODE_INVALID 0x04U + +/* + * OTP Lock services definition. + * Value must corresponding to the bit number in the register. + * Special case: (bit number << 1) for BSEC3. + */ +#define BSEC_LOCK_UPPER_OTP 0x00 +#define BSEC_LOCK_GWLOCK 0x01 +#define BSEC_LOCK_DEBUG 0x02 +#define BSEC_LOCK_PROGRAM 0x03 +#define BSEC_LOCK_KVLOCK 0x04 + +/* + * Values for struct bsec_config::freq + */ +#define FREQ_10_20_MHZ 0x0 +#define FREQ_20_30_MHZ 0x1 +#define FREQ_30_45_MHZ 0x2 +#define FREQ_45_67_MHZ 0x3 + +/* + * Device info structure, providing device-specific functions and a means of + * adding driver-specific state. + */ +struct bsec_config { + uint8_t den_lock; /* + * Debug enable sticky lock + * 1 debug enable is locked until next reset + */ + + /* BSEC2 only */ + uint8_t tread; /* SAFMEM Reading current level default 0 */ + uint8_t pulse_width; /* SAFMEM Programming pulse width default 1 */ + uint8_t freq; /* + * SAFMEM CLOCK see freq value define + * default FREQ_45_67_MHZ + */ + uint8_t power; /* Power up SAFMEM. 1 power up, 0 power off */ + uint8_t prog_lock; /* + * Programming Sticky lock + * 1 programming is locked until next reset + */ + uint8_t upper_otp_lock; /* + * Shadowing of upper OTP sticky lock + * 1 shadowing of upper OTP is locked + * until next reset + */ +}; + +uint32_t bsec_probe(void); +uint32_t bsec_get_base(void); + +uint32_t bsec_set_config(struct bsec_config *cfg); +uint32_t bsec_get_config(struct bsec_config *cfg); + +uint32_t bsec_shadow_register(uint32_t otp); +uint32_t bsec_read_otp(uint32_t *val, uint32_t otp); +uint32_t bsec_write_otp(uint32_t val, uint32_t otp); +uint32_t bsec_program_otp(uint32_t val, uint32_t otp); +uint32_t bsec_permanent_lock_otp(uint32_t otp); + +void bsec_write_debug_conf(uint32_t val); +uint32_t bsec_read_debug_conf(void); + +void bsec_write_scratch(uint32_t val); +uint32_t bsec_read_scratch(void); + +uint32_t bsec_get_status(void); +uint32_t bsec_get_hw_conf(void); +uint32_t bsec_get_version(void); +uint32_t bsec_get_id(void); +uint32_t bsec_get_magic_id(void); + +uint32_t bsec_set_sr_lock(uint32_t otp); +uint32_t bsec_read_sr_lock(uint32_t otp, bool *value); +uint32_t bsec_set_sw_lock(uint32_t otp); +uint32_t bsec_read_sw_lock(uint32_t otp, bool *value); +uint32_t bsec_set_sp_lock(uint32_t otp); +uint32_t bsec_read_sp_lock(uint32_t otp, bool *value); +uint32_t bsec_read_permanent_lock(uint32_t otp, bool *value); +uint32_t bsec_otp_lock(uint32_t service); + +uint32_t bsec_shadow_read_otp(uint32_t *otp_value, uint32_t word); +uint32_t bsec_check_nsec_access_rights(uint32_t otp); + +#endif /* BSEC_H */ diff --git a/include/drivers/st/bsec2_reg.h b/include/drivers/st/bsec2_reg.h new file mode 100644 index 0000000..f895020 --- /dev/null +++ b/include/drivers/st/bsec2_reg.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BSEC2_REG_H +#define BSEC2_REG_H + +#include <lib/utils_def.h> + +/* IP configuration */ +#define ADDR_LOWER_OTP_PERLOCK_SHIFT 0x03 +#define DATA_LOWER_OTP_PERLOCK_BIT 0x03U /* 2 significants bits are used */ +#define DATA_LOWER_OTP_PERLOCK_MASK GENMASK(2, 0) +#define ADDR_UPPER_OTP_PERLOCK_SHIFT 0x04 +#define DATA_UPPER_OTP_PERLOCK_BIT 0x01U /* 1 significants bits are used */ +#define DATA_UPPER_OTP_PERLOCK_MASK GENMASK(3, 0) + +/* BSEC REGISTER OFFSET (base relative) */ +#define BSEC_OTP_CONF_OFF U(0x000) +#define BSEC_OTP_CTRL_OFF U(0x004) +#define BSEC_OTP_WRDATA_OFF U(0x008) +#define BSEC_OTP_STATUS_OFF U(0x00C) +#define BSEC_OTP_LOCK_OFF U(0x010) +#define BSEC_DEN_OFF U(0x014) +#define BSEC_DISTURBED_OFF U(0x01C) +#define BSEC_DISTURBED1_OFF U(0x020) +#define BSEC_DISTURBED2_OFF U(0x024) +#define BSEC_ERROR_OFF U(0x034) +#define BSEC_ERROR1_OFF U(0x038) +#define BSEC_ERROR2_OFF U(0x03C) +#define BSEC_WRLOCK_OFF U(0x04C) /* Safmem permanent lock */ +#define BSEC_WRLOCK1_OFF U(0x050) +#define BSEC_WRLOCK2_OFF U(0x054) +#define BSEC_SPLOCK_OFF U(0x064) /* Program safmem sticky lock */ +#define BSEC_SPLOCK1_OFF U(0x068) +#define BSEC_SPLOCK2_OFF U(0x06C) +#define BSEC_SWLOCK_OFF U(0x07C) /* Write in OTP sticky lock */ +#define BSEC_SWLOCK1_OFF U(0x080) +#define BSEC_SWLOCK2_OFF U(0x084) +#define BSEC_SRLOCK_OFF U(0x094) /* Shadowing sticky lock */ +#define BSEC_SRLOCK1_OFF U(0x098) +#define BSEC_SRLOCK2_OFF U(0x09C) +#define BSEC_JTAG_IN_OFF U(0x0AC) +#define BSEC_JTAG_OUT_OFF U(0x0B0) +#define BSEC_SCRATCH_OFF U(0x0B4) +#define BSEC_OTP_DATA_OFF U(0x200) +#define BSEC_IPHW_CFG_OFF U(0xFF0) +#define BSEC_IPVR_OFF U(0xFF4) +#define BSEC_IP_ID_OFF U(0xFF8) +#define BSEC_IP_MAGIC_ID_OFF U(0xFFC) + +#define BSEC_WRLOCK(n) (BSEC_WRLOCK_OFF + U(0x04) * (n)) +#define BSEC_SPLOCK(n) (BSEC_SPLOCK_OFF + U(0x04) * (n)) +#define BSEC_SWLOCK(n) (BSEC_SWLOCK_OFF + U(0x04) * (n)) +#define BSEC_SRLOCK(n) (BSEC_SRLOCK_OFF + U(0x04) * (n)) + +/* BSEC_CONFIGURATION Register */ +#define BSEC_CONF_POWER_UP_MASK BIT(0) +#define BSEC_CONF_POWER_UP_SHIFT 0 +#define BSEC_CONF_FRQ_MASK GENMASK(2, 1) +#define BSEC_CONF_FRQ_SHIFT 1 +#define BSEC_CONF_PRG_WIDTH_MASK GENMASK(6, 3) +#define BSEC_CONF_PRG_WIDTH_SHIFT 3 +#define BSEC_CONF_TREAD_MASK GENMASK(8, 7) +#define BSEC_CONF_TREAD_SHIFT 7 + +/* BSEC_CONTROL Register */ +#define BSEC_READ 0U +#define BSEC_WRITE BIT(8) +#define BSEC_LOCK BIT(9) + +/* BSEC_OTP_LOCK register */ +#define UPPER_OTP_LOCK_MASK BIT(0) +#define UPPER_OTP_LOCK_SHIFT 0 +#define DENREG_LOCK_MASK BIT(2) +#define DENREG_LOCK_SHIFT 2 +#define GPLOCK_LOCK_MASK BIT(4) +#define GPLOCK_LOCK_SHIFT 4 + +/* BSEC_OTP_STATUS Register */ +#define BSEC_MODE_STATUS_MASK GENMASK(2, 0) +#define BSEC_MODE_SECURE_MASK BIT(0) +#define BSEC_MODE_FULLDBG_MASK BIT(1) +#define BSEC_MODE_INVALID_MASK BIT(2) +#define BSEC_MODE_BUSY_MASK BIT(3) +#define BSEC_MODE_PROGFAIL_MASK BIT(4) +#define BSEC_MODE_PWR_MASK BIT(5) +#define BSEC_MODE_BIST1_LOCK_MASK BIT(6) +#define BSEC_MODE_BIST2_LOCK_MASK BIT(7) + +/* BSEC_DENABLE Register */ +#define BSEC_HDPEN BIT(4) +#define BSEC_SPIDEN BIT(5) +#define BSEC_SPINDEN BIT(6) +#define BSEC_DBGSWGEN BIT(10) +#define BSEC_DEN_ALL_MSK GENMASK(10, 0) + +/* BSEC_FENABLE Register */ +#define BSEC_FEN_ALL_MSK GENMASK(14, 0) + +/* BSEC_IPVR Register */ +#define BSEC_IPVR_MSK GENMASK(7, 0) + +#endif /* BSEC2_REG_H */ diff --git a/include/drivers/st/etzpc.h b/include/drivers/st/etzpc.h new file mode 100644 index 0000000..4cd2b4e --- /dev/null +++ b/include/drivers/st/etzpc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DRIVERS_ST_ETZPC_H +#define DRIVERS_ST_ETZPC_H + +#include <stdbool.h> +#include <stdint.h> + +/* Define security level for each peripheral (DECPROT) */ +enum etzpc_decprot_attributes { + ETZPC_DECPROT_S_RW = 0, + ETZPC_DECPROT_NS_R_S_W = 1, + ETZPC_DECPROT_MCU_ISOLATION = 2, + ETZPC_DECPROT_NS_RW = 3, + ETZPC_DECPROT_MAX = 4, +}; + +void etzpc_configure_decprot(uint32_t decprot_id, + enum etzpc_decprot_attributes decprot_attr); +enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id); +void etzpc_lock_decprot(uint32_t decprot_id); + +void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value); +uint16_t etzpc_get_tzma(uint32_t tzma_id); +void etzpc_lock_tzma(uint32_t tzma_id); +bool etzpc_get_lock_tzma(uint32_t tzma_id); + +uint8_t etzpc_get_num_per_sec(void); +uint8_t etzpc_get_revision(void); +uintptr_t etzpc_get_base_address(void); + +int etzpc_init(void); + +#endif /* DRIVERS_ST_ETZPC_H */ diff --git a/include/drivers/st/regulator.h b/include/drivers/st/regulator.h new file mode 100644 index 0000000..bf583e2 --- /dev/null +++ b/include/drivers/st/regulator.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef REGULATOR_H +#define REGULATOR_H + +#include <platform_def.h> + +#ifndef PLAT_NB_RDEVS +#error "Missing PLAT_NB_RDEVS" +#endif + +/* + * Consumer interface + */ + +/* regulator-always-on : regulator should never be disabled */ +#define REGUL_ALWAYS_ON BIT(0) +/* + * regulator-boot-on: + * It's expected that this regulator was left on by the bootloader. + * The core shouldn't prevent it from being turned off later. + * The regulator is needed to exit from suspend so it is turned on during suspend entry. + */ +#define REGUL_BOOT_ON BIT(1) +/* regulator-over-current-protection: Enable over current protection. */ +#define REGUL_OCP BIT(2) +/* regulator-active-discharge: enable active discharge. */ +#define REGUL_ACTIVE_DISCHARGE BIT(3) +/* regulator-pull-down: Enable pull down resistor when the regulator is disabled. */ +#define REGUL_PULL_DOWN BIT(4) +/* + * st,mask-reset: set mask reset for the regulator, meaning that the regulator + * setting is maintained during pmic reset. + */ +#define REGUL_MASK_RESET BIT(5) +/* st,regulator-sink-source: set the regulator in sink source mode */ +#define REGUL_SINK_SOURCE BIT(6) +/* st,regulator-bypass: set the regulator in bypass mode */ +#define REGUL_ENABLE_BYPASS BIT(7) + +struct rdev *regulator_get_by_name(const char *node_name); + +struct rdev *regulator_get_by_supply_name(const void *fdt, int node, const char *name); + +int regulator_enable(struct rdev *rdev); +int regulator_disable(struct rdev *rdev); +int regulator_is_enabled(const struct rdev *rdev); + +int regulator_set_voltage(struct rdev *rdev, uint16_t volt); +int regulator_set_min_voltage(struct rdev *rdev); +int regulator_get_voltage(const struct rdev *rdev); + +int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count); +void regulator_get_range(const struct rdev *rdev, uint16_t *min_mv, uint16_t *max_mv); +int regulator_set_flag(struct rdev *rdev, uint16_t flag); + +/* + * Driver Interface + */ + +/* set_state() arguments */ +#define STATE_DISABLE false +#define STATE_ENABLE true + +struct regul_description { + const char *node_name; + const struct regul_ops *ops; + const void *driver_data; + const char *supply_name; + const uint32_t enable_ramp_delay; +}; + +struct regul_ops { + int (*set_state)(const struct regul_description *desc, bool state); + int (*get_state)(const struct regul_description *desc); + int (*set_voltage)(const struct regul_description *desc, uint16_t mv); + int (*get_voltage)(const struct regul_description *desc); + int (*list_voltages)(const struct regul_description *desc, + const uint16_t **levels, size_t *count); + int (*set_flag)(const struct regul_description *desc, uint16_t flag); + void (*lock)(const struct regul_description *desc); + void (*unlock)(const struct regul_description *desc); +}; + +int regulator_register(const struct regul_description *desc, int node); + +/* + * Internal regulator structure + * The structure is internal to the core, and the content should not be used + * by a consumer nor a driver. + */ +struct rdev { + const struct regul_description *desc; + + int32_t phandle; + + uint16_t min_mv; + uint16_t max_mv; + + uint16_t flags; + + uint32_t enable_ramp_delay; +}; + +#endif /* REGULATOR_H */ diff --git a/include/drivers/st/regulator_fixed.h b/include/drivers/st/regulator_fixed.h new file mode 100644 index 0000000..b981262 --- /dev/null +++ b/include/drivers/st/regulator_fixed.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef REGULATOR_FIXED_H +#define REGULATOR_FIXED_H + +int fixed_regulator_register(void); + +#endif /* REGULATOR_FIXED_H */ diff --git a/include/drivers/st/stm32_console.h b/include/drivers/st/stm32_console.h new file mode 100644 index 0000000..8d9187d --- /dev/null +++ b/include/drivers/st/stm32_console.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_CONSOLE_H +#define STM32_CONSOLE_H + +#include <drivers/console.h> + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +/* + * Initialize a new STM32 console instance and register it with the console + * framework. The |console| pointer must point to storage that will be valid + * for the lifetime of the console, such as a global or static local variable. + * Its contents will be reinitialized from scratch. + */ +int console_stm32_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, + console_t *console); + +#endif /*__ASSEMBLER__*/ + +#endif /* STM32_CONSOLE_H */ diff --git a/include/drivers/st/stm32_fmc2_nand.h b/include/drivers/st/stm32_fmc2_nand.h new file mode 100644 index 0000000..81d5b9d --- /dev/null +++ b/include/drivers/st/stm32_fmc2_nand.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_FMC2_NAND_H +#define STM32_FMC2_NAND_H + +int stm32_fmc2_init(void); + +#endif /* STM32_FMC2_NAND_H */ diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h new file mode 100644 index 0000000..eeef9da --- /dev/null +++ b/include/drivers/st/stm32_gpio.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_GPIO_H +#define STM32_GPIO_H + +#include <lib/utils_def.h> + +#define GPIO_MODE_OFFSET U(0x00) +#define GPIO_TYPE_OFFSET U(0x04) +#define GPIO_SPEED_OFFSET U(0x08) +#define GPIO_PUPD_OFFSET U(0x0C) +#define GPIO_OD_OFFSET U(0x14) +#define GPIO_BSRR_OFFSET U(0x18) +#define GPIO_AFRL_OFFSET U(0x20) +#define GPIO_AFRH_OFFSET U(0x24) +#define GPIO_SECR_OFFSET U(0x30) + +#define GPIO_ALT_LOWER_LIMIT U(0x08) + +#define GPIO_PIN_(_x) U(_x) +#define GPIO_PIN_MAX GPIO_PIN_(15) + +#define GPIO_ALTERNATE_(_x) U(_x) +#define GPIO_ALTERNATE_MASK U(0x0F) + +#define GPIO_MODE_INPUT U(0x00) +#define GPIO_MODE_OUTPUT U(0x01) +#define GPIO_MODE_ALTERNATE U(0x02) +#define GPIO_MODE_ANALOG U(0x03) +#define GPIO_MODE_MASK U(0x03) + +#define GPIO_TYPE_PUSH_PULL U(0x00) +#define GPIO_TYPE_OPEN_DRAIN U(0x01) +#define GPIO_TYPE_MASK U(0x01) + +#define GPIO_SPEED_LOW U(0x00) +#define GPIO_SPEED_MEDIUM U(0x01) +#define GPIO_SPEED_HIGH U(0x02) +#define GPIO_SPEED_VERY_HIGH U(0x03) +#define GPIO_SPEED_MASK U(0x03) + +#define GPIO_NO_PULL U(0x00) +#define GPIO_PULL_UP U(0x01) +#define GPIO_PULL_DOWN U(0x02) +#define GPIO_PULL_MASK U(0x03) + +#define GPIO_OD_OUTPUT_LOW U(0x00) +#define GPIO_OD_OUTPUT_HIGH U(0x01) +#define GPIO_OD_MASK U(0x01) + +#ifndef __ASSEMBLER__ +#include <stdint.h> + +int dt_set_pinctrl_config(int node); +void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure); +void set_gpio_reset_cfg(uint32_t bank, uint32_t pin); +#endif /*__ASSEMBLER__*/ + +#endif /* STM32_GPIO_H */ diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h new file mode 100644 index 0000000..bebb4af --- /dev/null +++ b/include/drivers/st/stm32_hash.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_HASH_H +#define STM32_HASH_H + +#include <stdint.h> + +enum stm32_hash_algo_mode { +#if STM32_HASH_VER == 2 + HASH_MD5SUM, +#endif + HASH_SHA1, + HASH_SHA224, + HASH_SHA256, +#if STM32_HASH_VER == 4 + HASH_SHA384, + HASH_SHA512, +#endif +}; + +int stm32_hash_update(const uint8_t *buffer, size_t length); +int stm32_hash_final(uint8_t *digest); +int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length, + uint8_t *digest); +void stm32_hash_init(enum stm32_hash_algo_mode mode); +int stm32_hash_register(void); + +#endif /* STM32_HASH_H */ diff --git a/include/drivers/st/stm32_i2c.h b/include/drivers/st/stm32_i2c.h new file mode 100644 index 0000000..170d4cf --- /dev/null +++ b/include/drivers/st/stm32_i2c.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_I2C_H +#define STM32_I2C_H + +#include <stdint.h> + +#include <lib/utils_def.h> + +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE BIT(0) +#define I2C_CR1_TXIE BIT(1) +#define I2C_CR1_RXIE BIT(2) +#define I2C_CR1_ADDRIE BIT(3) +#define I2C_CR1_NACKIE BIT(4) +#define I2C_CR1_STOPIE BIT(5) +#define I2C_CR1_TCIE BIT(6) +#define I2C_CR1_ERRIE BIT(7) +#define I2C_CR1_DNF GENMASK(11, 8) +#define I2C_CR1_ANFOFF BIT(12) +#define I2C_CR1_SWRST BIT(13) +#define I2C_CR1_TXDMAEN BIT(14) +#define I2C_CR1_RXDMAEN BIT(15) +#define I2C_CR1_SBC BIT(16) +#define I2C_CR1_NOSTRETCH BIT(17) +#define I2C_CR1_WUPEN BIT(18) +#define I2C_CR1_GCEN BIT(19) +#define I2C_CR1_SMBHEN BIT(22) +#define I2C_CR1_SMBDEN BIT(21) +#define I2C_CR1_ALERTEN BIT(22) +#define I2C_CR1_PECEN BIT(23) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_SADD GENMASK(9, 0) +#define I2C_CR2_RD_WRN BIT(10) +#define I2C_CR2_RD_WRN_OFFSET 10U +#define I2C_CR2_ADD10 BIT(11) +#define I2C_CR2_HEAD10R BIT(12) +#define I2C_CR2_START BIT(13) +#define I2C_CR2_STOP BIT(14) +#define I2C_CR2_NACK BIT(15) +#define I2C_CR2_NBYTES GENMASK(23, 16) +#define I2C_CR2_NBYTES_OFFSET 16U +#define I2C_CR2_RELOAD BIT(24) +#define I2C_CR2_AUTOEND BIT(25) +#define I2C_CR2_PECBYTE BIT(26) + +/* Bit definition for I2C_OAR1 register */ +#define I2C_OAR1_OA1 GENMASK(9, 0) +#define I2C_OAR1_OA1MODE BIT(10) +#define I2C_OAR1_OA1EN BIT(15) + +/* Bit definition for I2C_OAR2 register */ +#define I2C_OAR2_OA2 GENMASK(7, 1) +#define I2C_OAR2_OA2MSK GENMASK(10, 8) +#define I2C_OAR2_OA2NOMASK 0 +#define I2C_OAR2_OA2MASK01 BIT(8) +#define I2C_OAR2_OA2MASK02 BIT(9) +#define I2C_OAR2_OA2MASK03 GENMASK(9, 8) +#define I2C_OAR2_OA2MASK04 BIT(10) +#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) +#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) +#define I2C_OAR2_OA2MASK07 GENMASK(10, 8) +#define I2C_OAR2_OA2EN BIT(15) + +/* Bit definition for I2C_TIMINGR register */ +#define I2C_TIMINGR_SCLL GENMASK(7, 0) +#define I2C_TIMINGR_SCLH GENMASK(15, 8) +#define I2C_TIMINGR_SDADEL GENMASK(19, 16) +#define I2C_TIMINGR_SCLDEL GENMASK(23, 20) +#define I2C_TIMINGR_PRESC GENMASK(31, 28) + +/* Bit definition for I2C_TIMEOUTR register */ +#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0) +#define I2C_TIMEOUTR_TIDLE BIT(12) +#define I2C_TIMEOUTR_TIMOUTEN BIT(15) +#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16) +#define I2C_TIMEOUTR_TEXTEN BIT(31) + +/* Bit definition for I2C_ISR register */ +#define I2C_ISR_TXE BIT(0) +#define I2C_ISR_TXIS BIT(1) +#define I2C_ISR_RXNE BIT(2) +#define I2C_ISR_ADDR BIT(3) +#define I2C_ISR_NACKF BIT(4) +#define I2C_ISR_STOPF BIT(5) +#define I2C_ISR_TC BIT(6) +#define I2C_ISR_TCR BIT(7) +#define I2C_ISR_BERR BIT(8) +#define I2C_ISR_ARLO BIT(9) +#define I2C_ISR_OVR BIT(10) +#define I2C_ISR_PECERR BIT(11) +#define I2C_ISR_TIMEOUT BIT(12) +#define I2C_ISR_ALERT BIT(13) +#define I2C_ISR_BUSY BIT(15) +#define I2C_ISR_DIR BIT(16) +#define I2C_ISR_ADDCODE GENMASK(23, 17) + +/* Bit definition for I2C_ICR register */ +#define I2C_ICR_ADDRCF BIT(3) +#define I2C_ICR_NACKCF BIT(4) +#define I2C_ICR_STOPCF BIT(5) +#define I2C_ICR_BERRCF BIT(8) +#define I2C_ICR_ARLOCF BIT(9) +#define I2C_ICR_OVRCF BIT(10) +#define I2C_ICR_PECCF BIT(11) +#define I2C_ICR_TIMOUTCF BIT(12) +#define I2C_ICR_ALERTCF BIT(13) + +enum i2c_speed_e { + I2C_SPEED_STANDARD, /* 100 kHz */ + I2C_SPEED_FAST, /* 400 kHz */ + I2C_SPEED_FAST_PLUS, /* 1 MHz */ +}; + +#define STANDARD_RATE 100000 +#define FAST_RATE 400000 +#define FAST_PLUS_RATE 1000000 + +struct stm32_i2c_init_s { + uint32_t own_address1; /* + * Specifies the first device own + * address. This parameter can be a + * 7-bit or 10-bit address. + */ + + uint32_t addressing_mode; /* + * Specifies if 7-bit or 10-bit + * addressing mode is selected. + * This parameter can be a value of + * @ref I2C_ADDRESSING_MODE. + */ + + uint32_t dual_address_mode; /* + * Specifies if dual addressing mode is + * selected. + * This parameter can be a value of @ref + * I2C_DUAL_ADDRESSING_MODE. + */ + + uint32_t own_address2; /* + * Specifies the second device own + * address if dual addressing mode is + * selected. This parameter can be a + * 7-bit address. + */ + + uint32_t own_address2_masks; /* + * Specifies the acknowledge mask + * address second device own address + * if dual addressing mode is selected + * This parameter can be a value of @ref + * I2C_OWN_ADDRESS2_MASKS. + */ + + uint32_t general_call_mode; /* + * Specifies if general call mode is + * selected. + * This parameter can be a value of @ref + * I2C_GENERAL_CALL_ADDRESSING_MODE. + */ + + uint32_t no_stretch_mode; /* + * Specifies if nostretch mode is + * selected. + * This parameter can be a value of @ref + * I2C_NOSTRETCH_MODE. + */ + + uint32_t rise_time; /* + * Specifies the SCL clock pin rising + * time in nanoseconds. + */ + + uint32_t fall_time; /* + * Specifies the SCL clock pin falling + * time in nanoseconds. + */ + + enum i2c_speed_e speed_mode; /* + * Specifies the I2C clock source + * frequency mode. + * This parameter can be a value of @ref + * i2c_speed_mode_e. + */ + + int analog_filter; /* + * Specifies if the I2C analog noise + * filter is selected. + * This parameter can be 0 (filter + * off), all other values mean filter + * on. + */ + + uint8_t digital_filter_coef; /* + * Specifies the I2C digital noise + * filter coefficient. + * This parameter can be a value + * between 0 and + * STM32_I2C_DIGITAL_FILTER_MAX. + */ +}; + +enum i2c_state_e { + I2C_STATE_RESET = 0x00U, /* Not yet initialized */ + I2C_STATE_READY = 0x20U, /* Ready for use */ + I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */ + I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */ + I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */ +}; + +enum i2c_mode_e { + I2C_MODE_NONE = 0x00U, /* No active communication */ + I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */ + I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */ + I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */ + +}; + +#define I2C_ERROR_NONE 0x00000000U /* No error */ +#define I2C_ERROR_BERR 0x00000001U /* BERR error */ +#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */ +#define I2C_ERROR_AF 0x00000004U /* ACKF error */ +#define I2C_ERROR_OVR 0x00000008U /* OVR error */ +#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */ +#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */ +#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */ + +struct i2c_handle_s { + uint32_t i2c_base_addr; /* Registers base address */ + unsigned int dt_status; /* DT nsec/sec status */ + unsigned int clock; /* Clock reference */ + uint8_t lock; /* Locking object */ + enum i2c_state_e i2c_state; /* Communication state */ + enum i2c_mode_e i2c_mode; /* Communication mode */ + uint32_t i2c_err; /* Error code */ +}; + +#define I2C_ADDRESSINGMODE_7BIT 0x00000001U +#define I2C_ADDRESSINGMODE_10BIT 0x00000002U + +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN + +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN + +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH + +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000002U + +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE 0x00000000U + +#define I2C_NO_STARTSTOP 0x00000000U +#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ + I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) + +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR + +#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN) + +#define I2C_TIMEOUT_BUSY_MS 25U + +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF + +/* STM32 specific defines */ +#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ +#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ +#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD +#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ +#define STM32_I2C_DIGITAL_FILTER_MAX 16 + +int stm32_i2c_get_setup_from_fdt(void *fdt, int node, + struct stm32_i2c_init_s *init); +int stm32_i2c_init(struct i2c_handle_s *hi2c, + struct stm32_i2c_init_s *init_data); +int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint16_t mem_addr, uint16_t mem_add_size, + uint8_t *p_data, uint16_t size, uint32_t timeout_ms); +int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint16_t mem_addr, uint16_t mem_add_size, + uint8_t *p_data, uint16_t size, uint32_t timeout_ms); +int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint8_t *p_data, uint16_t size, + uint32_t timeout_ms); +int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint8_t *p_data, uint16_t size, + uint32_t timeout_ms); +bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr, + uint32_t trials, uint32_t timeout_ms); + +#endif /* STM32_I2C_H */ diff --git a/include/drivers/st/stm32_iwdg.h b/include/drivers/st/stm32_iwdg.h new file mode 100644 index 0000000..bad2524 --- /dev/null +++ b/include/drivers/st/stm32_iwdg.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_IWDG_H +#define STM32_IWDG_H + +#include <stdint.h> + +#define IWDG_HW_ENABLED BIT(0) +#define IWDG_DISABLE_ON_STOP BIT(1) +#define IWDG_DISABLE_ON_STANDBY BIT(2) + +int stm32_iwdg_init(void); +void stm32_iwdg_refresh(void); + +#endif /* STM32_IWDG_H */ diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h new file mode 100644 index 0000000..34b3f6b --- /dev/null +++ b/include/drivers/st/stm32_pka.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_PKA_H +#define STM32_PKA_H + +#include <stdint.h> + +enum stm32_pka_ecdsa_curve_id { + PKA_NIST_P256, + PKA_BRAINPOOL_P256R1, + PKA_BRAINPOOL_P256T1, + PKA_NIST_P521, +}; + +struct stm32_pka_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +int stm32_pka_init(void); +int stm32_pka_ecdsa_verif(void *hash, unsigned int hash_size, + void *sig_r_ptr, unsigned int sig_r_size, + void *sig_s_ptr, unsigned int sig_s_size, + void *pk_x_ptr, unsigned int pk_x_size, + void *pk_y_ptr, unsigned int pk_y_size, + enum stm32_pka_ecdsa_curve_id cid); + +#endif /* STM32_PKA_H */ diff --git a/include/drivers/st/stm32_qspi.h b/include/drivers/st/stm32_qspi.h new file mode 100644 index 0000000..f47fca4 --- /dev/null +++ b/include/drivers/st/stm32_qspi.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32_QSPI_H +#define STM32_QSPI_H + +int stm32_qspi_init(void); + +#endif /* STM32_QSPI_H */ diff --git a/include/drivers/st/stm32_rng.h b/include/drivers/st/stm32_rng.h new file mode 100644 index 0000000..6ac064d --- /dev/null +++ b/include/drivers/st/stm32_rng.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_RNG_H +#define STM32_RNG_H + +#include <stdint.h> + +int stm32_rng_read(uint8_t *out, uint32_t size); +int stm32_rng_init(void); + +#endif /* STM32_RNG_H */ diff --git a/include/drivers/st/stm32_saes.h b/include/drivers/st/stm32_saes.h new file mode 100644 index 0000000..0a50438 --- /dev/null +++ b/include/drivers/st/stm32_saes.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_SAES_H +#define STM32_SAES_H + +#include <stdbool.h> +#include <stddef.h> +#include <stdint.h> + +#define DT_SAES_COMPAT "st,stm32-saes" + +struct stm32_saes_platdata { + uintptr_t base; + unsigned long clock_id; + unsigned int reset_id; +}; + +enum stm32_saes_chaining_mode { + STM32_SAES_MODE_ECB, + STM32_SAES_MODE_CBC, + STM32_SAES_MODE_CTR, + STM32_SAES_MODE_GCM, + STM32_SAES_MODE_CCM, /* Not use in TF-A */ +}; + +enum stm32_saes_key_selection { + STM32_SAES_KEY_SOFT, + STM32_SAES_KEY_DHU, /* Derived HW unique key */ + STM32_SAES_KEY_BH, /* Boot HW key */ + STM32_SAES_KEY_BHU_XOR_BH, /* XOR of DHUK and BHK */ + STM32_SAES_KEY_WRAPPED +}; + +struct stm32_saes_context { + uintptr_t base; + uint32_t cr; + uint32_t assoc_len; + uint32_t load_len; + uint32_t key[8]; /* In HW byte order */ + uint32_t iv[4]; /* In HW byte order */ +}; + +int stm32_saes_driver_init(void); + +int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt, + enum stm32_saes_chaining_mode ch_mode, enum stm32_saes_key_selection key_select, + const void *key, size_t key_len, const void *iv, size_t iv_len); +int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data, size_t data_len); +int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block, + uint8_t *data_in, uint8_t *data_out, size_t data_len); +int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len); +#endif diff --git a/include/drivers/st/stm32_sdmmc2.h b/include/drivers/st/stm32_sdmmc2.h new file mode 100644 index 0000000..c83f625 --- /dev/null +++ b/include/drivers/st/stm32_sdmmc2.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_SDMMC2_H +#define STM32_SDMMC2_H + +#include <stdbool.h> + +#include <drivers/mmc.h> +#include <drivers/st/regulator.h> + +struct stm32_sdmmc2_params { + uintptr_t reg_base; + unsigned int clk_rate; + unsigned int bus_width; + unsigned int flags; + struct mmc_device_info *device_info; + unsigned int pin_ckin; + unsigned int negedge; + unsigned int dirpol; + unsigned int clock_id; + unsigned int reset_id; + unsigned int max_freq; + bool use_dma; + struct rdev *vmmc_regu; +}; + +unsigned long long stm32_sdmmc2_mmc_get_device_size(void); +int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params); +bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory); + +#endif /* STM32_SDMMC2_H */ diff --git a/include/drivers/st/stm32_uart.h b/include/drivers/st/stm32_uart.h new file mode 100644 index 0000000..866e158 --- /dev/null +++ b/include/drivers/st/stm32_uart.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_UART_H +#define STM32_UART_H + +/* UART word length */ +#define STM32_UART_WORDLENGTH_7B USART_CR1_M1 +#define STM32_UART_WORDLENGTH_8B 0x00000000U +#define STM32_UART_WORDLENGTH_9B USART_CR1_M0 + +/* UART number of stop bits */ +#define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0 +#define STM32_UART_STOPBITS_1 0x00000000U +#define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) +#define STM32_UART_STOPBITS_2 USART_CR2_STOP_1 + +/* UART parity */ +#define STM32_UART_PARITY_NONE 0x00000000U +#define STM32_UART_PARITY_EVEN USART_CR1_PCE +#define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) + +/* UART transfer mode */ +#define STM32_UART_MODE_RX USART_CR1_RE +#define STM32_UART_MODE_TX USART_CR1_TE +#define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) + +/* UART hardware flow control */ +#define STM32_UART_HWCONTROL_NONE 0x00000000U +#define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE +#define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE +#define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) + +/* UART prescaler */ +#define STM32_UART_PRESCALER_DIV1 0x00000000U +#define STM32_UART_PRESCALER_DIV2 0x00000001U +#define STM32_UART_PRESCALER_DIV4 0x00000002U +#define STM32_UART_PRESCALER_DIV6 0x00000003U +#define STM32_UART_PRESCALER_DIV8 0x00000004U +#define STM32_UART_PRESCALER_DIV10 0x00000005U +#define STM32_UART_PRESCALER_DIV12 0x00000006U +#define STM32_UART_PRESCALER_DIV16 0x00000007U +#define STM32_UART_PRESCALER_DIV32 0x00000008U +#define STM32_UART_PRESCALER_DIV64 0x00000009U +#define STM32_UART_PRESCALER_DIV128 0x0000000AU +#define STM32_UART_PRESCALER_DIV256 0x0000000BU +#define STM32_UART_PRESCALER_NB 0x0000000CU + +/* UART fifo mode */ +#define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN +#define STM32_UART_FIFOMODE_DIS 0x00000000U + +/* UART TXFIFO threshold level */ +#define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U +#define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0 +#define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1 +#define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1) +#define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2 +#define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) + +/* UART RXFIFO threshold level */ +#define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U +#define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0 +#define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1 +#define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1) +#define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2 +#define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) + +struct stm32_uart_init_s { + uint32_t baud_rate; /* + * Configures the UART communication + * baud rate. + */ + + uint32_t word_length; /* + * Specifies the number of data bits + * transmitted or received in a frame. + * This parameter can be a value of + * @ref STM32_UART_WORDLENGTH_*. + */ + + uint32_t stop_bits; /* + * Specifies the number of stop bits + * transmitted. This parameter can be + * a value of @ref STM32_UART_STOPBITS_*. + */ + + uint32_t parity; /* + * Specifies the parity mode. + * This parameter can be a value of + * @ref STM32_UART_PARITY_*. + */ + + uint32_t mode; /* + * Specifies whether the receive or + * transmit mode is enabled or + * disabled. This parameter can be a + * value of @ref @ref STM32_UART_MODE_*. + */ + + uint32_t hw_flow_control; /* + * Specifies whether the hardware flow + * control mode is enabled or + * disabled. This parameter can be a + * value of @ref STM32_UARTHWCONTROL_*. + */ + + uint32_t one_bit_sampling; /* + * Specifies whether a single sample + * or three samples' majority vote is + * selected. This parameter can be 0 + * or USART_CR3_ONEBIT. + */ + + uint32_t prescaler; /* + * Specifies the prescaler value used + * to divide the UART clock source. + * This parameter can be a value of + * @ref STM32_UART_PRESCALER_*. + */ + + uint32_t fifo_mode; /* + * Specifies if the FIFO mode will be + * used. This parameter can be a value + * of @ref STM32_UART_FIFOMODE_*. + */ + + uint32_t tx_fifo_threshold; /* + * Specifies the TXFIFO threshold + * level. This parameter can be a + * value of @ref + * STM32_UART_TXFIFO_THRESHOLD_*. + */ + + uint32_t rx_fifo_threshold; /* + * Specifies the RXFIFO threshold + * level. This parameter can be a + * value of @ref + * STM32_UART_RXFIFO_THRESHOLD_*. + */ +}; + +struct stm32_uart_handle_s { + uint32_t base; + uint32_t rdr_mask; +}; + +int stm32_uart_init(struct stm32_uart_handle_s *huart, + uintptr_t base_addr, + const struct stm32_uart_init_s *init); +void stm32_uart_stop(uintptr_t base_addr); +int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c); +int stm32_uart_flush(struct stm32_uart_handle_s *huart); +int stm32_uart_getc(struct stm32_uart_handle_s *huart); + +#endif /* STM32_UART_H */ diff --git a/include/drivers/st/stm32_uart_regs.h b/include/drivers/st/stm32_uart_regs.h new file mode 100644 index 0000000..14b296c --- /dev/null +++ b/include/drivers/st/stm32_uart_regs.h @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32_UART_REGS_H +#define STM32_UART_REGS_H + +#include <lib/utils_def.h> + +#define USART_CR1 U(0x00) +#define USART_CR2 U(0x04) +#define USART_CR3 U(0x08) +#define USART_BRR U(0x0C) +#define USART_GTPR U(0x10) +#define USART_RTOR U(0x14) +#define USART_RQR U(0x18) +#define USART_ISR U(0x1C) +#define USART_ICR U(0x20) +#define USART_RDR U(0x24) +#define USART_TDR U(0x28) +#define USART_PRESC U(0x2C) + +/* USART_CR1 register fields */ +#define USART_CR1_UE BIT(0) +#define USART_CR1_UESM BIT(1) +#define USART_CR1_RE BIT(2) +#define USART_CR1_TE BIT(3) +#define USART_CR1_IDLEIE BIT(4) +#define USART_CR1_RXNEIE BIT(5) +#define USART_CR1_TCIE BIT(6) +#define USART_CR1_TXEIE BIT(7) +#define USART_CR1_PEIE BIT(8) +#define USART_CR1_PS BIT(9) +#define USART_CR1_PCE BIT(10) +#define USART_CR1_WAKE BIT(11) +#define USART_CR1_M (BIT(28) | BIT(12)) +#define USART_CR1_M0 BIT(12) +#define USART_CR1_MME BIT(13) +#define USART_CR1_CMIE BIT(14) +#define USART_CR1_OVER8 BIT(15) +#define USART_CR1_DEDT GENMASK(20, 16) +#define USART_CR1_DEDT_0 BIT(16) +#define USART_CR1_DEDT_1 BIT(17) +#define USART_CR1_DEDT_2 BIT(18) +#define USART_CR1_DEDT_3 BIT(19) +#define USART_CR1_DEDT_4 BIT(20) +#define USART_CR1_DEAT GENMASK(25, 21) +#define USART_CR1_DEAT_0 BIT(21) +#define USART_CR1_DEAT_1 BIT(22) +#define USART_CR1_DEAT_2 BIT(23) +#define USART_CR1_DEAT_3 BIT(24) +#define USART_CR1_DEAT_4 BIT(25) +#define USART_CR1_RTOIE BIT(26) +#define USART_CR1_EOBIE BIT(27) +#define USART_CR1_M1 BIT(28) +#define USART_CR1_FIFOEN BIT(29) +#define USART_CR1_TXFEIE BIT(30) +#define USART_CR1_RXFFIE BIT(31) + +/* USART_CR2 register fields */ +#define USART_CR2_SLVEN BIT(0) +#define USART_CR2_DIS_NSS BIT(3) +#define USART_CR2_ADDM7 BIT(4) +#define USART_CR2_LBDL BIT(5) +#define USART_CR2_LBDIE BIT(6) +#define USART_CR2_LBCL BIT(8) +#define USART_CR2_CPHA BIT(9) +#define USART_CR2_CPOL BIT(10) +#define USART_CR2_CLKEN BIT(11) +#define USART_CR2_STOP GENMASK(13, 12) +#define USART_CR2_STOP_0 BIT(12) +#define USART_CR2_STOP_1 BIT(13) +#define USART_CR2_LINEN BIT(14) +#define USART_CR2_SWAP BIT(15) +#define USART_CR2_RXINV BIT(16) +#define USART_CR2_TXINV BIT(17) +#define USART_CR2_DATAINV BIT(18) +#define USART_CR2_MSBFIRST BIT(19) +#define USART_CR2_ABREN BIT(20) +#define USART_CR2_ABRMODE GENMASK(22, 21) +#define USART_CR2_ABRMODE_0 BIT(21) +#define USART_CR2_ABRMODE_1 BIT(22) +#define USART_CR2_RTOEN BIT(23) +#define USART_CR2_ADD GENMASK(31, 24) + +/* USART_CR3 register fields */ +#define USART_CR3_EIE BIT(0) +#define USART_CR3_IREN BIT(1) +#define USART_CR3_IRLP BIT(2) +#define USART_CR3_HDSEL BIT(3) +#define USART_CR3_NACK BIT(4) +#define USART_CR3_SCEN BIT(5) +#define USART_CR3_DMAR BIT(6) +#define USART_CR3_DMAT BIT(7) +#define USART_CR3_RTSE BIT(8) +#define USART_CR3_CTSE BIT(9) +#define USART_CR3_CTSIE BIT(10) +#define USART_CR3_ONEBIT BIT(11) +#define USART_CR3_OVRDIS BIT(12) +#define USART_CR3_DDRE BIT(13) +#define USART_CR3_DEM BIT(14) +#define USART_CR3_DEP BIT(15) +#define USART_CR3_SCARCNT GENMASK(19, 17) +#define USART_CR3_SCARCNT_0 BIT(17) +#define USART_CR3_SCARCNT_1 BIT(18) +#define USART_CR3_SCARCNT_2 BIT(19) +#define USART_CR3_WUS GENMASK(21, 20) +#define USART_CR3_WUS_0 BIT(20) +#define USART_CR3_WUS_1 BIT(21) +#define USART_CR3_WUFIE BIT(22) +#define USART_CR3_TXFTIE BIT(23) +#define USART_CR3_TCBGTIE BIT(24) +#define USART_CR3_RXFTCFG GENMASK(27, 25) +#define USART_CR3_RXFTCFG_0 BIT(25) +#define USART_CR3_RXFTCFG_1 BIT(26) +#define USART_CR3_RXFTCFG_2 BIT(27) +#define USART_CR3_RXFTIE BIT(28) +#define USART_CR3_TXFTCFG GENMASK(31, 29) +#define USART_CR3_TXFTCFG_0 BIT(29) +#define USART_CR3_TXFTCFG_1 BIT(30) +#define USART_CR3_TXFTCFG_2 BIT(31) + +/* USART_BRR register fields */ +#define USART_BRR_DIV_FRACTION GENMASK(3, 0) +#define USART_BRR_DIV_MANTISSA GENMASK(15, 4) + +/* USART_GTPR register fields */ +#define USART_GTPR_PSC GENMASK(7, 0) +#define USART_GTPR_GT GENMASK(15, 8) + +/* USART_RTOR register fields */ +#define USART_RTOR_RTO GENMASK(23, 0) +#define USART_RTOR_BLEN GENMASK(31, 24) + +/* USART_RQR register fields */ +#define USART_RQR_ABRRQ BIT(0) +#define USART_RQR_SBKRQ BIT(1) +#define USART_RQR_MMRQ BIT(2) +#define USART_RQR_RXFRQ BIT(3) +#define USART_RQR_TXFRQ BIT(4) + +/* USART_ISR register fields */ +#define USART_ISR_PE BIT(0) +#define USART_ISR_FE BIT(1) +#define USART_ISR_NE BIT(2) +#define USART_ISR_ORE BIT(3) +#define USART_ISR_IDLE BIT(4) +#define USART_ISR_RXNE BIT(5) +#define USART_ISR_TC BIT(6) +#define USART_ISR_TXE BIT(7) +#define USART_ISR_LBDF BIT(8) +#define USART_ISR_CTSIF BIT(9) +#define USART_ISR_CTS BIT(10) +#define USART_ISR_RTOF BIT(11) +#define USART_ISR_EOBF BIT(12) +#define USART_ISR_UDR BIT(13) +#define USART_ISR_ABRE BIT(14) +#define USART_ISR_ABRF BIT(15) +#define USART_ISR_BUSY BIT(16) +#define USART_ISR_CMF BIT(17) +#define USART_ISR_SBKF BIT(18) +#define USART_ISR_RWU BIT(19) +#define USART_ISR_WUF BIT(20) +#define USART_ISR_TEACK BIT(21) +#define USART_ISR_REACK BIT(22) +#define USART_ISR_TXFE BIT(23) +#define USART_ISR_RXFF BIT(24) +#define USART_ISR_TCBGT BIT(25) +#define USART_ISR_RXFT BIT(26) +#define USART_ISR_TXFT BIT(27) + +/* USART_ICR register fields */ +#define USART_ICR_PECF BIT(0) +#define USART_ICR_FECF BIT(1) +#define USART_ICR_NCF BIT(2) +#define USART_ICR_ORECF BIT(3) +#define USART_ICR_IDLECF BIT(4) +#define USART_ICR_TCCF BIT(6) +#define USART_ICR_TCBGT BIT(7) +#define USART_ICR_LBDCF BIT(8) +#define USART_ICR_CTSCF BIT(9) +#define USART_ICR_RTOCF BIT(11) +#define USART_ICR_EOBCF BIT(12) +#define USART_ICR_UDRCF BIT(13) +#define USART_ICR_CMCF BIT(17) +#define USART_ICR_WUCF BIT(20) + +/* USART_RDR register fields */ +#define USART_RDR_RDR GENMASK(8, 0) + +/* USART_TDR register fields */ +#define USART_TDR_TDR GENMASK(8, 0) + +/* USART_PRESC register fields */ +#define USART_PRESC_PRESCALER GENMASK(3, 0) + +#endif /* STM32_UART_REGS_H */ diff --git a/include/drivers/st/stm32mp13_rcc.h b/include/drivers/st/stm32mp13_rcc.h new file mode 100644 index 0000000..1451c9a --- /dev/null +++ b/include/drivers/st/stm32mp13_rcc.h @@ -0,0 +1,1878 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP13_RCC_H +#define STM32MP13_RCC_H + +#include <lib/utils_def.h> + +#define RCC_SECCFGR U(0X0) +#define RCC_MP_SREQSETR U(0X100) +#define RCC_MP_SREQCLRR U(0X104) +#define RCC_MP_APRSTCR U(0X108) +#define RCC_MP_APRSTSR U(0X10C) +#define RCC_PWRLPDLYCR U(0X110) +#define RCC_MP_GRSTCSETR U(0X114) +#define RCC_BR_RSTSCLRR U(0X118) +#define RCC_MP_RSTSSETR U(0X11C) +#define RCC_MP_RSTSCLRR U(0X120) +#define RCC_MP_IWDGFZSETR U(0X124) +#define RCC_MP_IWDGFZCLRR U(0X128) +#define RCC_MP_CIER U(0X200) +#define RCC_MP_CIFR U(0X204) +#define RCC_BDCR U(0X400) +#define RCC_RDLSICR U(0X404) +#define RCC_OCENSETR U(0X420) +#define RCC_OCENCLRR U(0X424) +#define RCC_OCRDYR U(0X428) +#define RCC_HSICFGR U(0X440) +#define RCC_CSICFGR U(0X444) +#define RCC_MCO1CFGR U(0X460) +#define RCC_MCO2CFGR U(0X464) +#define RCC_DBGCFGR U(0X468) +#define RCC_RCK12SELR U(0X480) +#define RCC_RCK3SELR U(0X484) +#define RCC_RCK4SELR U(0X488) +#define RCC_PLL1CR U(0X4A0) +#define RCC_PLL1CFGR1 U(0X4A4) +#define RCC_PLL1CFGR2 U(0X4A8) +#define RCC_PLL1FRACR U(0X4AC) +#define RCC_PLL1CSGR U(0X4B0) +#define RCC_PLL2CR U(0X4D0) +#define RCC_PLL2CFGR1 U(0X4D4) +#define RCC_PLL2CFGR2 U(0X4D8) +#define RCC_PLL2FRACR U(0X4DC) +#define RCC_PLL2CSGR U(0X4E0) +#define RCC_PLL3CR U(0X500) +#define RCC_PLL3CFGR1 U(0X504) +#define RCC_PLL3CFGR2 U(0X508) +#define RCC_PLL3FRACR U(0X50C) +#define RCC_PLL3CSGR U(0X510) +#define RCC_PLL4CR U(0X520) +#define RCC_PLL4CFGR1 U(0X524) +#define RCC_PLL4CFGR2 U(0X528) +#define RCC_PLL4FRACR U(0X52C) +#define RCC_PLL4CSGR U(0X530) +#define RCC_MPCKSELR U(0X540) +#define RCC_ASSCKSELR U(0X544) +#define RCC_MSSCKSELR U(0X548) +#define RCC_CPERCKSELR U(0X54C) +#define RCC_RTCDIVR U(0X560) +#define RCC_MPCKDIVR U(0X564) +#define RCC_AXIDIVR U(0X568) +#define RCC_MLAHBDIVR U(0X56C) +#define RCC_APB1DIVR U(0X570) +#define RCC_APB2DIVR U(0X574) +#define RCC_APB3DIVR U(0X578) +#define RCC_APB4DIVR U(0X57C) +#define RCC_APB5DIVR U(0X580) +#define RCC_APB6DIVR U(0X584) +#define RCC_TIMG1PRER U(0X5A0) +#define RCC_TIMG2PRER U(0X5A4) +#define RCC_TIMG3PRER U(0X5A8) +#define RCC_DDRITFCR U(0X5C0) +#define RCC_I2C12CKSELR U(0X600) +#define RCC_I2C345CKSELR U(0X604) +#define RCC_SPI2S1CKSELR U(0X608) +#define RCC_SPI2S23CKSELR U(0X60C) +#define RCC_SPI45CKSELR U(0X610) +#define RCC_UART12CKSELR U(0X614) +#define RCC_UART35CKSELR U(0X618) +#define RCC_UART4CKSELR U(0X61C) +#define RCC_UART6CKSELR U(0X620) +#define RCC_UART78CKSELR U(0X624) +#define RCC_LPTIM1CKSELR U(0X628) +#define RCC_LPTIM23CKSELR U(0X62C) +#define RCC_LPTIM45CKSELR U(0X630) +#define RCC_SAI1CKSELR U(0X634) +#define RCC_SAI2CKSELR U(0X638) +#define RCC_FDCANCKSELR U(0X63C) +#define RCC_SPDIFCKSELR U(0X640) +#define RCC_ADC12CKSELR U(0X644) +#define RCC_SDMMC12CKSELR U(0X648) +#define RCC_ETH12CKSELR U(0X64C) +#define RCC_USBCKSELR U(0X650) +#define RCC_QSPICKSELR U(0X654) +#define RCC_FMCCKSELR U(0X658) +#define RCC_RNG1CKSELR U(0X65C) +#define RCC_STGENCKSELR U(0X660) +#define RCC_DCMIPPCKSELR U(0X664) +#define RCC_SAESCKSELR U(0X668) +#define RCC_APB1RSTSETR U(0X6A0) +#define RCC_APB1RSTCLRR U(0X6A4) +#define RCC_APB2RSTSETR U(0X6A8) +#define RCC_APB2RSTCLRR U(0X6AC) +#define RCC_APB3RSTSETR U(0X6B0) +#define RCC_APB3RSTCLRR U(0X6B4) +#define RCC_APB4RSTSETR U(0X6B8) +#define RCC_APB4RSTCLRR U(0X6BC) +#define RCC_APB5RSTSETR U(0X6C0) +#define RCC_APB5RSTCLRR U(0X6C4) +#define RCC_APB6RSTSETR U(0X6C8) +#define RCC_APB6RSTCLRR U(0X6CC) +#define RCC_AHB2RSTSETR U(0X6D0) +#define RCC_AHB2RSTCLRR U(0X6D4) +#define RCC_AHB4RSTSETR U(0X6E0) +#define RCC_AHB4RSTCLRR U(0X6E4) +#define RCC_AHB5RSTSETR U(0X6E8) +#define RCC_AHB5RSTCLRR U(0X6EC) +#define RCC_AHB6RSTSETR U(0X6F0) +#define RCC_AHB6RSTCLRR U(0X6F4) +#define RCC_MP_APB1ENSETR U(0X700) +#define RCC_MP_APB1ENCLRR U(0X704) +#define RCC_MP_APB2ENSETR U(0X708) +#define RCC_MP_APB2ENCLRR U(0X70C) +#define RCC_MP_APB3ENSETR U(0X710) +#define RCC_MP_APB3ENCLRR U(0X714) +#define RCC_MP_S_APB3ENSETR U(0X718) +#define RCC_MP_S_APB3ENCLRR U(0X71C) +#define RCC_MP_NS_APB3ENSETR U(0X720) +#define RCC_MP_NS_APB3ENCLRR U(0X724) +#define RCC_MP_APB4ENSETR U(0X728) +#define RCC_MP_APB4ENCLRR U(0X72C) +#define RCC_MP_S_APB4ENSETR U(0X730) +#define RCC_MP_S_APB4ENCLRR U(0X734) +#define RCC_MP_NS_APB4ENSETR U(0X738) +#define RCC_MP_NS_APB4ENCLRR U(0X73C) +#define RCC_MP_APB5ENSETR U(0X740) +#define RCC_MP_APB5ENCLRR U(0X744) +#define RCC_MP_APB6ENSETR U(0X748) +#define RCC_MP_APB6ENCLRR U(0X74C) +#define RCC_MP_AHB2ENSETR U(0X750) +#define RCC_MP_AHB2ENCLRR U(0X754) +#define RCC_MP_AHB4ENSETR U(0X760) +#define RCC_MP_AHB4ENCLRR U(0X764) +#define RCC_MP_S_AHB4ENSETR U(0X768) +#define RCC_MP_S_AHB4ENCLRR U(0X76C) +#define RCC_MP_NS_AHB4ENSETR U(0X770) +#define RCC_MP_NS_AHB4ENCLRR U(0X774) +#define RCC_MP_AHB5ENSETR U(0X778) +#define RCC_MP_AHB5ENCLRR U(0X77C) +#define RCC_MP_AHB6ENSETR U(0X780) +#define RCC_MP_AHB6ENCLRR U(0X784) +#define RCC_MP_S_AHB6ENSETR U(0X788) +#define RCC_MP_S_AHB6ENCLRR U(0X78C) +#define RCC_MP_NS_AHB6ENSETR U(0X790) +#define RCC_MP_NS_AHB6ENCLRR U(0X794) +#define RCC_MP_APB1LPENSETR U(0X800) +#define RCC_MP_APB1LPENCLRR U(0X804) +#define RCC_MP_APB2LPENSETR U(0X808) +#define RCC_MP_APB2LPENCLRR U(0X80C) +#define RCC_MP_APB3LPENSETR U(0X810) +#define RCC_MP_APB3LPENCLRR U(0X814) +#define RCC_MP_S_APB3LPENSETR U(0X818) +#define RCC_MP_S_APB3LPENCLRR U(0X81C) +#define RCC_MP_NS_APB3LPENSETR U(0X820) +#define RCC_MP_NS_APB3LPENCLRR U(0X824) +#define RCC_MP_APB4LPENSETR U(0X828) +#define RCC_MP_APB4LPENCLRR U(0X82C) +#define RCC_MP_S_APB4LPENSETR U(0X830) +#define RCC_MP_S_APB4LPENCLRR U(0X834) +#define RCC_MP_NS_APB4LPENSETR U(0X838) +#define RCC_MP_NS_APB4LPENCLRR U(0X83C) +#define RCC_MP_APB5LPENSETR U(0X840) +#define RCC_MP_APB5LPENCLRR U(0X844) +#define RCC_MP_APB6LPENSETR U(0X848) +#define RCC_MP_APB6LPENCLRR U(0X84C) +#define RCC_MP_AHB2LPENSETR U(0X850) +#define RCC_MP_AHB2LPENCLRR U(0X854) +#define RCC_MP_AHB4LPENSETR U(0X858) +#define RCC_MP_AHB4LPENCLRR U(0X85C) +#define RCC_MP_S_AHB4LPENSETR U(0X868) +#define RCC_MP_S_AHB4LPENCLRR U(0X86C) +#define RCC_MP_NS_AHB4LPENSETR U(0X870) +#define RCC_MP_NS_AHB4LPENCLRR U(0X874) +#define RCC_MP_AHB5LPENSETR U(0X878) +#define RCC_MP_AHB5LPENCLRR U(0X87C) +#define RCC_MP_AHB6LPENSETR U(0X880) +#define RCC_MP_AHB6LPENCLRR U(0X884) +#define RCC_MP_S_AHB6LPENSETR U(0X888) +#define RCC_MP_S_AHB6LPENCLRR U(0X88C) +#define RCC_MP_NS_AHB6LPENSETR U(0X890) +#define RCC_MP_NS_AHB6LPENCLRR U(0X894) +#define RCC_MP_S_AXIMLPENSETR U(0X898) +#define RCC_MP_S_AXIMLPENCLRR U(0X89C) +#define RCC_MP_NS_AXIMLPENSETR U(0X8A0) +#define RCC_MP_NS_AXIMLPENCLRR U(0X8A4) +#define RCC_MP_MLAHBLPENSETR U(0X8A8) +#define RCC_MP_MLAHBLPENCLRR U(0X8AC) +#define RCC_APB3SECSR U(0X8C0) +#define RCC_APB4SECSR U(0X8C4) +#define RCC_APB5SECSR U(0X8C8) +#define RCC_APB6SECSR U(0X8CC) +#define RCC_AHB2SECSR U(0X8D0) +#define RCC_AHB4SECSR U(0X8D4) +#define RCC_AHB5SECSR U(0X8D8) +#define RCC_AHB6SECSR U(0X8DC) +#define RCC_VERR U(0XFF4) +#define RCC_IDR U(0XFF8) +#define RCC_SIDR U(0XFFC) + +/* RCC_SECCFGR register fields */ +#define RCC_SECCFGR_HSISEC BIT(0) +#define RCC_SECCFGR_CSISEC BIT(1) +#define RCC_SECCFGR_HSESEC BIT(2) +#define RCC_SECCFGR_LSISEC BIT(3) +#define RCC_SECCFGR_LSESEC BIT(4) +#define RCC_SECCFGR_PLL12SEC BIT(8) +#define RCC_SECCFGR_PLL3SEC BIT(9) +#define RCC_SECCFGR_PLL4SEC BIT(10) +#define RCC_SECCFGR_MPUSEC BIT(11) +#define RCC_SECCFGR_AXISEC BIT(12) +#define RCC_SECCFGR_MLAHBSEC BIT(13) +#define RCC_SECCFGR_APB3DIVSEC BIT(16) +#define RCC_SECCFGR_APB4DIVSEC BIT(17) +#define RCC_SECCFGR_APB5DIVSEC BIT(18) +#define RCC_SECCFGR_APB6DIVSEC BIT(19) +#define RCC_SECCFGR_TIMG3SEC BIT(20) +#define RCC_SECCFGR_CPERSEC BIT(21) +#define RCC_SECCFGR_MCO1SEC BIT(22) +#define RCC_SECCFGR_MCO2SEC BIT(23) +#define RCC_SECCFGR_STPSEC BIT(24) +#define RCC_SECCFGR_RSTSEC BIT(25) +#define RCC_SECCFGR_PWRSEC BIT(31) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_VCPURSTF BIT(5) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STP2RSTF BIT(10) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_VCPURSTF BIT(5) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STP2RSTF BIT(10) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_DIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 8 + +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +#define RCC_RDLSICR_LSIRDY_BIT 1 + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSIDIVRDY_BIT 2 +#define RCC_OCRDYR_CSIRDY_BIT 4 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_MLAHBSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MLAHBSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MLAHBSSRCRDY BIT(31) + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(3, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_MLAHBDIVR register fields */ +#define RCC_MLAHBDIVR_MLAHBDIV_MASK GENMASK(3, 0) +#define RCC_MLAHBDIVR_MLAHBDIV_SHIFT 0 +#define RCC_MLAHBDIVR_MLAHBDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_APB6DIVR register fields */ +#define RCC_APB6DIVR_APB6DIV_MASK GENMASK(2, 0) +#define RCC_APB6DIVR_APB6DIV_SHIFT 0 +#define RCC_APB6DIVR_APB6DIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMG3PRER register fields */ +#define RCC_TIMG3PRER_TIMG3PRE BIT(0) +#define RCC_TIMG3PRER_TIMG3PRERDY BIT(31) + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C345CKSELR register fields */ +#define RCC_I2C345CKSELR_I2C3SRC_MASK GENMASK(2, 0) +#define RCC_I2C345CKSELR_I2C3SRC_SHIFT 0 +#define RCC_I2C345CKSELR_I2C4SRC_MASK GENMASK(5, 3) +#define RCC_I2C345CKSELR_I2C4SRC_SHIFT 3 +#define RCC_I2C345CKSELR_I2C5SRC_MASK GENMASK(8, 6) +#define RCC_I2C345CKSELR_I2C5SRC_SHIFT 6 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI4SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI4SRC_SHIFT 0 +#define RCC_SPI45CKSELR_SPI5SRC_MASK GENMASK(5, 3) +#define RCC_SPI45CKSELR_SPI5SRC_SHIFT 3 + +/* RCC_UART12CKSELR register fields */ +#define RCC_UART12CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART12CKSELR_UART1SRC_SHIFT 0 +#define RCC_UART12CKSELR_UART2SRC_MASK GENMASK(5, 3) +#define RCC_UART12CKSELR_UART2SRC_SHIFT 3 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART4CKSELR register fields */ +#define RCC_UART4CKSELR_UART4SRC_MASK GENMASK(2, 0) +#define RCC_UART4CKSELR_UART4SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM2SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM2SRC_SHIFT 0 +#define RCC_LPTIM23CKSELR_LPTIM3SRC_MASK GENMASK(5, 3) +#define RCC_LPTIM23CKSELR_LPTIM3SRC_SHIFT 3 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_ADC12CKSELR register fields */ +#define RCC_ADC12CKSELR_ADC1SRC_MASK GENMASK(1, 0) +#define RCC_ADC12CKSELR_ADC1SRC_SHIFT 0 +#define RCC_ADC12CKSELR_ADC2SRC_MASK GENMASK(3, 2) +#define RCC_ADC12CKSELR_ADC2SRC_SHIFT 2 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC1SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC1SRC_SHIFT 0 +#define RCC_SDMMC12CKSELR_SDMMC2SRC_MASK GENMASK(5, 3) +#define RCC_SDMMC12CKSELR_SDMMC2SRC_SHIFT 3 + +/* RCC_ETH12CKSELR register fields */ +#define RCC_ETH12CKSELR_ETH1SRC_MASK GENMASK(1, 0) +#define RCC_ETH12CKSELR_ETH1SRC_SHIFT 0 +#define RCC_ETH12CKSELR_ETH1PTPDIV_MASK GENMASK(7, 4) +#define RCC_ETH12CKSELR_ETH1PTPDIV_SHIFT 4 +#define RCC_ETH12CKSELR_ETH2SRC_MASK GENMASK(9, 8) +#define RCC_ETH12CKSELR_ETH2SRC_SHIFT 8 +#define RCC_ETH12CKSELR_ETH2PTPDIV_MASK GENMASK(15, 12) +#define RCC_ETH12CKSELR_ETH2PTPDIV_SHIFT 12 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DCMIPPCKSELR register fields */ +#define RCC_DCMIPPCKSELR_DCMIPPSRC_MASK GENMASK(1, 0) +#define RCC_DCMIPPCKSELR_DCMIPPSRC_SHIFT 0 + +/* RCC_SAESCKSELR register fields */ +#define RCC_SAESCKSELR_SAESSRC_MASK GENMASK(1, 0) +#define RCC_SAESCKSELR_SAESSRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_DTSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_DTSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DCMIPPRST BIT(1) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DCMIPPRST BIT(1) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_APB6RSTSETR register fields */ +#define RCC_APB6RSTSETR_USART1RST BIT(0) +#define RCC_APB6RSTSETR_USART2RST BIT(1) +#define RCC_APB6RSTSETR_SPI4RST BIT(2) +#define RCC_APB6RSTSETR_SPI5RST BIT(3) +#define RCC_APB6RSTSETR_I2C3RST BIT(4) +#define RCC_APB6RSTSETR_I2C4RST BIT(5) +#define RCC_APB6RSTSETR_I2C5RST BIT(6) +#define RCC_APB6RSTSETR_TIM12RST BIT(7) +#define RCC_APB6RSTSETR_TIM13RST BIT(8) +#define RCC_APB6RSTSETR_TIM14RST BIT(9) +#define RCC_APB6RSTSETR_TIM15RST BIT(10) +#define RCC_APB6RSTSETR_TIM16RST BIT(11) +#define RCC_APB6RSTSETR_TIM17RST BIT(12) + +/* RCC_APB6RSTCLRR register fields */ +#define RCC_APB6RSTCLRR_USART1RST BIT(0) +#define RCC_APB6RSTCLRR_USART2RST BIT(1) +#define RCC_APB6RSTCLRR_SPI4RST BIT(2) +#define RCC_APB6RSTCLRR_SPI5RST BIT(3) +#define RCC_APB6RSTCLRR_I2C3RST BIT(4) +#define RCC_APB6RSTCLRR_I2C4RST BIT(5) +#define RCC_APB6RSTCLRR_I2C5RST BIT(6) +#define RCC_APB6RSTCLRR_TIM12RST BIT(7) +#define RCC_APB6RSTCLRR_TIM13RST BIT(8) +#define RCC_APB6RSTCLRR_TIM14RST BIT(9) +#define RCC_APB6RSTCLRR_TIM15RST BIT(10) +#define RCC_APB6RSTCLRR_TIM16RST BIT(11) +#define RCC_APB6RSTCLRR_TIM17RST BIT(12) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTSETR_DMA3RST BIT(3) +#define RCC_AHB2RSTSETR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTSETR_ADC1RST BIT(5) +#define RCC_AHB2RSTSETR_ADC2RST BIT(6) +#define RCC_AHB2RSTSETR_USBORST BIT(8) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUX1RST BIT(2) +#define RCC_AHB2RSTCLRR_DMA3RST BIT(3) +#define RCC_AHB2RSTCLRR_DMAMUX2RST BIT(4) +#define RCC_AHB2RSTCLRR_ADC1RST BIT(5) +#define RCC_AHB2RSTCLRR_ADC2RST BIT(6) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_TSCRST BIT(15) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_TSCRST BIT(15) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_PKARST BIT(2) +#define RCC_AHB5RSTSETR_SAESRST BIT(3) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_PKARST BIT(2) +#define RCC_AHB5RSTCLRR_SAESRST BIT(3) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_MDMARST BIT(0) +#define RCC_AHB6RSTSETR_MCERST BIT(1) +#define RCC_AHB6RSTSETR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) +#define RCC_AHB6RSTSETR_ETH2MACRST BIT(30) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_MDMARST BIT(0) +#define RCC_AHB6RSTCLRR_MCERST BIT(1) +#define RCC_AHB6RSTCLRR_ETH1MACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) +#define RCC_AHB6RSTCLRR_ETH2MACRST BIT(30) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_DTSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_DTSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_S_APB3ENSETR register fields */ +#define RCC_MP_S_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_S_APB3ENCLRR register fields */ +#define RCC_MP_S_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENSETR register fields */ +#define RCC_MP_NS_APB3ENSETR_SYSCFGEN BIT(0) + +/* RCC_MP_NS_APB3ENCLRR register fields */ +#define RCC_MP_NS_APB3ENCLRR_SYSCFGEN BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_DCMIPPEN BIT(1) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_S_APB4ENSETR register fields */ +#define RCC_MP_S_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_S_APB4ENCLRR register fields */ +#define RCC_MP_S_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENSETR register fields */ +#define RCC_MP_NS_APB4ENSETR_LTDCEN BIT(0) + +/* RCC_MP_NS_APB4ENCLRR register fields */ +#define RCC_MP_NS_APB4ENCLRR_LTDCEN BIT(0) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZCEN BIT(11) +#define RCC_MP_APB5ENSETR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENCEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZCEN BIT(11) +#define RCC_MP_APB5ENCLRR_ETZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENCEN BIT(20) + +/* RCC_MP_APB6ENSETR register fields */ +#define RCC_MP_APB6ENSETR_USART1EN BIT(0) +#define RCC_MP_APB6ENSETR_USART2EN BIT(1) +#define RCC_MP_APB6ENSETR_SPI4EN BIT(2) +#define RCC_MP_APB6ENSETR_SPI5EN BIT(3) +#define RCC_MP_APB6ENSETR_I2C3EN BIT(4) +#define RCC_MP_APB6ENSETR_I2C4EN BIT(5) +#define RCC_MP_APB6ENSETR_I2C5EN BIT(6) +#define RCC_MP_APB6ENSETR_TIM12EN BIT(7) +#define RCC_MP_APB6ENSETR_TIM13EN BIT(8) +#define RCC_MP_APB6ENSETR_TIM14EN BIT(9) +#define RCC_MP_APB6ENSETR_TIM15EN BIT(10) +#define RCC_MP_APB6ENSETR_TIM16EN BIT(11) +#define RCC_MP_APB6ENSETR_TIM17EN BIT(12) + +/* RCC_MP_APB6ENCLRR register fields */ +#define RCC_MP_APB6ENCLRR_USART1EN BIT(0) +#define RCC_MP_APB6ENCLRR_USART2EN BIT(1) +#define RCC_MP_APB6ENCLRR_SPI4EN BIT(2) +#define RCC_MP_APB6ENCLRR_SPI5EN BIT(3) +#define RCC_MP_APB6ENCLRR_I2C3EN BIT(4) +#define RCC_MP_APB6ENCLRR_I2C4EN BIT(5) +#define RCC_MP_APB6ENCLRR_I2C5EN BIT(6) +#define RCC_MP_APB6ENCLRR_TIM12EN BIT(7) +#define RCC_MP_APB6ENCLRR_TIM13EN BIT(8) +#define RCC_MP_APB6ENCLRR_TIM14EN BIT(9) +#define RCC_MP_APB6ENCLRR_TIM15EN BIT(10) +#define RCC_MP_APB6ENCLRR_TIM16EN BIT(11) +#define RCC_MP_APB6ENCLRR_TIM17EN BIT(12) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENSETR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENSETR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENSETR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENSETR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUX1EN BIT(2) +#define RCC_MP_AHB2ENCLRR_DMA3EN BIT(3) +#define RCC_MP_AHB2ENCLRR_DMAMUX2EN BIT(4) +#define RCC_MP_AHB2ENCLRR_ADC1EN BIT(5) +#define RCC_MP_AHB2ENCLRR_ADC2EN BIT(6) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_TSCEN BIT(15) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_TSCEN BIT(15) + +/* RCC_MP_S_AHB4ENSETR register fields */ +#define RCC_MP_S_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_S_AHB4ENCLRR register fields */ +#define RCC_MP_S_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_S_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_S_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_S_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_S_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_S_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_S_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_S_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_S_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENSETR register fields */ +#define RCC_MP_NS_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENSETR_GPIOIEN BIT(8) + +/* RCC_MP_NS_AHB4ENCLRR register fields */ +#define RCC_MP_NS_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_NS_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_NS_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_NS_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_NS_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_NS_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_NS_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_NS_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_NS_AHB4ENCLRR_GPIOIEN BIT(8) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_PKAEN BIT(2) +#define RCC_MP_AHB5ENSETR_SAESEN BIT(3) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_PKAEN BIT(2) +#define RCC_MP_AHB5ENCLRR_SAESEN BIT(3) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MCEEN BIT(1) +#define RCC_MP_AHB6ENSETR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) +#define RCC_MP_AHB6ENSETR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENSETR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENSETR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENSETR_ETH2MACEN BIT(30) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MCEEN BIT(1) +#define RCC_MP_AHB6ENCLRR_ETH1CKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETH1TXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETH1RXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETH1MACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) +#define RCC_MP_AHB6ENCLRR_ETH2CKEN BIT(27) +#define RCC_MP_AHB6ENCLRR_ETH2TXEN BIT(28) +#define RCC_MP_AHB6ENCLRR_ETH2RXEN BIT(29) +#define RCC_MP_AHB6ENCLRR_ETH2MACEN BIT(30) + +/* RCC_MP_S_AHB6ENSETR register fields */ +#define RCC_MP_S_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_S_AHB6ENCLRR register fields */ +#define RCC_MP_S_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENSETR register fields */ +#define RCC_MP_NS_AHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_NS_AHB6ENCLRR register fields */ +#define RCC_MP_NS_AHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_DTSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_S_APB3LPENSETR register fields */ +#define RCC_MP_S_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_S_APB3LPENCLRR register fields */ +#define RCC_MP_S_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENSETR register fields */ +#define RCC_MP_NS_APB3LPENSETR_SYSCFGLPEN BIT(0) + +/* RCC_MP_NS_APB3LPENCLRR register fields */ +#define RCC_MP_NS_APB3LPENCLRR_SYSCFGLPEN BIT(0) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_DCMIPPLPEN BIT(1) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_S_APB4LPENSETR register fields */ +#define RCC_MP_S_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_S_APB4LPENCLRR register fields */ +#define RCC_MP_S_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENSETR register fields */ +#define RCC_MP_NS_APB4LPENSETR_LTDCLPEN BIT(0) + +/* RCC_MP_NS_APB4LPENCLRR register fields */ +#define RCC_MP_NS_APB4LPENCLRR_LTDCLPEN BIT(0) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENSETR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZCLPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_ETZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENCLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENCSTPEN BIT(21) + +/* RCC_MP_APB6LPENSETR register fields */ +#define RCC_MP_APB6LPENSETR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENSETR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENSETR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENSETR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENSETR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENSETR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENSETR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENSETR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENSETR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENSETR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENSETR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENSETR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENSETR_TIM17LPEN BIT(12) + +/* RCC_MP_APB6LPENCLRR register fields */ +#define RCC_MP_APB6LPENCLRR_USART1LPEN BIT(0) +#define RCC_MP_APB6LPENCLRR_USART2LPEN BIT(1) +#define RCC_MP_APB6LPENCLRR_SPI4LPEN BIT(2) +#define RCC_MP_APB6LPENCLRR_SPI5LPEN BIT(3) +#define RCC_MP_APB6LPENCLRR_I2C3LPEN BIT(4) +#define RCC_MP_APB6LPENCLRR_I2C4LPEN BIT(5) +#define RCC_MP_APB6LPENCLRR_I2C5LPEN BIT(6) +#define RCC_MP_APB6LPENCLRR_TIM12LPEN BIT(7) +#define RCC_MP_APB6LPENCLRR_TIM13LPEN BIT(8) +#define RCC_MP_APB6LPENCLRR_TIM14LPEN BIT(9) +#define RCC_MP_APB6LPENCLRR_TIM15LPEN BIT(10) +#define RCC_MP_APB6LPENCLRR_TIM16LPEN BIT(11) +#define RCC_MP_APB6LPENCLRR_TIM17LPEN BIT(12) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENSETR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENSETR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUX1LPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_DMA3LPEN BIT(3) +#define RCC_MP_AHB2LPENCLRR_DMAMUX2LPEN BIT(4) +#define RCC_MP_AHB2LPENCLRR_ADC1LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_ADC2LPEN BIT(6) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_TSCLPEN BIT(15) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_TSCLPEN BIT(15) + +/* RCC_MP_S_AHB4LPENSETR register fields */ +#define RCC_MP_S_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_S_AHB4LPENCLRR register fields */ +#define RCC_MP_S_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_S_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_S_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_S_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_S_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_S_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_S_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_S_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_S_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENSETR register fields */ +#define RCC_MP_NS_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENSETR_GPIOILPEN BIT(8) + +/* RCC_MP_NS_AHB4LPENCLRR register fields */ +#define RCC_MP_NS_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_NS_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_NS_AHB4LPENCLRR_GPIOILPEN BIT(8) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENSETR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_PKALPEN BIT(2) +#define RCC_MP_AHB5LPENCLRR_SAESLPEN BIT(3) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENSETR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENSETR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENSETR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENSETR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENSETR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENSETR_ETH2STPEN BIT(31) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MCELPEN BIT(1) +#define RCC_MP_AHB6LPENCLRR_ETH1CKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETH1TXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETH1RXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETH1MACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETH1STPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) +#define RCC_MP_AHB6LPENCLRR_ETH2CKLPEN BIT(27) +#define RCC_MP_AHB6LPENCLRR_ETH2TXLPEN BIT(28) +#define RCC_MP_AHB6LPENCLRR_ETH2RXLPEN BIT(29) +#define RCC_MP_AHB6LPENCLRR_ETH2MACLPEN BIT(30) +#define RCC_MP_AHB6LPENCLRR_ETH2STPEN BIT(31) + +/* RCC_MP_S_AHB6LPENSETR register fields */ +#define RCC_MP_S_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_S_AHB6LPENCLRR register fields */ +#define RCC_MP_S_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENSETR register fields */ +#define RCC_MP_NS_AHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_NS_AHB6LPENCLRR register fields */ +#define RCC_MP_NS_AHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MP_S_AXIMLPENSETR register fields */ +#define RCC_MP_S_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_S_AXIMLPENCLRR register fields */ +#define RCC_MP_S_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENSETR register fields */ +#define RCC_MP_NS_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_NS_AXIMLPENCLRR register fields */ +#define RCC_MP_NS_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM3LPEN BIT(2) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM3LPEN BIT(2) + +/* RCC_APB3SECSR register fields */ +#define RCC_APB3SECSR_LPTIM2SECF BIT(0) +#define RCC_APB3SECSR_LPTIM3SECF BIT(1) +#define RCC_APB3SECSR_VREFSECF BIT(13) + +/* RCC_APB4SECSR register fields */ +#define RCC_APB4SECSR_DCMIPPSECF BIT(1) +#define RCC_APB4SECSR_USBPHYSECF BIT(16) + +/* RCC_APB5SECSR register fields */ +#define RCC_APB5SECSR_RTCSECF BIT(8) +#define RCC_APB5SECSR_TZCSECF BIT(11) +#define RCC_APB5SECSR_ETZPCSECF BIT(13) +#define RCC_APB5SECSR_IWDG1SECF BIT(15) +#define RCC_APB5SECSR_BSECSECF BIT(16) +#define RCC_APB5SECSR_STGENCSECF_MASK GENMASK(21, 20) +#define RCC_APB5SECSR_STGENCSECF_SHIFT 20 + +/* RCC_APB6SECSR register fields */ +#define RCC_APB6SECSR_USART1SECF BIT(0) +#define RCC_APB6SECSR_USART2SECF BIT(1) +#define RCC_APB6SECSR_SPI4SECF BIT(2) +#define RCC_APB6SECSR_SPI5SECF BIT(3) +#define RCC_APB6SECSR_I2C3SECF BIT(4) +#define RCC_APB6SECSR_I2C4SECF BIT(5) +#define RCC_APB6SECSR_I2C5SECF BIT(6) +#define RCC_APB6SECSR_TIM12SECF BIT(7) +#define RCC_APB6SECSR_TIM13SECF BIT(8) +#define RCC_APB6SECSR_TIM14SECF BIT(9) +#define RCC_APB6SECSR_TIM15SECF BIT(10) +#define RCC_APB6SECSR_TIM16SECF BIT(11) +#define RCC_APB6SECSR_TIM17SECF BIT(12) + +/* RCC_AHB2SECSR register fields */ +#define RCC_AHB2SECSR_DMA3SECF BIT(3) +#define RCC_AHB2SECSR_DMAMUX2SECF BIT(4) +#define RCC_AHB2SECSR_ADC1SECF BIT(5) +#define RCC_AHB2SECSR_ADC2SECF BIT(6) +#define RCC_AHB2SECSR_USBOSECF BIT(8) + +/* RCC_AHB4SECSR register fields */ +#define RCC_AHB4SECSR_TSCSECF BIT(15) + +/* RCC_AHB5SECSR register fields */ +#define RCC_AHB5SECSR_PKASECF BIT(2) +#define RCC_AHB5SECSR_SAESSECF BIT(3) +#define RCC_AHB5SECSR_CRYP1SECF BIT(4) +#define RCC_AHB5SECSR_HASH1SECF BIT(5) +#define RCC_AHB5SECSR_RNG1SECF BIT(6) +#define RCC_AHB5SECSR_BKPSRAMSECF BIT(8) + +/* RCC_AHB6SECSR register fields */ +#define RCC_AHB6SECSR_MCESECF BIT(1) +#define RCC_AHB6SECSR_ETH1SECF_MASK GENMASK(11, 7) +#define RCC_AHB6SECSR_ETH1SECF_SHIFT 7 +#define RCC_AHB6SECSR_FMCSECF BIT(12) +#define RCC_AHB6SECSR_QSPISECF BIT(14) +#define RCC_AHB6SECSR_SDMMC1SECF BIT(16) +#define RCC_AHB6SECSR_SDMMC2SECF BIT(17) +#define RCC_AHB6SECSR_ETH2SECF_MASK GENMASK(31, 27) +#define RCC_AHB6SECSR_ETH2SECF_SHIFT 27 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* RCC_IDR register fields */ +#define RCC_IDR_ID_MASK GENMASK(31, 0) +#define RCC_IDR_ID_SHIFT 0 + +/* RCC_SIDR register fields */ +#define RCC_SIDR_SID_MASK GENMASK(31, 0) +#define RCC_SIDR_SID_SHIFT 0 + +/* Used for all RCC_PLL<n>CR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLL<n>CFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) + +/* Used for all RCC_PLL<n>CFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) + +/* Used for all RCC_PLL<n>FRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLL<n>CSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for most of RCC_<x>SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Values of RCC_MPCKSELR register */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 + +/* Values of RCC_ASSCKSELR register */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 + +/* Values of RCC_MSSCKSELR register */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 + +/* Values of RCC_CPERCKSELR register */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MLAHBDIV_MASK GENMASK(3, 0) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +#define RCC_OCENR_DIGBYP_BIT 7 +#define RCC_OCENR_HSEBYP_BIT 10 +#define RCC_OCENR_HSECSSON_BIT 11 + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#define RCC_UART4CKSELR_HSI 0x00000002 + +#define RCC_CPERCKSELR_PERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_PERSRC_SHIFT 0 + +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) + +#define RCC_DDRITFCR_DDRC2EN BIT(0) +#define RCC_DDRITFCR_DDRC2LPEN BIT(1) + +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_OFFSET_MASK GENMASK(11, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp15_rcc.h b/include/drivers/st/stm32mp15_rcc.h new file mode 100644 index 0000000..ddc0397 --- /dev/null +++ b/include/drivers/st/stm32mp15_rcc.h @@ -0,0 +1,2328 @@ +/* + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_RCC_H +#define STM32MP1_RCC_H + +#include <lib/utils_def.h> + +#define RCC_TZCR U(0x00) +#define RCC_OCENSETR U(0x0C) +#define RCC_OCENCLRR U(0x10) +#define RCC_HSICFGR U(0x18) +#define RCC_CSICFGR U(0x1C) +#define RCC_MPCKSELR U(0x20) +#define RCC_ASSCKSELR U(0x24) +#define RCC_RCK12SELR U(0x28) +#define RCC_MPCKDIVR U(0x2C) +#define RCC_AXIDIVR U(0x30) +#define RCC_APB4DIVR U(0x3C) +#define RCC_APB5DIVR U(0x40) +#define RCC_RTCDIVR U(0x44) +#define RCC_MSSCKSELR U(0x48) +#define RCC_PLL1CR U(0x80) +#define RCC_PLL1CFGR1 U(0x84) +#define RCC_PLL1CFGR2 U(0x88) +#define RCC_PLL1FRACR U(0x8C) +#define RCC_PLL1CSGR U(0x90) +#define RCC_PLL2CR U(0x94) +#define RCC_PLL2CFGR1 U(0x98) +#define RCC_PLL2CFGR2 U(0x9C) +#define RCC_PLL2FRACR U(0xA0) +#define RCC_PLL2CSGR U(0xA4) +#define RCC_I2C46CKSELR U(0xC0) +#define RCC_SPI6CKSELR U(0xC4) +#define RCC_UART1CKSELR U(0xC8) +#define RCC_RNG1CKSELR U(0xCC) +#define RCC_CPERCKSELR U(0xD0) +#define RCC_STGENCKSELR U(0xD4) +#define RCC_DDRITFCR U(0xD8) +#define RCC_MP_BOOTCR U(0x100) +#define RCC_MP_SREQSETR U(0x104) +#define RCC_MP_SREQCLRR U(0x108) +#define RCC_MP_GCR U(0x10C) +#define RCC_MP_APRSTCR U(0x110) +#define RCC_MP_APRSTSR U(0x114) +#define RCC_BDCR U(0x140) +#define RCC_RDLSICR U(0x144) +#define RCC_APB4RSTSETR U(0x180) +#define RCC_APB4RSTCLRR U(0x184) +#define RCC_APB5RSTSETR U(0x188) +#define RCC_APB5RSTCLRR U(0x18C) +#define RCC_AHB5RSTSETR U(0x190) +#define RCC_AHB5RSTCLRR U(0x194) +#define RCC_AHB6RSTSETR U(0x198) +#define RCC_AHB6RSTCLRR U(0x19C) +#define RCC_TZAHB6RSTSETR U(0x1A0) +#define RCC_TZAHB6RSTCLRR U(0x1A4) +#define RCC_MP_APB4ENSETR U(0x200) +#define RCC_MP_APB4ENCLRR U(0x204) +#define RCC_MP_APB5ENSETR U(0x208) +#define RCC_MP_APB5ENCLRR U(0x20C) +#define RCC_MP_AHB5ENSETR U(0x210) +#define RCC_MP_AHB5ENCLRR U(0x214) +#define RCC_MP_AHB6ENSETR U(0x218) +#define RCC_MP_AHB6ENCLRR U(0x21C) +#define RCC_MP_TZAHB6ENSETR U(0x220) +#define RCC_MP_TZAHB6ENCLRR U(0x224) +#define RCC_MC_APB4ENSETR U(0x280) +#define RCC_MC_APB4ENCLRR U(0x284) +#define RCC_MC_APB5ENSETR U(0x288) +#define RCC_MC_APB5ENCLRR U(0x28C) +#define RCC_MC_AHB5ENSETR U(0x290) +#define RCC_MC_AHB5ENCLRR U(0x294) +#define RCC_MC_AHB6ENSETR U(0x298) +#define RCC_MC_AHB6ENCLRR U(0x29C) +#define RCC_MP_APB4LPENSETR U(0x300) +#define RCC_MP_APB4LPENCLRR U(0x304) +#define RCC_MP_APB5LPENSETR U(0x308) +#define RCC_MP_APB5LPENCLRR U(0x30C) +#define RCC_MP_AHB5LPENSETR U(0x310) +#define RCC_MP_AHB5LPENCLRR U(0x314) +#define RCC_MP_AHB6LPENSETR U(0x318) +#define RCC_MP_AHB6LPENCLRR U(0x31C) +#define RCC_MP_TZAHB6LPENSETR U(0x320) +#define RCC_MP_TZAHB6LPENCLRR U(0x324) +#define RCC_MC_APB4LPENSETR U(0x380) +#define RCC_MC_APB4LPENCLRR U(0x384) +#define RCC_MC_APB5LPENSETR U(0x388) +#define RCC_MC_APB5LPENCLRR U(0x38C) +#define RCC_MC_AHB5LPENSETR U(0x390) +#define RCC_MC_AHB5LPENCLRR U(0x394) +#define RCC_MC_AHB6LPENSETR U(0x398) +#define RCC_MC_AHB6LPENCLRR U(0x39C) +#define RCC_BR_RSTSCLRR U(0x400) +#define RCC_MP_GRSTCSETR U(0x404) +#define RCC_MP_RSTSCLRR U(0x408) +#define RCC_MP_IWDGFZSETR U(0x40C) +#define RCC_MP_IWDGFZCLRR U(0x410) +#define RCC_MP_CIER U(0x414) +#define RCC_MP_CIFR U(0x418) +#define RCC_PWRLPDLYCR U(0x41C) +#define RCC_MP_RSTSSETR U(0x420) +#define RCC_MCO1CFGR U(0x800) +#define RCC_MCO2CFGR U(0x804) +#define RCC_OCRDYR U(0x808) +#define RCC_DBGCFGR U(0x80C) +#define RCC_RCK3SELR U(0x820) +#define RCC_RCK4SELR U(0x824) +#define RCC_TIMG1PRER U(0x828) +#define RCC_TIMG2PRER U(0x82C) +#define RCC_MCUDIVR U(0x830) +#define RCC_APB1DIVR U(0x834) +#define RCC_APB2DIVR U(0x838) +#define RCC_APB3DIVR U(0x83C) +#define RCC_PLL3CR U(0x880) +#define RCC_PLL3CFGR1 U(0x884) +#define RCC_PLL3CFGR2 U(0x888) +#define RCC_PLL3FRACR U(0x88C) +#define RCC_PLL3CSGR U(0x890) +#define RCC_PLL4CR U(0x894) +#define RCC_PLL4CFGR1 U(0x898) +#define RCC_PLL4CFGR2 U(0x89C) +#define RCC_PLL4FRACR U(0x8A0) +#define RCC_PLL4CSGR U(0x8A4) +#define RCC_I2C12CKSELR U(0x8C0) +#define RCC_I2C35CKSELR U(0x8C4) +#define RCC_SAI1CKSELR U(0x8C8) +#define RCC_SAI2CKSELR U(0x8CC) +#define RCC_SAI3CKSELR U(0x8D0) +#define RCC_SAI4CKSELR U(0x8D4) +#define RCC_SPI2S1CKSELR U(0x8D8) +#define RCC_SPI2S23CKSELR U(0x8DC) +#define RCC_SPI45CKSELR U(0x8E0) +#define RCC_UART6CKSELR U(0x8E4) +#define RCC_UART24CKSELR U(0x8E8) +#define RCC_UART35CKSELR U(0x8EC) +#define RCC_UART78CKSELR U(0x8F0) +#define RCC_SDMMC12CKSELR U(0x8F4) +#define RCC_SDMMC3CKSELR U(0x8F8) +#define RCC_ETHCKSELR U(0x8FC) +#define RCC_QSPICKSELR U(0x900) +#define RCC_FMCCKSELR U(0x904) +#define RCC_FDCANCKSELR U(0x90C) +#define RCC_SPDIFCKSELR U(0x914) +#define RCC_CECCKSELR U(0x918) +#define RCC_USBCKSELR U(0x91C) +#define RCC_RNG2CKSELR U(0x920) +#define RCC_DSICKSELR U(0x924) +#define RCC_ADCCKSELR U(0x928) +#define RCC_LPTIM45CKSELR U(0x92C) +#define RCC_LPTIM23CKSELR U(0x930) +#define RCC_LPTIM1CKSELR U(0x934) +#define RCC_APB1RSTSETR U(0x980) +#define RCC_APB1RSTCLRR U(0x984) +#define RCC_APB2RSTSETR U(0x988) +#define RCC_APB2RSTCLRR U(0x98C) +#define RCC_APB3RSTSETR U(0x990) +#define RCC_APB3RSTCLRR U(0x994) +#define RCC_AHB2RSTSETR U(0x998) +#define RCC_AHB2RSTCLRR U(0x99C) +#define RCC_AHB3RSTSETR U(0x9A0) +#define RCC_AHB3RSTCLRR U(0x9A4) +#define RCC_AHB4RSTSETR U(0x9A8) +#define RCC_AHB4RSTCLRR U(0x9AC) +#define RCC_MP_APB1ENSETR U(0xA00) +#define RCC_MP_APB1ENCLRR U(0xA04) +#define RCC_MP_APB2ENSETR U(0xA08) +#define RCC_MP_APB2ENCLRR U(0xA0C) +#define RCC_MP_APB3ENSETR U(0xA10) +#define RCC_MP_APB3ENCLRR U(0xA14) +#define RCC_MP_AHB2ENSETR U(0xA18) +#define RCC_MP_AHB2ENCLRR U(0xA1C) +#define RCC_MP_AHB3ENSETR U(0xA20) +#define RCC_MP_AHB3ENCLRR U(0xA24) +#define RCC_MP_AHB4ENSETR U(0xA28) +#define RCC_MP_AHB4ENCLRR U(0xA2C) +#define RCC_MP_MLAHBENSETR U(0xA38) +#define RCC_MP_MLAHBENCLRR U(0xA3C) +#define RCC_MC_APB1ENSETR U(0xA80) +#define RCC_MC_APB1ENCLRR U(0xA84) +#define RCC_MC_APB2ENSETR U(0xA88) +#define RCC_MC_APB2ENCLRR U(0xA8C) +#define RCC_MC_APB3ENSETR U(0xA90) +#define RCC_MC_APB3ENCLRR U(0xA94) +#define RCC_MC_AHB2ENSETR U(0xA98) +#define RCC_MC_AHB2ENCLRR U(0xA9C) +#define RCC_MC_AHB3ENSETR U(0xAA0) +#define RCC_MC_AHB3ENCLRR U(0xAA4) +#define RCC_MC_AHB4ENSETR U(0xAA8) +#define RCC_MC_AHB4ENCLRR U(0xAAC) +#define RCC_MC_AXIMENSETR U(0xAB0) +#define RCC_MC_AXIMENCLRR U(0xAB4) +#define RCC_MC_MLAHBENSETR U(0xAB8) +#define RCC_MC_MLAHBENCLRR U(0xABC) +#define RCC_MP_APB1LPENSETR U(0xB00) +#define RCC_MP_APB1LPENCLRR U(0xB04) +#define RCC_MP_APB2LPENSETR U(0xB08) +#define RCC_MP_APB2LPENCLRR U(0xB0C) +#define RCC_MP_APB3LPENSETR U(0xB10) +#define RCC_MP_APB3LPENCLRR U(0xB14) +#define RCC_MP_AHB2LPENSETR U(0xB18) +#define RCC_MP_AHB2LPENCLRR U(0xB1C) +#define RCC_MP_AHB3LPENSETR U(0xB20) +#define RCC_MP_AHB3LPENCLRR U(0xB24) +#define RCC_MP_AHB4LPENSETR U(0xB28) +#define RCC_MP_AHB4LPENCLRR U(0xB2C) +#define RCC_MP_AXIMLPENSETR U(0xB30) +#define RCC_MP_AXIMLPENCLRR U(0xB34) +#define RCC_MP_MLAHBLPENSETR U(0xB38) +#define RCC_MP_MLAHBLPENCLRR U(0xB3C) +#define RCC_MC_APB1LPENSETR U(0xB80) +#define RCC_MC_APB1LPENCLRR U(0xB84) +#define RCC_MC_APB2LPENSETR U(0xB88) +#define RCC_MC_APB2LPENCLRR U(0xB8C) +#define RCC_MC_APB3LPENSETR U(0xB90) +#define RCC_MC_APB3LPENCLRR U(0xB94) +#define RCC_MC_AHB2LPENSETR U(0xB98) +#define RCC_MC_AHB2LPENCLRR U(0xB9C) +#define RCC_MC_AHB3LPENSETR U(0xBA0) +#define RCC_MC_AHB3LPENCLRR U(0xBA4) +#define RCC_MC_AHB4LPENSETR U(0xBA8) +#define RCC_MC_AHB4LPENCLRR U(0xBAC) +#define RCC_MC_AXIMLPENSETR U(0xBB0) +#define RCC_MC_AXIMLPENCLRR U(0xBB4) +#define RCC_MC_MLAHBLPENSETR U(0xBB8) +#define RCC_MC_MLAHBLPENCLRR U(0xBBC) +#define RCC_MC_RSTSCLRR U(0xC00) +#define RCC_MC_CIER U(0xC14) +#define RCC_MC_CIFR U(0xC18) +#define RCC_VERR U(0xFF4) +#define RCC_IDR U(0xFF8) +#define RCC_SIDR U(0xFFC) + +/* RCC_TZCR register fields */ +#define RCC_TZCR_TZEN BIT(0) +#define RCC_TZCR_MCKPROT BIT(1) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_CSION BIT(4) +#define RCC_OCENSETR_CSIKERON BIT(5) +#define RCC_OCENSETR_DIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_CSION BIT(4) +#define RCC_OCENCLRR_CSIKERON BIT(5) +#define RCC_OCENCLRR_DIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) +#define RCC_HSICFGR_HSIDIV_SHIFT 0 +#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 +#define RCC_HSICFGR_HSICAL_TEMP_MASK GENMASK(27, 25) + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_MPCKSELR register fields */ +#define RCC_MPCKSELR_HSI 0x00000000 +#define RCC_MPCKSELR_HSE 0x00000001 +#define RCC_MPCKSELR_PLL 0x00000002 +#define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 +#define RCC_MPCKSELR_MPUSRC_MASK GENMASK(1, 0) +#define RCC_MPCKSELR_MPUSRC_SHIFT 0 +#define RCC_MPCKSELR_MPUSRCRDY BIT(31) + +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_HSI 0x00000000 +#define RCC_ASSCKSELR_HSE 0x00000001 +#define RCC_ASSCKSELR_PLL 0x00000002 +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 +#define RCC_ASSCKSELR_AXISSRCRDY BIT(31) + +/* RCC_RCK12SELR register fields */ +#define RCC_RCK12SELR_PLL12SRC_MASK GENMASK(1, 0) +#define RCC_RCK12SELR_PLL12SRC_SHIFT 0 +#define RCC_RCK12SELR_PLL12SRCRDY BIT(31) + +/* RCC_MPCKDIVR register fields */ +#define RCC_MPCKDIVR_MPUDIV_MASK GENMASK(2, 0) +#define RCC_MPCKDIVR_MPUDIV_SHIFT 0 +#define RCC_MPCKDIVR_MPUDIVRDY BIT(31) + +/* RCC_AXIDIVR register fields */ +#define RCC_AXIDIVR_AXIDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIVR_AXIDIV_SHIFT 0 +#define RCC_AXIDIVR_AXIDIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APB5DIVR register fields */ +#define RCC_APB5DIVR_APB5DIV_MASK GENMASK(2, 0) +#define RCC_APB5DIVR_APB5DIV_SHIFT 0 +#define RCC_APB5DIVR_APB5DIVRDY BIT(31) + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_HSI 0x00000000 +#define RCC_MSSCKSELR_HSE 0x00000001 +#define RCC_MSSCKSELR_CSI 0x00000002 +#define RCC_MSSCKSELR_PLL 0x00000003 +#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 +#define RCC_MSSCKSELR_MCUSSRCRDY BIT(31) + +/* RCC_PLL1CR register fields */ +#define RCC_PLL1CR_PLLON BIT(0) +#define RCC_PLL1CR_PLL1RDY BIT(1) +#define RCC_PLL1CR_SSCG_CTRL BIT(2) +#define RCC_PLL1CR_DIVPEN BIT(4) +#define RCC_PLL1CR_DIVQEN BIT(5) +#define RCC_PLL1CR_DIVREN BIT(6) + +/* RCC_PLL1CFGR1 register fields */ +#define RCC_PLL1CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL1CFGR1_DIVN_SHIFT 0 +#define RCC_PLL1CFGR1_DIVM1_MASK GENMASK(21, 16) +#define RCC_PLL1CFGR1_DIVM1_SHIFT 16 + +/* RCC_PLL1CFGR2 register fields */ +#define RCC_PLL1CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL1CFGR2_DIVP_SHIFT 0 +#define RCC_PLL1CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL1CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL1CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL1CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL1FRACR register fields */ +#define RCC_PLL1FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL1FRACR_FRACV_SHIFT 3 +#define RCC_PLL1FRACR_FRACLE BIT(16) + +/* RCC_PLL1CSGR register fields */ +#define RCC_PLL1CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL1CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL1CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL1CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL1CSGR_SSCG_MODE BIT(15) +#define RCC_PLL1CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL1CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL2CR register fields */ +#define RCC_PLL2CR_PLLON BIT(0) +#define RCC_PLL2CR_PLL2RDY BIT(1) +#define RCC_PLL2CR_SSCG_CTRL BIT(2) +#define RCC_PLL2CR_DIVPEN BIT(4) +#define RCC_PLL2CR_DIVQEN BIT(5) +#define RCC_PLL2CR_DIVREN BIT(6) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL2CFGR1_DIVN_SHIFT 0 +#define RCC_PLL2CFGR1_DIVM2_MASK GENMASK(21, 16) +#define RCC_PLL2CFGR1_DIVM2_SHIFT 16 + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL2CFGR2_DIVP_SHIFT 0 +#define RCC_PLL2CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL2CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL2CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL2CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL2FRACR register fields */ +#define RCC_PLL2FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL2FRACR_FRACV_SHIFT 3 +#define RCC_PLL2FRACR_FRACLE BIT(16) + +/* RCC_PLL2CSGR register fields */ +#define RCC_PLL2CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL2CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL2CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL2CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL2CSGR_SSCG_MODE BIT(15) +#define RCC_PLL2CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL2CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C46CKSELR register fields */ +#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) +#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 + +/* RCC_SPI6CKSELR register fields */ +#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) +#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 + +/* RCC_UART1CKSELR register fields */ +#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_CPERCKSELR register fields */ +#define RCC_CPERCKSELR_HSI 0x00000000 +#define RCC_CPERCKSELR_CSI 0x00000001 +#define RCC_CPERCKSELR_HSE 0x00000002 +#define RCC_CPERCKSELR_CKPERSRC_MASK GENMASK(1, 0) +#define RCC_CPERCKSELR_CKPERSRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_DDRITFCR register fields */ +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRC2EN BIT(2) +#define RCC_DDRITFCR_DDRC2LPEN BIT(3) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_KERDCG_DLY_MASK GENMASK(13, 11) +#define RCC_DDRITFCR_KERDCG_DLY_SHIFT 11 +#define RCC_DDRITFCR_DDRCAPBRST BIT(14) +#define RCC_DDRITFCR_DDRCAXIRST BIT(15) +#define RCC_DDRITFCR_DDRCORERST BIT(16) +#define RCC_DDRITFCR_DPHYAPBRST BIT(17) +#define RCC_DDRITFCR_DPHYRST BIT(18) +#define RCC_DDRITFCR_DPHYCTLRST BIT(19) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 +#define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) +#define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) +#define RCC_DDRITFCR_GSKPMOD BIT(23) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) +#define RCC_DDRITFCR_DFILP_WIDTH_MASK GENMASK(27, 25) +#define RCC_DDRITFCR_DFILP_WIDTH_SHIFT 25 +#define RCC_DDRITFCR_GSKP_DUR_MASK GENMASK(31, 28) +#define RCC_DDRITFCR_GSKP_DUR_SHIFT 28 + +/* RCC_MP_BOOTCR register fields */ +#define RCC_MP_BOOTCR_MCU_BEN BIT(0) +#define RCC_MP_BOOTCR_MPU_BEN BIT(1) + +/* RCC_MP_SREQSETR register fields */ +#define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) + +/* RCC_MP_SREQCLRR register fields */ +#define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) + +/* RCC_MP_GCR register fields */ +#define RCC_MP_GCR_BOOT_MCU BIT(0) + +/* RCC_MP_APRSTCR register fields */ +#define RCC_MP_APRSTCR_RDCTLEN BIT(0) +#define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8) +#define RCC_MP_APRSTCR_RSTTO_SHIFT 8 + +/* RCC_MP_APRSTSR register fields */ +#define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8) +#define RCC_MP_APRSTSR_RSTTOV_SHIFT 8 + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_LSECSSD BIT(9) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_VSWRST BIT(31) + +/* RCC_RDLSICR register fields */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) +#define RCC_RDLSICR_MRD_MASK GENMASK(20, 16) +#define RCC_RDLSICR_MRD_SHIFT 16 +#define RCC_RDLSICR_EADLY_MASK GENMASK(26, 24) +#define RCC_RDLSICR_EADLY_SHIFT 24 +#define RCC_RDLSICR_SPARE_MASK GENMASK(31, 27) +#define RCC_RDLSICR_SPARE_SHIFT 27 + +/* RCC_APB4RSTSETR register fields */ +#define RCC_APB4RSTSETR_LTDCRST BIT(0) +#define RCC_APB4RSTSETR_DSIRST BIT(4) +#define RCC_APB4RSTSETR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTSETR_USBPHYRST BIT(16) + +/* RCC_APB4RSTCLRR register fields */ +#define RCC_APB4RSTCLRR_LTDCRST BIT(0) +#define RCC_APB4RSTCLRR_DSIRST BIT(4) +#define RCC_APB4RSTCLRR_DDRPERFMRST BIT(8) +#define RCC_APB4RSTCLRR_USBPHYRST BIT(16) + +/* RCC_APB5RSTSETR register fields */ +#define RCC_APB5RSTSETR_SPI6RST BIT(0) +#define RCC_APB5RSTSETR_I2C4RST BIT(2) +#define RCC_APB5RSTSETR_I2C6RST BIT(3) +#define RCC_APB5RSTSETR_USART1RST BIT(4) +#define RCC_APB5RSTSETR_STGENRST BIT(20) + +/* RCC_APB5RSTCLRR register fields */ +#define RCC_APB5RSTCLRR_SPI6RST BIT(0) +#define RCC_APB5RSTCLRR_I2C4RST BIT(2) +#define RCC_APB5RSTCLRR_I2C6RST BIT(3) +#define RCC_APB5RSTCLRR_USART1RST BIT(4) +#define RCC_APB5RSTCLRR_STGENRST BIT(20) + +/* RCC_AHB5RSTSETR register fields */ +#define RCC_AHB5RSTSETR_GPIOZRST BIT(0) +#define RCC_AHB5RSTSETR_CRYP1RST BIT(4) +#define RCC_AHB5RSTSETR_HASH1RST BIT(5) +#define RCC_AHB5RSTSETR_RNG1RST BIT(6) +#define RCC_AHB5RSTSETR_AXIMCRST BIT(16) + +/* RCC_AHB5RSTCLRR register fields */ +#define RCC_AHB5RSTCLRR_GPIOZRST BIT(0) +#define RCC_AHB5RSTCLRR_CRYP1RST BIT(4) +#define RCC_AHB5RSTCLRR_HASH1RST BIT(5) +#define RCC_AHB5RSTCLRR_RNG1RST BIT(6) +#define RCC_AHB5RSTCLRR_AXIMCRST BIT(16) + +/* RCC_AHB6RSTSETR register fields */ +#define RCC_AHB6RSTSETR_GPURST BIT(5) +#define RCC_AHB6RSTSETR_ETHMACRST BIT(10) +#define RCC_AHB6RSTSETR_FMCRST BIT(12) +#define RCC_AHB6RSTSETR_QSPIRST BIT(14) +#define RCC_AHB6RSTSETR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTSETR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTSETR_CRC1RST BIT(20) +#define RCC_AHB6RSTSETR_USBHRST BIT(24) + +/* RCC_AHB6RSTCLRR register fields */ +#define RCC_AHB6RSTCLRR_ETHMACRST BIT(10) +#define RCC_AHB6RSTCLRR_FMCRST BIT(12) +#define RCC_AHB6RSTCLRR_QSPIRST BIT(14) +#define RCC_AHB6RSTCLRR_SDMMC1RST BIT(16) +#define RCC_AHB6RSTCLRR_SDMMC2RST BIT(17) +#define RCC_AHB6RSTCLRR_CRC1RST BIT(20) +#define RCC_AHB6RSTCLRR_USBHRST BIT(24) + +/* RCC_TZAHB6RSTSETR register fields */ +#define RCC_TZAHB6RSTSETR_MDMARST BIT(0) + +/* RCC_TZAHB6RSTCLRR register fields */ +#define RCC_TZAHB6RSTCLRR_MDMARST BIT(0) + +/* RCC_MP_APB4ENSETR register fields */ +#define RCC_MP_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MP_APB4ENSETR_DSIEN BIT(4) +#define RCC_MP_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENSETR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MP_APB4ENCLRR register fields */ +#define RCC_MP_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MP_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MP_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MP_APB4ENCLRR_IWDG2APBEN BIT(15) +#define RCC_MP_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MP_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MP_APB5ENSETR register fields */ +#define RCC_MP_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MP_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MP_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MP_APB5ENSETR_USART1EN BIT(4) +#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MP_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MP_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENSETR_BSECEN BIT(16) +#define RCC_MP_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MP_APB5ENCLRR register fields */ +#define RCC_MP_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MP_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MP_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MP_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MP_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MP_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MP_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MP_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MP_APB5ENCLRR_IWDG1APBEN BIT(15) +#define RCC_MP_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MP_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MP_AHB5ENSETR register fields */ +#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENSETR_AXIMCEN BIT(16) + +/* RCC_MP_AHB5ENCLRR register fields */ +#define RCC_MP_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MP_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MP_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MP_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MP_AHB5ENCLRR_BKPSRAMEN BIT(8) +#define RCC_MP_AHB5ENCLRR_AXIMCEN BIT(16) + +/* RCC_MP_AHB6ENSETR register fields */ +#define RCC_MP_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MP_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MP_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MP_AHB6ENCLRR register fields */ +#define RCC_MP_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MP_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MP_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MP_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MP_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MP_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MP_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MP_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MP_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MP_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MP_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MP_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_TZAHB6ENSETR register fields */ +#define RCC_MP_TZAHB6ENSETR_MDMAEN BIT(0) + +/* RCC_MP_TZAHB6ENCLRR register fields */ +#define RCC_MP_TZAHB6ENCLRR_MDMAEN BIT(0) + +/* RCC_MC_APB4ENSETR register fields */ +#define RCC_MC_APB4ENSETR_LTDCEN BIT(0) +#define RCC_MC_APB4ENSETR_DSIEN BIT(4) +#define RCC_MC_APB4ENSETR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENSETR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENSETR_STGENROEN BIT(20) + +/* RCC_MC_APB4ENCLRR register fields */ +#define RCC_MC_APB4ENCLRR_LTDCEN BIT(0) +#define RCC_MC_APB4ENCLRR_DSIEN BIT(4) +#define RCC_MC_APB4ENCLRR_DDRPERFMEN BIT(8) +#define RCC_MC_APB4ENCLRR_USBPHYEN BIT(16) +#define RCC_MC_APB4ENCLRR_STGENROEN BIT(20) + +/* RCC_MC_APB5ENSETR register fields */ +#define RCC_MC_APB5ENSETR_SPI6EN BIT(0) +#define RCC_MC_APB5ENSETR_I2C4EN BIT(2) +#define RCC_MC_APB5ENSETR_I2C6EN BIT(3) +#define RCC_MC_APB5ENSETR_USART1EN BIT(4) +#define RCC_MC_APB5ENSETR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENSETR_TZC1EN BIT(11) +#define RCC_MC_APB5ENSETR_TZC2EN BIT(12) +#define RCC_MC_APB5ENSETR_TZPCEN BIT(13) +#define RCC_MC_APB5ENSETR_BSECEN BIT(16) +#define RCC_MC_APB5ENSETR_STGENEN BIT(20) + +/* RCC_MC_APB5ENCLRR register fields */ +#define RCC_MC_APB5ENCLRR_SPI6EN BIT(0) +#define RCC_MC_APB5ENCLRR_I2C4EN BIT(2) +#define RCC_MC_APB5ENCLRR_I2C6EN BIT(3) +#define RCC_MC_APB5ENCLRR_USART1EN BIT(4) +#define RCC_MC_APB5ENCLRR_RTCAPBEN BIT(8) +#define RCC_MC_APB5ENCLRR_TZC1EN BIT(11) +#define RCC_MC_APB5ENCLRR_TZC2EN BIT(12) +#define RCC_MC_APB5ENCLRR_TZPCEN BIT(13) +#define RCC_MC_APB5ENCLRR_BSECEN BIT(16) +#define RCC_MC_APB5ENCLRR_STGENEN BIT(20) + +/* RCC_MC_AHB5ENSETR register fields */ +#define RCC_MC_AHB5ENSETR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENSETR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENSETR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENSETR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENSETR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB5ENCLRR register fields */ +#define RCC_MC_AHB5ENCLRR_GPIOZEN BIT(0) +#define RCC_MC_AHB5ENCLRR_CRYP1EN BIT(4) +#define RCC_MC_AHB5ENCLRR_HASH1EN BIT(5) +#define RCC_MC_AHB5ENCLRR_RNG1EN BIT(6) +#define RCC_MC_AHB5ENCLRR_BKPSRAMEN BIT(8) + +/* RCC_MC_AHB6ENSETR register fields */ +#define RCC_MC_AHB6ENSETR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENSETR_GPUEN BIT(5) +#define RCC_MC_AHB6ENSETR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENSETR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENSETR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENSETR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENSETR_FMCEN BIT(12) +#define RCC_MC_AHB6ENSETR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENSETR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENSETR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENSETR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENSETR_USBHEN BIT(24) + +/* RCC_MC_AHB6ENCLRR register fields */ +#define RCC_MC_AHB6ENCLRR_MDMAEN BIT(0) +#define RCC_MC_AHB6ENCLRR_GPUEN BIT(5) +#define RCC_MC_AHB6ENCLRR_ETHCKEN BIT(7) +#define RCC_MC_AHB6ENCLRR_ETHTXEN BIT(8) +#define RCC_MC_AHB6ENCLRR_ETHRXEN BIT(9) +#define RCC_MC_AHB6ENCLRR_ETHMACEN BIT(10) +#define RCC_MC_AHB6ENCLRR_FMCEN BIT(12) +#define RCC_MC_AHB6ENCLRR_QSPIEN BIT(14) +#define RCC_MC_AHB6ENCLRR_SDMMC1EN BIT(16) +#define RCC_MC_AHB6ENCLRR_SDMMC2EN BIT(17) +#define RCC_MC_AHB6ENCLRR_CRC1EN BIT(20) +#define RCC_MC_AHB6ENCLRR_USBHEN BIT(24) + +/* RCC_MP_APB4LPENSETR register fields */ +#define RCC_MP_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB4LPENCLRR register fields */ +#define RCC_MP_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MP_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MP_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN BIT(15) +#define RCC_MP_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MP_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MP_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MP_APB5LPENSETR register fields */ +#define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MP_APB5LPENCLRR register fields */ +#define RCC_MP_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MP_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MP_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MP_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MP_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MP_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MP_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MP_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN BIT(15) +#define RCC_MP_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MP_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MP_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MP_AHB5LPENSETR register fields */ +#define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB5LPENCLRR register fields */ +#define RCC_MP_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MP_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MP_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MP_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MP_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MP_AHB6LPENSETR register fields */ +#define RCC_MP_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MP_AHB6LPENCLRR register fields */ +#define RCC_MP_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MP_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MP_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MP_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MP_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MP_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MP_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MP_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MP_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MP_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MP_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MP_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MP_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_MP_TZAHB6LPENSETR register fields */ +#define RCC_MP_TZAHB6LPENSETR_MDMALPEN BIT(0) + +/* RCC_MP_TZAHB6LPENCLRR register fields */ +#define RCC_MP_TZAHB6LPENCLRR_MDMALPEN BIT(0) + +/* RCC_MC_APB4LPENSETR register fields */ +#define RCC_MC_APB4LPENSETR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENSETR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENSETR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENSETR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENSETR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENSETR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB4LPENCLRR register fields */ +#define RCC_MC_APB4LPENCLRR_LTDCLPEN BIT(0) +#define RCC_MC_APB4LPENCLRR_DSILPEN BIT(4) +#define RCC_MC_APB4LPENCLRR_DDRPERFMLPEN BIT(8) +#define RCC_MC_APB4LPENCLRR_USBPHYLPEN BIT(16) +#define RCC_MC_APB4LPENCLRR_STGENROLPEN BIT(20) +#define RCC_MC_APB4LPENCLRR_STGENROSTPEN BIT(21) + +/* RCC_MC_APB5LPENSETR register fields */ +#define RCC_MC_APB5LPENSETR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENSETR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENSETR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENSETR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENSETR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENSETR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENSETR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENSETR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENSETR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENSETR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENSETR_STGENSTPEN BIT(21) + +/* RCC_MC_APB5LPENCLRR register fields */ +#define RCC_MC_APB5LPENCLRR_SPI6LPEN BIT(0) +#define RCC_MC_APB5LPENCLRR_I2C4LPEN BIT(2) +#define RCC_MC_APB5LPENCLRR_I2C6LPEN BIT(3) +#define RCC_MC_APB5LPENCLRR_USART1LPEN BIT(4) +#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN BIT(8) +#define RCC_MC_APB5LPENCLRR_TZC1LPEN BIT(11) +#define RCC_MC_APB5LPENCLRR_TZC2LPEN BIT(12) +#define RCC_MC_APB5LPENCLRR_TZPCLPEN BIT(13) +#define RCC_MC_APB5LPENCLRR_BSECLPEN BIT(16) +#define RCC_MC_APB5LPENCLRR_STGENLPEN BIT(20) +#define RCC_MC_APB5LPENCLRR_STGENSTPEN BIT(21) + +/* RCC_MC_AHB5LPENSETR register fields */ +#define RCC_MC_AHB5LPENSETR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENSETR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENSETR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENSETR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB5LPENCLRR register fields */ +#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN BIT(0) +#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN BIT(4) +#define RCC_MC_AHB5LPENCLRR_HASH1LPEN BIT(5) +#define RCC_MC_AHB5LPENCLRR_RNG1LPEN BIT(6) +#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN BIT(8) + +/* RCC_MC_AHB6LPENSETR register fields */ +#define RCC_MC_AHB6LPENSETR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENSETR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENSETR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENSETR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENSETR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENSETR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENSETR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENSETR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENSETR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENSETR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENSETR_USBHLPEN BIT(24) + +/* RCC_MC_AHB6LPENCLRR register fields */ +#define RCC_MC_AHB6LPENCLRR_MDMALPEN BIT(0) +#define RCC_MC_AHB6LPENCLRR_GPULPEN BIT(5) +#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN BIT(7) +#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN BIT(8) +#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN BIT(9) +#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN BIT(10) +#define RCC_MC_AHB6LPENCLRR_ETHSTPEN BIT(11) +#define RCC_MC_AHB6LPENCLRR_FMCLPEN BIT(12) +#define RCC_MC_AHB6LPENCLRR_QSPILPEN BIT(14) +#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN BIT(16) +#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN BIT(17) +#define RCC_MC_AHB6LPENCLRR_CRC1LPEN BIT(20) +#define RCC_MC_AHB6LPENCLRR_USBHLPEN BIT(24) + +/* RCC_BR_RSTSCLRR register fields */ +#define RCC_BR_RSTSCLRR_PORRSTF BIT(0) +#define RCC_BR_RSTSCLRR_BORRSTF BIT(1) +#define RCC_BR_RSTSCLRR_PADRSTF BIT(2) +#define RCC_BR_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_BR_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_BR_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_BR_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_BR_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_BR_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_BR_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_BR_RSTSCLRR_MPUP1RSTF BIT(14) + +/* RCC_MP_GRSTCSETR register fields */ +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MCURST BIT(1) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) +#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) + +/* RCC_MP_RSTSCLRR register fields */ +#define RCC_MP_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MP_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MP_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSCLRR_SPARE BIT(15) + +/* RCC_MP_IWDGFZSETR register fields */ +#define RCC_MP_IWDGFZSETR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZSETR_FZ_IWDG2 BIT(1) + +/* RCC_MP_IWDGFZCLRR register fields */ +#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 BIT(0) +#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_MP_CIER register fields */ +#define RCC_MP_CIER_LSIRDYIE BIT(0) +#define RCC_MP_CIER_LSERDYIE BIT(1) +#define RCC_MP_CIER_HSIRDYIE BIT(2) +#define RCC_MP_CIER_HSERDYIE BIT(3) +#define RCC_MP_CIER_CSIRDYIE BIT(4) +#define RCC_MP_CIER_PLL1DYIE BIT(8) +#define RCC_MP_CIER_PLL2DYIE BIT(9) +#define RCC_MP_CIER_PLL3DYIE BIT(10) +#define RCC_MP_CIER_PLL4DYIE BIT(11) +#define RCC_MP_CIER_LSECSSIE BIT(16) +#define RCC_MP_CIER_WKUPIE BIT(20) + +/* RCC_MP_CIFR register fields */ +#define RCC_MP_CIFR_MASK U(0x110F1F) +#define RCC_MP_CIFR_LSIRDYF BIT(0) +#define RCC_MP_CIFR_LSERDYF BIT(1) +#define RCC_MP_CIFR_HSIRDYF BIT(2) +#define RCC_MP_CIFR_HSERDYF BIT(3) +#define RCC_MP_CIFR_CSIRDYF BIT(4) +#define RCC_MP_CIFR_PLL1DYF BIT(8) +#define RCC_MP_CIFR_PLL2DYF BIT(9) +#define RCC_MP_CIFR_PLL3DYF BIT(10) +#define RCC_MP_CIFR_PLL4DYF BIT(11) +#define RCC_MP_CIFR_LSECSSF BIT(16) +#define RCC_MP_CIFR_WKUPF BIT(20) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_MCTMPSKP BIT(24) + +/* RCC_MP_RSTSSETR register fields */ +#define RCC_MP_RSTSSETR_PORRSTF BIT(0) +#define RCC_MP_RSTSSETR_BORRSTF BIT(1) +#define RCC_MP_RSTSSETR_PADRSTF BIT(2) +#define RCC_MP_RSTSSETR_HCSSRSTF BIT(3) +#define RCC_MP_RSTSSETR_VCORERSTF BIT(4) +#define RCC_MP_RSTSSETR_MPSYSRSTF BIT(6) +#define RCC_MP_RSTSSETR_MCSYSRSTF BIT(7) +#define RCC_MP_RSTSSETR_IWDG1RSTF BIT(8) +#define RCC_MP_RSTSSETR_IWDG2RSTF BIT(9) +#define RCC_MP_RSTSSETR_STDBYRSTF BIT(11) +#define RCC_MP_RSTSSETR_CSTDBYRSTF BIT(12) +#define RCC_MP_RSTSSETR_MPUP0RSTF BIT(13) +#define RCC_MP_RSTSSETR_MPUP1RSTF BIT(14) +#define RCC_MP_RSTSSETR_SPARE BIT(15) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL_MASK GENMASK(2, 0) +#define RCC_MCO1CFGR_MCO1SEL_SHIFT 0 +#define RCC_MCO1CFGR_MCO1DIV_MASK GENMASK(7, 4) +#define RCC_MCO1CFGR_MCO1DIV_SHIFT 4 +#define RCC_MCO1CFGR_MCO1ON BIT(12) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL_MASK GENMASK(2, 0) +#define RCC_MCO2CFGR_MCO2SEL_SHIFT 0 +#define RCC_MCO2CFGR_MCO2DIV_MASK GENMASK(7, 4) +#define RCC_MCO2CFGR_MCO2DIV_SHIFT 4 +#define RCC_MCO2CFGR_MCO2ON BIT(12) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_MPUCKRDY BIT(23) +#define RCC_OCRDYR_AXICKRDY BIT(24) +#define RCC_OCRDYR_CKREST BIT(25) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_TRACEDIV_MASK GENMASK(2, 0) +#define RCC_DBGCFGR_TRACEDIV_SHIFT 0 +#define RCC_DBGCFGR_DBGCKEN BIT(8) +#define RCC_DBGCFGR_TRACECKEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_RCK3SELR register fields */ +#define RCC_RCK3SELR_PLL3SRC_MASK GENMASK(1, 0) +#define RCC_RCK3SELR_PLL3SRC_SHIFT 0 +#define RCC_RCK3SELR_PLL3SRCRDY BIT(31) + +/* RCC_RCK4SELR register fields */ +#define RCC_RCK4SELR_PLL4SRC_MASK GENMASK(1, 0) +#define RCC_RCK4SELR_PLL4SRC_SHIFT 0 +#define RCC_RCK4SELR_PLL4SRCRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_MCUDIVR register fields */ +#define RCC_MCUDIVR_MCUDIV_MASK GENMASK(3, 0) +#define RCC_MCUDIVR_MCUDIV_SHIFT 0 +#define RCC_MCUDIVR_MCUDIVRDY BIT(31) + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_PLL3CR register fields */ +#define RCC_PLL3CR_PLLON BIT(0) +#define RCC_PLL3CR_PLL3RDY BIT(1) +#define RCC_PLL3CR_SSCG_CTRL BIT(2) +#define RCC_PLL3CR_DIVPEN BIT(4) +#define RCC_PLL3CR_DIVQEN BIT(5) +#define RCC_PLL3CR_DIVREN BIT(6) + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL3CFGR1_DIVN_SHIFT 0 +#define RCC_PLL3CFGR1_DIVM3_MASK GENMASK(21, 16) +#define RCC_PLL3CFGR1_DIVM3_SHIFT 16 +#define RCC_PLL3CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL3CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL3CFGR2_DIVP_SHIFT 0 +#define RCC_PLL3CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL3CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL3CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL3CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL3FRACR register fields */ +#define RCC_PLL3FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL3FRACR_FRACV_SHIFT 3 +#define RCC_PLL3FRACR_FRACLE BIT(16) + +/* RCC_PLL3CSGR register fields */ +#define RCC_PLL3CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL3CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL3CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL3CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL3CSGR_SSCG_MODE BIT(15) +#define RCC_PLL3CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL3CSGR_INC_STEP_SHIFT 16 + +/* RCC_PLL4CR register fields */ +#define RCC_PLL4CR_PLLON BIT(0) +#define RCC_PLL4CR_PLL4RDY BIT(1) +#define RCC_PLL4CR_SSCG_CTRL BIT(2) +#define RCC_PLL4CR_DIVPEN BIT(4) +#define RCC_PLL4CR_DIVQEN BIT(5) +#define RCC_PLL4CR_DIVREN BIT(6) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLL4CFGR1_DIVN_SHIFT 0 +#define RCC_PLL4CFGR1_DIVM4_MASK GENMASK(21, 16) +#define RCC_PLL4CFGR1_DIVM4_SHIFT 16 +#define RCC_PLL4CFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLL4CFGR1_IFRGE_SHIFT 24 + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLL4CFGR2_DIVP_SHIFT 0 +#define RCC_PLL4CFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLL4CFGR2_DIVQ_SHIFT 8 +#define RCC_PLL4CFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLL4CFGR2_DIVR_SHIFT 16 + +/* RCC_PLL4FRACR register fields */ +#define RCC_PLL4FRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLL4FRACR_FRACV_SHIFT 3 +#define RCC_PLL4FRACR_FRACLE BIT(16) + +/* RCC_PLL4CSGR register fields */ +#define RCC_PLL4CSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLL4CSGR_MOD_PER_SHIFT 0 +#define RCC_PLL4CSGR_TPDFN_DIS BIT(13) +#define RCC_PLL4CSGR_RPDFN_DIS BIT(14) +#define RCC_PLL4CSGR_SSCG_MODE BIT(15) +#define RCC_PLL4CSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLL4CSGR_INC_STEP_SHIFT 16 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C35CKSELR register fields */ +#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) +#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 + +/* RCC_SAI1CKSELR register fields */ +#define RCC_SAI1CKSELR_SAI1SRC_MASK GENMASK(2, 0) +#define RCC_SAI1CKSELR_SAI1SRC_SHIFT 0 + +/* RCC_SAI2CKSELR register fields */ +#define RCC_SAI2CKSELR_SAI2SRC_MASK GENMASK(2, 0) +#define RCC_SAI2CKSELR_SAI2SRC_SHIFT 0 + +/* RCC_SAI3CKSELR register fields */ +#define RCC_SAI3CKSELR_SAI3SRC_MASK GENMASK(2, 0) +#define RCC_SAI3CKSELR_SAI3SRC_SHIFT 0 + +/* RCC_SAI4CKSELR register fields */ +#define RCC_SAI4CKSELR_SAI4SRC_MASK GENMASK(2, 0) +#define RCC_SAI4CKSELR_SAI4SRC_SHIFT 0 + +/* RCC_SPI2S1CKSELR register fields */ +#define RCC_SPI2S1CKSELR_SPI1SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S1CKSELR_SPI1SRC_SHIFT 0 + +/* RCC_SPI2S23CKSELR register fields */ +#define RCC_SPI2S23CKSELR_SPI23SRC_MASK GENMASK(2, 0) +#define RCC_SPI2S23CKSELR_SPI23SRC_SHIFT 0 + +/* RCC_SPI45CKSELR register fields */ +#define RCC_SPI45CKSELR_SPI45SRC_MASK GENMASK(2, 0) +#define RCC_SPI45CKSELR_SPI45SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART24CKSELR register fields */ +#define RCC_UART24CKSELR_HSI 0x00000002 +#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) +#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 + +/* RCC_SDMMC3CKSELR register fields */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 + +/* RCC_ETHCKSELR register fields */ +#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) +#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 +#define RCC_ETHCKSELR_ETHPTPDIV_MASK GENMASK(7, 4) +#define RCC_ETHCKSELR_ETHPTPDIV_SHIFT 4 + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_FDCANCKSELR register fields */ +#define RCC_FDCANCKSELR_FDCANSRC_MASK GENMASK(1, 0) +#define RCC_FDCANCKSELR_FDCANSRC_SHIFT 0 + +/* RCC_SPDIFCKSELR register fields */ +#define RCC_SPDIFCKSELR_SPDIFSRC_MASK GENMASK(1, 0) +#define RCC_SPDIFCKSELR_SPDIFSRC_SHIFT 0 + +/* RCC_CECCKSELR register fields */ +#define RCC_CECCKSELR_CECSRC_MASK GENMASK(1, 0) +#define RCC_CECCKSELR_CECSRC_SHIFT 0 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC BIT(4) +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + +/* RCC_RNG2CKSELR register fields */ +#define RCC_RNG2CKSELR_RNG2SRC_MASK GENMASK(1, 0) +#define RCC_RNG2CKSELR_RNG2SRC_SHIFT 0 + +/* RCC_DSICKSELR register fields */ +#define RCC_DSICKSELR_DSISRC BIT(0) + +/* RCC_ADCCKSELR register fields */ +#define RCC_ADCCKSELR_ADCSRC_MASK GENMASK(1, 0) +#define RCC_ADCCKSELR_ADCSRC_SHIFT 0 + +/* RCC_LPTIM45CKSELR register fields */ +#define RCC_LPTIM45CKSELR_LPTIM45SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM45CKSELR_LPTIM45SRC_SHIFT 0 + +/* RCC_LPTIM23CKSELR register fields */ +#define RCC_LPTIM23CKSELR_LPTIM23SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM23CKSELR_LPTIM23SRC_SHIFT 0 + +/* RCC_LPTIM1CKSELR register fields */ +#define RCC_LPTIM1CKSELR_LPTIM1SRC_MASK GENMASK(2, 0) +#define RCC_LPTIM1CKSELR_LPTIM1SRC_SHIFT 0 + +/* RCC_APB1RSTSETR register fields */ +#define RCC_APB1RSTSETR_TIM2RST BIT(0) +#define RCC_APB1RSTSETR_TIM3RST BIT(1) +#define RCC_APB1RSTSETR_TIM4RST BIT(2) +#define RCC_APB1RSTSETR_TIM5RST BIT(3) +#define RCC_APB1RSTSETR_TIM6RST BIT(4) +#define RCC_APB1RSTSETR_TIM7RST BIT(5) +#define RCC_APB1RSTSETR_TIM12RST BIT(6) +#define RCC_APB1RSTSETR_TIM13RST BIT(7) +#define RCC_APB1RSTSETR_TIM14RST BIT(8) +#define RCC_APB1RSTSETR_LPTIM1RST BIT(9) +#define RCC_APB1RSTSETR_SPI2RST BIT(11) +#define RCC_APB1RSTSETR_SPI3RST BIT(12) +#define RCC_APB1RSTSETR_USART2RST BIT(14) +#define RCC_APB1RSTSETR_USART3RST BIT(15) +#define RCC_APB1RSTSETR_UART4RST BIT(16) +#define RCC_APB1RSTSETR_UART5RST BIT(17) +#define RCC_APB1RSTSETR_UART7RST BIT(18) +#define RCC_APB1RSTSETR_UART8RST BIT(19) +#define RCC_APB1RSTSETR_I2C1RST BIT(21) +#define RCC_APB1RSTSETR_I2C2RST BIT(22) +#define RCC_APB1RSTSETR_I2C3RST BIT(23) +#define RCC_APB1RSTSETR_I2C5RST BIT(24) +#define RCC_APB1RSTSETR_SPDIFRST BIT(26) +#define RCC_APB1RSTSETR_CECRST BIT(27) +#define RCC_APB1RSTSETR_DAC12RST BIT(29) +#define RCC_APB1RSTSETR_MDIOSRST BIT(31) + +/* RCC_APB1RSTCLRR register fields */ +#define RCC_APB1RSTCLRR_TIM2RST BIT(0) +#define RCC_APB1RSTCLRR_TIM3RST BIT(1) +#define RCC_APB1RSTCLRR_TIM4RST BIT(2) +#define RCC_APB1RSTCLRR_TIM5RST BIT(3) +#define RCC_APB1RSTCLRR_TIM6RST BIT(4) +#define RCC_APB1RSTCLRR_TIM7RST BIT(5) +#define RCC_APB1RSTCLRR_TIM12RST BIT(6) +#define RCC_APB1RSTCLRR_TIM13RST BIT(7) +#define RCC_APB1RSTCLRR_TIM14RST BIT(8) +#define RCC_APB1RSTCLRR_LPTIM1RST BIT(9) +#define RCC_APB1RSTCLRR_SPI2RST BIT(11) +#define RCC_APB1RSTCLRR_SPI3RST BIT(12) +#define RCC_APB1RSTCLRR_USART2RST BIT(14) +#define RCC_APB1RSTCLRR_USART3RST BIT(15) +#define RCC_APB1RSTCLRR_UART4RST BIT(16) +#define RCC_APB1RSTCLRR_UART5RST BIT(17) +#define RCC_APB1RSTCLRR_UART7RST BIT(18) +#define RCC_APB1RSTCLRR_UART8RST BIT(19) +#define RCC_APB1RSTCLRR_I2C1RST BIT(21) +#define RCC_APB1RSTCLRR_I2C2RST BIT(22) +#define RCC_APB1RSTCLRR_I2C3RST BIT(23) +#define RCC_APB1RSTCLRR_I2C5RST BIT(24) +#define RCC_APB1RSTCLRR_SPDIFRST BIT(26) +#define RCC_APB1RSTCLRR_CECRST BIT(27) +#define RCC_APB1RSTCLRR_DAC12RST BIT(29) +#define RCC_APB1RSTCLRR_MDIOSRST BIT(31) + +/* RCC_APB2RSTSETR register fields */ +#define RCC_APB2RSTSETR_TIM1RST BIT(0) +#define RCC_APB2RSTSETR_TIM8RST BIT(1) +#define RCC_APB2RSTSETR_TIM15RST BIT(2) +#define RCC_APB2RSTSETR_TIM16RST BIT(3) +#define RCC_APB2RSTSETR_TIM17RST BIT(4) +#define RCC_APB2RSTSETR_SPI1RST BIT(8) +#define RCC_APB2RSTSETR_SPI4RST BIT(9) +#define RCC_APB2RSTSETR_SPI5RST BIT(10) +#define RCC_APB2RSTSETR_USART6RST BIT(13) +#define RCC_APB2RSTSETR_SAI1RST BIT(16) +#define RCC_APB2RSTSETR_SAI2RST BIT(17) +#define RCC_APB2RSTSETR_SAI3RST BIT(18) +#define RCC_APB2RSTSETR_DFSDMRST BIT(20) +#define RCC_APB2RSTSETR_FDCANRST BIT(24) + +/* RCC_APB2RSTCLRR register fields */ +#define RCC_APB2RSTCLRR_TIM1RST BIT(0) +#define RCC_APB2RSTCLRR_TIM8RST BIT(1) +#define RCC_APB2RSTCLRR_TIM15RST BIT(2) +#define RCC_APB2RSTCLRR_TIM16RST BIT(3) +#define RCC_APB2RSTCLRR_TIM17RST BIT(4) +#define RCC_APB2RSTCLRR_SPI1RST BIT(8) +#define RCC_APB2RSTCLRR_SPI4RST BIT(9) +#define RCC_APB2RSTCLRR_SPI5RST BIT(10) +#define RCC_APB2RSTCLRR_USART6RST BIT(13) +#define RCC_APB2RSTCLRR_SAI1RST BIT(16) +#define RCC_APB2RSTCLRR_SAI2RST BIT(17) +#define RCC_APB2RSTCLRR_SAI3RST BIT(18) +#define RCC_APB2RSTCLRR_DFSDMRST BIT(20) +#define RCC_APB2RSTCLRR_FDCANRST BIT(24) + +/* RCC_APB3RSTSETR register fields */ +#define RCC_APB3RSTSETR_LPTIM2RST BIT(0) +#define RCC_APB3RSTSETR_LPTIM3RST BIT(1) +#define RCC_APB3RSTSETR_LPTIM4RST BIT(2) +#define RCC_APB3RSTSETR_LPTIM5RST BIT(3) +#define RCC_APB3RSTSETR_SAI4RST BIT(8) +#define RCC_APB3RSTSETR_SYSCFGRST BIT(11) +#define RCC_APB3RSTSETR_VREFRST BIT(13) +#define RCC_APB3RSTSETR_TMPSENSRST BIT(16) +#define RCC_APB3RSTSETR_PMBCTRLRST BIT(17) + +/* RCC_APB3RSTCLRR register fields */ +#define RCC_APB3RSTCLRR_LPTIM2RST BIT(0) +#define RCC_APB3RSTCLRR_LPTIM3RST BIT(1) +#define RCC_APB3RSTCLRR_LPTIM4RST BIT(2) +#define RCC_APB3RSTCLRR_LPTIM5RST BIT(3) +#define RCC_APB3RSTCLRR_SAI4RST BIT(8) +#define RCC_APB3RSTCLRR_SYSCFGRST BIT(11) +#define RCC_APB3RSTCLRR_VREFRST BIT(13) +#define RCC_APB3RSTCLRR_TMPSENSRST BIT(16) +#define RCC_APB3RSTCLRR_PMBCTRLRST BIT(17) + +/* RCC_AHB2RSTSETR register fields */ +#define RCC_AHB2RSTSETR_DMA1RST BIT(0) +#define RCC_AHB2RSTSETR_DMA2RST BIT(1) +#define RCC_AHB2RSTSETR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTSETR_ADC12RST BIT(5) +#define RCC_AHB2RSTSETR_USBORST BIT(8) +#define RCC_AHB2RSTSETR_SDMMC3RST BIT(16) + +/* RCC_AHB2RSTCLRR register fields */ +#define RCC_AHB2RSTCLRR_DMA1RST BIT(0) +#define RCC_AHB2RSTCLRR_DMA2RST BIT(1) +#define RCC_AHB2RSTCLRR_DMAMUXRST BIT(2) +#define RCC_AHB2RSTCLRR_ADC12RST BIT(5) +#define RCC_AHB2RSTCLRR_USBORST BIT(8) +#define RCC_AHB2RSTCLRR_SDMMC3RST BIT(16) + +/* RCC_AHB3RSTSETR register fields */ +#define RCC_AHB3RSTSETR_DCMIRST BIT(0) +#define RCC_AHB3RSTSETR_CRYP2RST BIT(4) +#define RCC_AHB3RSTSETR_HASH2RST BIT(5) +#define RCC_AHB3RSTSETR_RNG2RST BIT(6) +#define RCC_AHB3RSTSETR_CRC2RST BIT(7) +#define RCC_AHB3RSTSETR_HSEMRST BIT(11) +#define RCC_AHB3RSTSETR_IPCCRST BIT(12) + +/* RCC_AHB3RSTCLRR register fields */ +#define RCC_AHB3RSTCLRR_DCMIRST BIT(0) +#define RCC_AHB3RSTCLRR_CRYP2RST BIT(4) +#define RCC_AHB3RSTCLRR_HASH2RST BIT(5) +#define RCC_AHB3RSTCLRR_RNG2RST BIT(6) +#define RCC_AHB3RSTCLRR_CRC2RST BIT(7) +#define RCC_AHB3RSTCLRR_HSEMRST BIT(11) +#define RCC_AHB3RSTCLRR_IPCCRST BIT(12) + +/* RCC_AHB4RSTSETR register fields */ +#define RCC_AHB4RSTSETR_GPIOARST BIT(0) +#define RCC_AHB4RSTSETR_GPIOBRST BIT(1) +#define RCC_AHB4RSTSETR_GPIOCRST BIT(2) +#define RCC_AHB4RSTSETR_GPIODRST BIT(3) +#define RCC_AHB4RSTSETR_GPIOERST BIT(4) +#define RCC_AHB4RSTSETR_GPIOFRST BIT(5) +#define RCC_AHB4RSTSETR_GPIOGRST BIT(6) +#define RCC_AHB4RSTSETR_GPIOHRST BIT(7) +#define RCC_AHB4RSTSETR_GPIOIRST BIT(8) +#define RCC_AHB4RSTSETR_GPIOJRST BIT(9) +#define RCC_AHB4RSTSETR_GPIOKRST BIT(10) + +/* RCC_AHB4RSTCLRR register fields */ +#define RCC_AHB4RSTCLRR_GPIOARST BIT(0) +#define RCC_AHB4RSTCLRR_GPIOBRST BIT(1) +#define RCC_AHB4RSTCLRR_GPIOCRST BIT(2) +#define RCC_AHB4RSTCLRR_GPIODRST BIT(3) +#define RCC_AHB4RSTCLRR_GPIOERST BIT(4) +#define RCC_AHB4RSTCLRR_GPIOFRST BIT(5) +#define RCC_AHB4RSTCLRR_GPIOGRST BIT(6) +#define RCC_AHB4RSTCLRR_GPIOHRST BIT(7) +#define RCC_AHB4RSTCLRR_GPIOIRST BIT(8) +#define RCC_AHB4RSTCLRR_GPIOJRST BIT(9) +#define RCC_AHB4RSTCLRR_GPIOKRST BIT(10) + +/* RCC_MP_APB1ENSETR register fields */ +#define RCC_MP_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MP_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MP_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MP_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MP_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MP_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MP_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MP_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MP_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MP_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MP_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MP_APB1ENSETR_USART2EN BIT(14) +#define RCC_MP_APB1ENSETR_USART3EN BIT(15) +#define RCC_MP_APB1ENSETR_UART4EN BIT(16) +#define RCC_MP_APB1ENSETR_UART5EN BIT(17) +#define RCC_MP_APB1ENSETR_UART7EN BIT(18) +#define RCC_MP_APB1ENSETR_UART8EN BIT(19) +#define RCC_MP_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MP_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MP_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MP_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MP_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENSETR_CECEN BIT(27) +#define RCC_MP_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MP_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MP_APB1ENCLRR register fields */ +#define RCC_MP_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MP_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MP_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MP_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MP_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MP_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MP_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MP_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MP_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MP_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MP_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MP_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MP_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MP_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MP_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MP_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MP_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MP_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MP_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MP_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MP_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MP_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MP_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MP_APB1ENCLRR_CECEN BIT(27) +#define RCC_MP_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MP_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MP_APB2ENSETR register fields */ +#define RCC_MP_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MP_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MP_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MP_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MP_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MP_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MP_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MP_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MP_APB2ENSETR_USART6EN BIT(13) +#define RCC_MP_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MP_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MP_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MP_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MP_APB2ENCLRR register fields */ +#define RCC_MP_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MP_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MP_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MP_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MP_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MP_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MP_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MP_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MP_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MP_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MP_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MP_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MP_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MP_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MP_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MP_APB3ENSETR register fields */ +#define RCC_MP_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MP_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENSETR_VREFEN BIT(13) +#define RCC_MP_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MP_APB3ENCLRR register fields */ +#define RCC_MP_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MP_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MP_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MP_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MP_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MP_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MP_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MP_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MP_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MP_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MP_AHB2ENSETR register fields */ +#define RCC_MP_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MP_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB2ENCLRR register fields */ +#define RCC_MP_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MP_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MP_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MP_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MP_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MP_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MP_AHB3ENSETR register fields */ +#define RCC_MP_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MP_AHB3ENCLRR register fields */ +#define RCC_MP_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MP_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MP_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MP_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MP_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MP_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MP_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MP_AHB4ENSETR register fields */ +#define RCC_MP_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MP_AHB4ENCLRR register fields */ +#define RCC_MP_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MP_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MP_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MP_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MP_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MP_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MP_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MP_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MP_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MP_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MP_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MP_MLAHBENSETR register fields */ +#define RCC_MP_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MP_MLAHBENCLRR register fields */ +#define RCC_MP_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MC_APB1ENSETR register fields */ +#define RCC_MC_APB1ENSETR_TIM2EN BIT(0) +#define RCC_MC_APB1ENSETR_TIM3EN BIT(1) +#define RCC_MC_APB1ENSETR_TIM4EN BIT(2) +#define RCC_MC_APB1ENSETR_TIM5EN BIT(3) +#define RCC_MC_APB1ENSETR_TIM6EN BIT(4) +#define RCC_MC_APB1ENSETR_TIM7EN BIT(5) +#define RCC_MC_APB1ENSETR_TIM12EN BIT(6) +#define RCC_MC_APB1ENSETR_TIM13EN BIT(7) +#define RCC_MC_APB1ENSETR_TIM14EN BIT(8) +#define RCC_MC_APB1ENSETR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENSETR_SPI2EN BIT(11) +#define RCC_MC_APB1ENSETR_SPI3EN BIT(12) +#define RCC_MC_APB1ENSETR_USART2EN BIT(14) +#define RCC_MC_APB1ENSETR_USART3EN BIT(15) +#define RCC_MC_APB1ENSETR_UART4EN BIT(16) +#define RCC_MC_APB1ENSETR_UART5EN BIT(17) +#define RCC_MC_APB1ENSETR_UART7EN BIT(18) +#define RCC_MC_APB1ENSETR_UART8EN BIT(19) +#define RCC_MC_APB1ENSETR_I2C1EN BIT(21) +#define RCC_MC_APB1ENSETR_I2C2EN BIT(22) +#define RCC_MC_APB1ENSETR_I2C3EN BIT(23) +#define RCC_MC_APB1ENSETR_I2C5EN BIT(24) +#define RCC_MC_APB1ENSETR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENSETR_CECEN BIT(27) +#define RCC_MC_APB1ENSETR_WWDG1EN BIT(28) +#define RCC_MC_APB1ENSETR_DAC12EN BIT(29) +#define RCC_MC_APB1ENSETR_MDIOSEN BIT(31) + +/* RCC_MC_APB1ENCLRR register fields */ +#define RCC_MC_APB1ENCLRR_TIM2EN BIT(0) +#define RCC_MC_APB1ENCLRR_TIM3EN BIT(1) +#define RCC_MC_APB1ENCLRR_TIM4EN BIT(2) +#define RCC_MC_APB1ENCLRR_TIM5EN BIT(3) +#define RCC_MC_APB1ENCLRR_TIM6EN BIT(4) +#define RCC_MC_APB1ENCLRR_TIM7EN BIT(5) +#define RCC_MC_APB1ENCLRR_TIM12EN BIT(6) +#define RCC_MC_APB1ENCLRR_TIM13EN BIT(7) +#define RCC_MC_APB1ENCLRR_TIM14EN BIT(8) +#define RCC_MC_APB1ENCLRR_LPTIM1EN BIT(9) +#define RCC_MC_APB1ENCLRR_SPI2EN BIT(11) +#define RCC_MC_APB1ENCLRR_SPI3EN BIT(12) +#define RCC_MC_APB1ENCLRR_USART2EN BIT(14) +#define RCC_MC_APB1ENCLRR_USART3EN BIT(15) +#define RCC_MC_APB1ENCLRR_UART4EN BIT(16) +#define RCC_MC_APB1ENCLRR_UART5EN BIT(17) +#define RCC_MC_APB1ENCLRR_UART7EN BIT(18) +#define RCC_MC_APB1ENCLRR_UART8EN BIT(19) +#define RCC_MC_APB1ENCLRR_I2C1EN BIT(21) +#define RCC_MC_APB1ENCLRR_I2C2EN BIT(22) +#define RCC_MC_APB1ENCLRR_I2C3EN BIT(23) +#define RCC_MC_APB1ENCLRR_I2C5EN BIT(24) +#define RCC_MC_APB1ENCLRR_SPDIFEN BIT(26) +#define RCC_MC_APB1ENCLRR_CECEN BIT(27) +#define RCC_MC_APB1ENCLRR_DAC12EN BIT(29) +#define RCC_MC_APB1ENCLRR_MDIOSEN BIT(31) + +/* RCC_MC_APB2ENSETR register fields */ +#define RCC_MC_APB2ENSETR_TIM1EN BIT(0) +#define RCC_MC_APB2ENSETR_TIM8EN BIT(1) +#define RCC_MC_APB2ENSETR_TIM15EN BIT(2) +#define RCC_MC_APB2ENSETR_TIM16EN BIT(3) +#define RCC_MC_APB2ENSETR_TIM17EN BIT(4) +#define RCC_MC_APB2ENSETR_SPI1EN BIT(8) +#define RCC_MC_APB2ENSETR_SPI4EN BIT(9) +#define RCC_MC_APB2ENSETR_SPI5EN BIT(10) +#define RCC_MC_APB2ENSETR_USART6EN BIT(13) +#define RCC_MC_APB2ENSETR_SAI1EN BIT(16) +#define RCC_MC_APB2ENSETR_SAI2EN BIT(17) +#define RCC_MC_APB2ENSETR_SAI3EN BIT(18) +#define RCC_MC_APB2ENSETR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENSETR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENSETR_FDCANEN BIT(24) + +/* RCC_MC_APB2ENCLRR register fields */ +#define RCC_MC_APB2ENCLRR_TIM1EN BIT(0) +#define RCC_MC_APB2ENCLRR_TIM8EN BIT(1) +#define RCC_MC_APB2ENCLRR_TIM15EN BIT(2) +#define RCC_MC_APB2ENCLRR_TIM16EN BIT(3) +#define RCC_MC_APB2ENCLRR_TIM17EN BIT(4) +#define RCC_MC_APB2ENCLRR_SPI1EN BIT(8) +#define RCC_MC_APB2ENCLRR_SPI4EN BIT(9) +#define RCC_MC_APB2ENCLRR_SPI5EN BIT(10) +#define RCC_MC_APB2ENCLRR_USART6EN BIT(13) +#define RCC_MC_APB2ENCLRR_SAI1EN BIT(16) +#define RCC_MC_APB2ENCLRR_SAI2EN BIT(17) +#define RCC_MC_APB2ENCLRR_SAI3EN BIT(18) +#define RCC_MC_APB2ENCLRR_DFSDMEN BIT(20) +#define RCC_MC_APB2ENCLRR_ADFSDMEN BIT(21) +#define RCC_MC_APB2ENCLRR_FDCANEN BIT(24) + +/* RCC_MC_APB3ENSETR register fields */ +#define RCC_MC_APB3ENSETR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENSETR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENSETR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENSETR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENSETR_SAI4EN BIT(8) +#define RCC_MC_APB3ENSETR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENSETR_VREFEN BIT(13) +#define RCC_MC_APB3ENSETR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENSETR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENSETR_HDPEN BIT(20) + +/* RCC_MC_APB3ENCLRR register fields */ +#define RCC_MC_APB3ENCLRR_LPTIM2EN BIT(0) +#define RCC_MC_APB3ENCLRR_LPTIM3EN BIT(1) +#define RCC_MC_APB3ENCLRR_LPTIM4EN BIT(2) +#define RCC_MC_APB3ENCLRR_LPTIM5EN BIT(3) +#define RCC_MC_APB3ENCLRR_SAI4EN BIT(8) +#define RCC_MC_APB3ENCLRR_SYSCFGEN BIT(11) +#define RCC_MC_APB3ENCLRR_VREFEN BIT(13) +#define RCC_MC_APB3ENCLRR_TMPSENSEN BIT(16) +#define RCC_MC_APB3ENCLRR_PMBCTRLEN BIT(17) +#define RCC_MC_APB3ENCLRR_HDPEN BIT(20) + +/* RCC_MC_AHB2ENSETR register fields */ +#define RCC_MC_AHB2ENSETR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENSETR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENSETR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENSETR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENSETR_USBOEN BIT(8) +#define RCC_MC_AHB2ENSETR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB2ENCLRR register fields */ +#define RCC_MC_AHB2ENCLRR_DMA1EN BIT(0) +#define RCC_MC_AHB2ENCLRR_DMA2EN BIT(1) +#define RCC_MC_AHB2ENCLRR_DMAMUXEN BIT(2) +#define RCC_MC_AHB2ENCLRR_ADC12EN BIT(5) +#define RCC_MC_AHB2ENCLRR_USBOEN BIT(8) +#define RCC_MC_AHB2ENCLRR_SDMMC3EN BIT(16) + +/* RCC_MC_AHB3ENSETR register fields */ +#define RCC_MC_AHB3ENSETR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENSETR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENSETR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENSETR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENSETR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENSETR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENSETR_IPCCEN BIT(12) + +/* RCC_MC_AHB3ENCLRR register fields */ +#define RCC_MC_AHB3ENCLRR_DCMIEN BIT(0) +#define RCC_MC_AHB3ENCLRR_CRYP2EN BIT(4) +#define RCC_MC_AHB3ENCLRR_HASH2EN BIT(5) +#define RCC_MC_AHB3ENCLRR_RNG2EN BIT(6) +#define RCC_MC_AHB3ENCLRR_CRC2EN BIT(7) +#define RCC_MC_AHB3ENCLRR_HSEMEN BIT(11) +#define RCC_MC_AHB3ENCLRR_IPCCEN BIT(12) + +/* RCC_MC_AHB4ENSETR register fields */ +#define RCC_MC_AHB4ENSETR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENSETR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENSETR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENSETR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENSETR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENSETR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENSETR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENSETR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENSETR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENSETR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENSETR_GPIOKEN BIT(10) + +/* RCC_MC_AHB4ENCLRR register fields */ +#define RCC_MC_AHB4ENCLRR_GPIOAEN BIT(0) +#define RCC_MC_AHB4ENCLRR_GPIOBEN BIT(1) +#define RCC_MC_AHB4ENCLRR_GPIOCEN BIT(2) +#define RCC_MC_AHB4ENCLRR_GPIODEN BIT(3) +#define RCC_MC_AHB4ENCLRR_GPIOEEN BIT(4) +#define RCC_MC_AHB4ENCLRR_GPIOFEN BIT(5) +#define RCC_MC_AHB4ENCLRR_GPIOGEN BIT(6) +#define RCC_MC_AHB4ENCLRR_GPIOHEN BIT(7) +#define RCC_MC_AHB4ENCLRR_GPIOIEN BIT(8) +#define RCC_MC_AHB4ENCLRR_GPIOJEN BIT(9) +#define RCC_MC_AHB4ENCLRR_GPIOKEN BIT(10) + +/* RCC_MC_AXIMENSETR register fields */ +#define RCC_MC_AXIMENSETR_SYSRAMEN BIT(0) + +/* RCC_MC_AXIMENCLRR register fields */ +#define RCC_MC_AXIMENCLRR_SYSRAMEN BIT(0) + +/* RCC_MC_MLAHBENSETR register fields */ +#define RCC_MC_MLAHBENSETR_RETRAMEN BIT(4) + +/* RCC_MC_MLAHBENCLRR register fields */ +#define RCC_MC_MLAHBENCLRR_RETRAMEN BIT(4) + +/* RCC_MP_APB1LPENSETR register fields */ +#define RCC_MP_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB1LPENCLRR register fields */ +#define RCC_MP_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MP_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MP_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MP_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MP_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MP_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MP_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MP_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MP_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MP_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MP_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MP_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MP_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MP_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MP_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MP_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MP_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MP_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MP_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MP_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MP_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MP_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MP_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MP_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MP_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MP_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MP_APB2LPENSETR register fields */ +#define RCC_MP_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MP_APB2LPENCLRR register fields */ +#define RCC_MP_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MP_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MP_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MP_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MP_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MP_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MP_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MP_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MP_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MP_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MP_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MP_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MP_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MP_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MP_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MP_APB3LPENSETR register fields */ +#define RCC_MP_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_APB3LPENCLRR register fields */ +#define RCC_MP_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MP_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MP_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MP_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MP_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MP_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MP_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MP_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MP_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MP_AHB2LPENSETR register fields */ +#define RCC_MP_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB2LPENCLRR register fields */ +#define RCC_MP_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MP_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MP_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MP_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MP_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MP_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MP_AHB3LPENSETR register fields */ +#define RCC_MP_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB3LPENCLRR register fields */ +#define RCC_MP_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MP_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MP_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MP_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MP_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MP_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MP_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MP_AHB4LPENSETR register fields */ +#define RCC_MP_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MP_AHB4LPENCLRR register fields */ +#define RCC_MP_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MP_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MP_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MP_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MP_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MP_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MP_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MP_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MP_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MP_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MP_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MP_AXIMLPENSETR register fields */ +#define RCC_MP_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MP_AXIMLPENCLRR register fields */ +#define RCC_MP_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MP_MLAHBLPENSETR register fields */ +#define RCC_MP_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MP_MLAHBLPENCLRR register fields */ +#define RCC_MP_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MP_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MP_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MP_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_APB1LPENSETR register fields */ +#define RCC_MC_APB1LPENSETR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENSETR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENSETR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENSETR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENSETR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENSETR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENSETR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENSETR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENSETR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENSETR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENSETR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENSETR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENSETR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENSETR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENSETR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENSETR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENSETR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENSETR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENSETR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENSETR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENSETR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENSETR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENSETR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENSETR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENSETR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENSETR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENSETR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB1LPENCLRR register fields */ +#define RCC_MC_APB1LPENCLRR_TIM2LPEN BIT(0) +#define RCC_MC_APB1LPENCLRR_TIM3LPEN BIT(1) +#define RCC_MC_APB1LPENCLRR_TIM4LPEN BIT(2) +#define RCC_MC_APB1LPENCLRR_TIM5LPEN BIT(3) +#define RCC_MC_APB1LPENCLRR_TIM6LPEN BIT(4) +#define RCC_MC_APB1LPENCLRR_TIM7LPEN BIT(5) +#define RCC_MC_APB1LPENCLRR_TIM12LPEN BIT(6) +#define RCC_MC_APB1LPENCLRR_TIM13LPEN BIT(7) +#define RCC_MC_APB1LPENCLRR_TIM14LPEN BIT(8) +#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN BIT(9) +#define RCC_MC_APB1LPENCLRR_SPI2LPEN BIT(11) +#define RCC_MC_APB1LPENCLRR_SPI3LPEN BIT(12) +#define RCC_MC_APB1LPENCLRR_USART2LPEN BIT(14) +#define RCC_MC_APB1LPENCLRR_USART3LPEN BIT(15) +#define RCC_MC_APB1LPENCLRR_UART4LPEN BIT(16) +#define RCC_MC_APB1LPENCLRR_UART5LPEN BIT(17) +#define RCC_MC_APB1LPENCLRR_UART7LPEN BIT(18) +#define RCC_MC_APB1LPENCLRR_UART8LPEN BIT(19) +#define RCC_MC_APB1LPENCLRR_I2C1LPEN BIT(21) +#define RCC_MC_APB1LPENCLRR_I2C2LPEN BIT(22) +#define RCC_MC_APB1LPENCLRR_I2C3LPEN BIT(23) +#define RCC_MC_APB1LPENCLRR_I2C5LPEN BIT(24) +#define RCC_MC_APB1LPENCLRR_SPDIFLPEN BIT(26) +#define RCC_MC_APB1LPENCLRR_CECLPEN BIT(27) +#define RCC_MC_APB1LPENCLRR_WWDG1LPEN BIT(28) +#define RCC_MC_APB1LPENCLRR_DAC12LPEN BIT(29) +#define RCC_MC_APB1LPENCLRR_MDIOSLPEN BIT(31) + +/* RCC_MC_APB2LPENSETR register fields */ +#define RCC_MC_APB2LPENSETR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENSETR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENSETR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENSETR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENSETR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENSETR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENSETR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENSETR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENSETR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENSETR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENSETR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENSETR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENSETR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENSETR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENSETR_FDCANLPEN BIT(24) + +/* RCC_MC_APB2LPENCLRR register fields */ +#define RCC_MC_APB2LPENCLRR_TIM1LPEN BIT(0) +#define RCC_MC_APB2LPENCLRR_TIM8LPEN BIT(1) +#define RCC_MC_APB2LPENCLRR_TIM15LPEN BIT(2) +#define RCC_MC_APB2LPENCLRR_TIM16LPEN BIT(3) +#define RCC_MC_APB2LPENCLRR_TIM17LPEN BIT(4) +#define RCC_MC_APB2LPENCLRR_SPI1LPEN BIT(8) +#define RCC_MC_APB2LPENCLRR_SPI4LPEN BIT(9) +#define RCC_MC_APB2LPENCLRR_SPI5LPEN BIT(10) +#define RCC_MC_APB2LPENCLRR_USART6LPEN BIT(13) +#define RCC_MC_APB2LPENCLRR_SAI1LPEN BIT(16) +#define RCC_MC_APB2LPENCLRR_SAI2LPEN BIT(17) +#define RCC_MC_APB2LPENCLRR_SAI3LPEN BIT(18) +#define RCC_MC_APB2LPENCLRR_DFSDMLPEN BIT(20) +#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN BIT(21) +#define RCC_MC_APB2LPENCLRR_FDCANLPEN BIT(24) + +/* RCC_MC_APB3LPENSETR register fields */ +#define RCC_MC_APB3LPENSETR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENSETR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENSETR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENSETR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENSETR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENSETR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENSETR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENSETR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_APB3LPENCLRR register fields */ +#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN BIT(0) +#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN BIT(1) +#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN BIT(2) +#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN BIT(3) +#define RCC_MC_APB3LPENCLRR_SAI4LPEN BIT(8) +#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN BIT(11) +#define RCC_MC_APB3LPENCLRR_VREFLPEN BIT(13) +#define RCC_MC_APB3LPENCLRR_TMPSENSLPEN BIT(16) +#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN BIT(17) + +/* RCC_MC_AHB2LPENSETR register fields */ +#define RCC_MC_AHB2LPENSETR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENSETR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENSETR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENSETR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB2LPENCLRR register fields */ +#define RCC_MC_AHB2LPENCLRR_DMA1LPEN BIT(0) +#define RCC_MC_AHB2LPENCLRR_DMA2LPEN BIT(1) +#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN BIT(2) +#define RCC_MC_AHB2LPENCLRR_ADC12LPEN BIT(5) +#define RCC_MC_AHB2LPENCLRR_USBOLPEN BIT(8) +#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN BIT(16) + +/* RCC_MC_AHB3LPENSETR register fields */ +#define RCC_MC_AHB3LPENSETR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENSETR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENSETR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENSETR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENSETR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENSETR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENSETR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB3LPENCLRR register fields */ +#define RCC_MC_AHB3LPENCLRR_DCMILPEN BIT(0) +#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN BIT(4) +#define RCC_MC_AHB3LPENCLRR_HASH2LPEN BIT(5) +#define RCC_MC_AHB3LPENCLRR_RNG2LPEN BIT(6) +#define RCC_MC_AHB3LPENCLRR_CRC2LPEN BIT(7) +#define RCC_MC_AHB3LPENCLRR_HSEMLPEN BIT(11) +#define RCC_MC_AHB3LPENCLRR_IPCCLPEN BIT(12) + +/* RCC_MC_AHB4LPENSETR register fields */ +#define RCC_MC_AHB4LPENSETR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENSETR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENSETR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENSETR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENSETR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENSETR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENSETR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENSETR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENSETR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENSETR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENSETR_GPIOKLPEN BIT(10) + +/* RCC_MC_AHB4LPENCLRR register fields */ +#define RCC_MC_AHB4LPENCLRR_GPIOALPEN BIT(0) +#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN BIT(1) +#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN BIT(2) +#define RCC_MC_AHB4LPENCLRR_GPIODLPEN BIT(3) +#define RCC_MC_AHB4LPENCLRR_GPIOELPEN BIT(4) +#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN BIT(5) +#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN BIT(6) +#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN BIT(7) +#define RCC_MC_AHB4LPENCLRR_GPIOILPEN BIT(8) +#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN BIT(9) +#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN BIT(10) + +/* RCC_MC_AXIMLPENSETR register fields */ +#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN BIT(0) + +/* RCC_MC_AXIMLPENCLRR register fields */ +#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN BIT(0) + +/* RCC_MC_MLAHBLPENSETR register fields */ +#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENSETR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN BIT(4) + +/* RCC_MC_MLAHBLPENCLRR register fields */ +#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN BIT(0) +#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN BIT(1) +#define RCC_MC_MLAHBLPENCLRR_SRAM34LPEN BIT(2) +#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN BIT(4) + +/* RCC_MC_RSTSCLRR register fields */ +#define RCC_MC_RSTSCLRR_PORRSTF BIT(0) +#define RCC_MC_RSTSCLRR_BORRSTF BIT(1) +#define RCC_MC_RSTSCLRR_PADRSTF BIT(2) +#define RCC_MC_RSTSCLRR_HCSSRSTF BIT(3) +#define RCC_MC_RSTSCLRR_VCORERSTF BIT(4) +#define RCC_MC_RSTSCLRR_MCURSTF BIT(5) +#define RCC_MC_RSTSCLRR_MPSYSRSTF BIT(6) +#define RCC_MC_RSTSCLRR_MCSYSRSTF BIT(7) +#define RCC_MC_RSTSCLRR_IWDG1RSTF BIT(8) +#define RCC_MC_RSTSCLRR_IWDG2RSTF BIT(9) +#define RCC_MC_RSTSCLRR_WWDG1RSTF BIT(10) + +/* RCC_MC_CIER register fields */ +#define RCC_MC_CIER_LSIRDYIE BIT(0) +#define RCC_MC_CIER_LSERDYIE BIT(1) +#define RCC_MC_CIER_HSIRDYIE BIT(2) +#define RCC_MC_CIER_HSERDYIE BIT(3) +#define RCC_MC_CIER_CSIRDYIE BIT(4) +#define RCC_MC_CIER_PLL1DYIE BIT(8) +#define RCC_MC_CIER_PLL2DYIE BIT(9) +#define RCC_MC_CIER_PLL3DYIE BIT(10) +#define RCC_MC_CIER_PLL4DYIE BIT(11) +#define RCC_MC_CIER_LSECSSIE BIT(16) +#define RCC_MC_CIER_WKUPIE BIT(20) + +/* RCC_MC_CIFR register fields */ +#define RCC_MC_CIFR_LSIRDYF BIT(0) +#define RCC_MC_CIFR_LSERDYF BIT(1) +#define RCC_MC_CIFR_HSIRDYF BIT(2) +#define RCC_MC_CIFR_HSERDYF BIT(3) +#define RCC_MC_CIFR_CSIRDYF BIT(4) +#define RCC_MC_CIFR_PLL1DYF BIT(8) +#define RCC_MC_CIFR_PLL2DYF BIT(9) +#define RCC_MC_CIFR_PLL3DYF BIT(10) +#define RCC_MC_CIFR_PLL4DYF BIT(11) +#define RCC_MC_CIFR_LSECSSF BIT(16) +#define RCC_MC_CIFR_WKUPF BIT(20) + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_HSIKERON BIT(1) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_CSIKERON BIT(5) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEKERON BIT(9) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */ +#define RCC_RSTCLRR_OFFSET U(4) + +/* Used for most of DIVR register: max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + +/* Masks for specific DIVR registers */ +#define RCC_APBXDIV_MASK GENMASK(2, 0) +#define RCC_MPUDIV_MASK GENMASK(2, 0) +#define RCC_AXIDIV_MASK GENMASK(2, 0) +#define RCC_MCUDIV_MASK GENMASK(3, 0) + +/* Used for most of RCC_<x>SELR registers */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* Used for all RCC_PLL<n>CR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* Used for all RCC_PLL<n>CFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 + +/* Only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 + +/* Used for all RCC_PLL<n>CFGR2 registers */ +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT 0 +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVQ_SHIFT 8 +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) +#define RCC_PLLNCFGR2_DIVR_SHIFT 16 + +/* Used for all RCC_PLL<n>FRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* Used for all RCC_PLL<n>CSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* Used for TIMER Prescaler */ +#define RCC_TIMGXPRER_TIMGXPRE BIT(0) + +/* Used for RCC_MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +#endif /* STM32MP1_RCC_H */ diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h new file mode 100644 index 0000000..e2395bc --- /dev/null +++ b/include/drivers/st/stm32mp1_clk.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_CLK_H +#define STM32MP1_CLK_H + +#include <arch_helpers.h> + +enum stm32mp_osc_id { + _HSI, + _HSE, + _CSI, + _LSI, + _LSE, + _I2S_CKIN, + NB_OSC, + _UNKNOWN_OSC_ID = 0xFF +}; + +extern const char *stm32mp_osc_node_label[NB_OSC]; + +int stm32mp1_clk_probe(void); +int stm32mp1_clk_init(void); + +bool stm32mp1_rcc_is_secure(void); +bool stm32mp1_rcc_is_mckprot(void); + +/* SMP protection on RCC registers access */ +void stm32mp1_clk_rcc_regs_lock(void); +void stm32mp1_clk_rcc_regs_unlock(void); + +#ifdef STM32MP_SHARED_RESOURCES +void stm32mp1_register_clock_parents_secure(unsigned long id); +#endif +#endif /* STM32MP1_CLK_H */ diff --git a/include/drivers/st/stm32mp1_ddr.h b/include/drivers/st/stm32mp1_ddr.h new file mode 100644 index 0000000..df71f35 --- /dev/null +++ b/include/drivers/st/stm32mp1_ddr.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP1_DDR_H +#define STM32MP1_DDR_H + +#include <stdbool.h> +#include <stdint.h> + +#include <drivers/st/stm32mp_ddr.h> + +struct stm32mp1_ddrctrl_reg { + uint32_t mstr; + uint32_t mrctrl0; + uint32_t mrctrl1; + uint32_t derateen; + uint32_t derateint; + uint32_t pwrctl; + uint32_t pwrtmg; + uint32_t hwlpctl; + uint32_t rfshctl0; + uint32_t rfshctl3; + uint32_t crcparctl0; + uint32_t zqctl0; + uint32_t dfitmg0; + uint32_t dfitmg1; + uint32_t dfilpcfg0; + uint32_t dfiupd0; + uint32_t dfiupd1; + uint32_t dfiupd2; + uint32_t dfiphymstr; + uint32_t odtmap; + uint32_t dbg0; + uint32_t dbg1; + uint32_t dbgcmd; + uint32_t poisoncfg; + uint32_t pccfg; +}; + +struct stm32mp1_ddrctrl_timing { + uint32_t rfshtmg; + uint32_t dramtmg0; + uint32_t dramtmg1; + uint32_t dramtmg2; + uint32_t dramtmg3; + uint32_t dramtmg4; + uint32_t dramtmg5; + uint32_t dramtmg6; + uint32_t dramtmg7; + uint32_t dramtmg8; + uint32_t dramtmg14; + uint32_t odtcfg; +}; + +struct stm32mp1_ddrctrl_map { + uint32_t addrmap1; + uint32_t addrmap2; + uint32_t addrmap3; + uint32_t addrmap4; + uint32_t addrmap5; + uint32_t addrmap6; + uint32_t addrmap9; + uint32_t addrmap10; + uint32_t addrmap11; +}; + +struct stm32mp1_ddrctrl_perf { + uint32_t sched; + uint32_t sched1; + uint32_t perfhpr1; + uint32_t perflpr1; + uint32_t perfwr1; + uint32_t pcfgr_0; + uint32_t pcfgw_0; + uint32_t pcfgqos0_0; + uint32_t pcfgqos1_0; + uint32_t pcfgwqos0_0; + uint32_t pcfgwqos1_0; +#if STM32MP_DDR_DUAL_AXI_PORT + uint32_t pcfgr_1; + uint32_t pcfgw_1; + uint32_t pcfgqos0_1; + uint32_t pcfgqos1_1; + uint32_t pcfgwqos0_1; + uint32_t pcfgwqos1_1; +#endif +}; + +struct stm32mp1_ddrphy_reg { + uint32_t pgcr; + uint32_t aciocr; + uint32_t dxccr; + uint32_t dsgcr; + uint32_t dcr; + uint32_t odtcr; + uint32_t zq0cr1; + uint32_t dx0gcr; + uint32_t dx1gcr; +#if STM32MP_DDR_32BIT_INTERFACE + uint32_t dx2gcr; + uint32_t dx3gcr; +#endif +}; + +struct stm32mp1_ddrphy_timing { + uint32_t ptr0; + uint32_t ptr1; + uint32_t ptr2; + uint32_t dtpr0; + uint32_t dtpr1; + uint32_t dtpr2; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; +}; + +struct stm32mp_ddr_config { + struct stm32mp_ddr_info info; + struct stm32mp1_ddrctrl_reg c_reg; + struct stm32mp1_ddrctrl_timing c_timing; + struct stm32mp1_ddrctrl_map c_map; + struct stm32mp1_ddrctrl_perf c_perf; + struct stm32mp1_ddrphy_reg p_reg; + struct stm32mp1_ddrphy_timing p_timing; +}; + +int stm32mp1_ddr_clk_enable(struct stm32mp_ddr_priv *priv, uint32_t mem_speed); +void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, struct stm32mp_ddr_config *config); + +#endif /* STM32MP1_DDR_H */ diff --git a/include/drivers/st/stm32mp1_ddr_helpers.h b/include/drivers/st/stm32mp1_ddr_helpers.h new file mode 100644 index 0000000..38f2415 --- /dev/null +++ b/include/drivers/st/stm32mp1_ddr_helpers.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_DDR_HELPERS_H +#define STM32MP1_DDR_HELPERS_H + +void ddr_enable_clock(void); + +#endif /* STM32MP1_DDR_HELPERS_H */ diff --git a/include/drivers/st/stm32mp1_ddr_regs.h b/include/drivers/st/stm32mp1_ddr_regs.h new file mode 100644 index 0000000..2fbe1c8 --- /dev/null +++ b/include/drivers/st/stm32mp1_ddr_regs.h @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP1_DDR_REGS_H +#define STM32MP1_DDR_REGS_H + +#include <drivers/st/stm32mp_ddrctrl_regs.h> +#include <lib/utils_def.h> + +/* DDR Physical Interface Control (DDRPHYC) registers*/ +struct stm32mp_ddrphy { + uint32_t ridr; /* 0x00 R Revision Identification */ + uint32_t pir; /* 0x04 R/W PHY Initialization */ + uint32_t pgcr; /* 0x08 R/W PHY General Configuration */ + uint32_t pgsr; /* 0x0C PHY General Status */ + uint32_t dllgcr; /* 0x10 R/W DLL General Control */ + uint32_t acdllcr; /* 0x14 R/W AC DLL Control */ + uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */ + uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */ + uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */ + uint32_t aciocr; /* 0x24 AC I/O Configuration */ + uint32_t dxccr; /* 0x28 DATX8 Common Configuration */ + uint32_t dsgcr; /* 0x2C DDR System General Configuration */ + uint32_t dcr; /* 0x30 DRAM Configuration */ + uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */ + uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */ + uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */ + uint32_t mr0; /* 0x40 Mode 0 */ + uint32_t mr1; /* 0x44 Mode 1 */ + uint32_t mr2; /* 0x48 Mode 2 */ + uint32_t mr3; /* 0x4C Mode 3 */ + uint32_t odtcr; /* 0x50 ODT Configuration */ + uint32_t dtar; /* 0x54 data training address */ + uint32_t dtdr0; /* 0x58 */ + uint32_t dtdr1; /* 0x5c */ + uint8_t res1[0x0c0 - 0x060]; /* 0x60 */ + uint32_t dcuar; /* 0xc0 Address */ + uint32_t dcudr; /* 0xc4 DCU Data */ + uint32_t dcurr; /* 0xc8 DCU Run */ + uint32_t dculr; /* 0xcc DCU Loop */ + uint32_t dcugcr; /* 0xd0 DCU General Configuration */ + uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */ + uint32_t dcusr0; /* 0xd8 DCU Status 0 */ + uint32_t dcusr1; /* 0xdc DCU Status 1 */ + uint8_t res2[0x100 - 0xe0]; /* 0xe0 */ + uint32_t bistrr; /* 0x100 BIST Run */ + uint32_t bistmskr0; /* 0x104 BIST Mask 0 */ + uint32_t bistmskr1; /* 0x108 BIST Mask 0 */ + uint32_t bistwcr; /* 0x10c BIST Word Count */ + uint32_t bistlsr; /* 0x110 BIST LFSR Seed */ + uint32_t bistar0; /* 0x114 BIST Address 0 */ + uint32_t bistar1; /* 0x118 BIST Address 1 */ + uint32_t bistar2; /* 0x11c BIST Address 2 */ + uint32_t bistupdr; /* 0x120 BIST User Data Pattern */ + uint32_t bistgsr; /* 0x124 BIST General Status */ + uint32_t bistwer; /* 0x128 BIST Word Error */ + uint32_t bistber0; /* 0x12c BIST Bit Error 0 */ + uint32_t bistber1; /* 0x130 BIST Bit Error 1 */ + uint32_t bistber2; /* 0x134 BIST Bit Error 2 */ + uint32_t bistwcsr; /* 0x138 BIST Word Count Status */ + uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */ + uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */ + uint8_t res3[0x178 - 0x144]; /* 0x144 */ + uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */ + uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */ + uint32_t zq0cr0; /* 0x180 zq 0 control 0 */ + uint32_t zq0cr1; /* 0x184 zq 0 control 1 */ + uint32_t zq0sr0; /* 0x188 zq 0 status 0 */ + uint32_t zq0sr1; /* 0x18C zq 0 status 1 */ + uint8_t res4[0x1C0 - 0x190]; /* 0x190 */ + uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */ + uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */ + uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */ + uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */ + uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */ + uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */ + uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */ + uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */ + uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */ + uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */ + uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */ + uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */ + uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */ + uint8_t res6[0x240 - 0x218]; /* 0x218 */ +#if STM32MP_DDR_32BIT_INTERFACE + uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */ + uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */ + uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */ + uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */ + uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */ + uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */ + uint8_t res7[0x280 - 0x258]; /* 0x258 */ + uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */ + uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */ + uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */ + uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */ + uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */ + uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */ +#endif +} __packed; + +/* DDR PHY registers offsets */ +#define DDRPHYC_PIR 0x004 +#define DDRPHYC_PGCR 0x008 +#define DDRPHYC_PGSR 0x00C +#define DDRPHYC_DLLGCR 0x010 +#define DDRPHYC_ACDLLCR 0x014 +#define DDRPHYC_PTR0 0x018 +#define DDRPHYC_ACIOCR 0x024 +#define DDRPHYC_DXCCR 0x028 +#define DDRPHYC_DSGCR 0x02C +#define DDRPHYC_ZQ0CR0 0x180 +#define DDRPHYC_DX0GCR 0x1C0 +#define DDRPHYC_DX0DLLCR 0x1CC +#define DDRPHYC_DX1GCR 0x200 +#define DDRPHYC_DX1DLLCR 0x20C +#if STM32MP_DDR_32BIT_INTERFACE +#define DDRPHYC_DX2GCR 0x240 +#define DDRPHYC_DX2DLLCR 0x24C +#define DDRPHYC_DX3GCR 0x280 +#define DDRPHYC_DX3DLLCR 0x28C +#endif + +/* DDR PHY Register fields */ +#define DDRPHYC_PIR_INIT BIT(0) +#define DDRPHYC_PIR_DLLSRST BIT(1) +#define DDRPHYC_PIR_DLLLOCK BIT(2) +#define DDRPHYC_PIR_ZCAL BIT(3) +#define DDRPHYC_PIR_ITMSRST BIT(4) +#define DDRPHYC_PIR_DRAMRST BIT(5) +#define DDRPHYC_PIR_DRAMINIT BIT(6) +#define DDRPHYC_PIR_QSTRN BIT(7) +#define DDRPHYC_PIR_RVTRN BIT(8) +#define DDRPHYC_PIR_ICPC BIT(16) +#define DDRPHYC_PIR_ZCALBYP BIT(30) +#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) + +#define DDRPHYC_PGCR_DFTCMP BIT(2) +#define DDRPHYC_PGCR_PDDISDX BIT(24) +#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) + +#define DDRPHYC_PGSR_IDONE BIT(0) +#define DDRPHYC_PGSR_DTERR BIT(5) +#define DDRPHYC_PGSR_DTIERR BIT(6) +#define DDRPHYC_PGSR_DFTERR BIT(7) +#define DDRPHYC_PGSR_RVERR BIT(8) +#define DDRPHYC_PGSR_RVEIRR BIT(9) + +#define DDRPHYC_DLLGCR_BPS200 BIT(23) + +#define DDRPHYC_ACDLLCR_DLLSRST BIT(30) +#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) + +#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0 +#define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0) +#define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6 +#define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6) +#define DDRPHYC_PTR0_TITMSRST_OFFSET 18 +#define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18) + +#define DDRPHYC_ACIOCR_ACPDD BIT(3) +#define DDRPHYC_ACIOCR_ACPDR BIT(4) +#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8) +#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8) +#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11) +#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11) +#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18) +#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18) +#define DDRPHYC_ACIOCR_RSTPDD BIT(27) +#define DDRPHYC_ACIOCR_RSTPDR BIT(28) + +#define DDRPHYC_DXCCR_DXPDD BIT(2) +#define DDRPHYC_DXCCR_DXPDR BIT(3) + +#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16) +#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16) +#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20) +#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20) +#define DDRPHYC_DSGCR_NL2PD BIT(24) + +#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) +#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 +#define DDRPHYC_ZQ0CRN_ZDEN BIT(28) +#define DDRPHYC_ZQ0CRN_ZQPD BIT(31) + +#define DDRPHYC_DXNGCR_DXEN BIT(0) + +#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30) +#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) +#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) +#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 + +#endif /* STM32MP1_DDR_REGS_H */ diff --git a/include/drivers/st/stm32mp1_pwr.h b/include/drivers/st/stm32mp1_pwr.h new file mode 100644 index 0000000..e17df44 --- /dev/null +++ b/include/drivers/st/stm32mp1_pwr.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_PWR_H +#define STM32MP1_PWR_H + +#include <lib/utils_def.h> + +#define PWR_CR1 U(0x00) +#define PWR_CR2 U(0x08) +#define PWR_CR3 U(0x0C) +#define PWR_MPUCR U(0x10) +#define PWR_WKUPCR U(0x20) +#define PWR_MPUWKUPENR U(0x28) + +#define PWR_CR1_LPDS BIT(0) +#define PWR_CR1_LPCFG BIT(1) +#define PWR_CR1_LVDS BIT(2) +#define PWR_CR1_DBP BIT(8) + +#define PWR_CR3_DDRSREN BIT(10) +#define PWR_CR3_DDRSRDIS BIT(11) +#define PWR_CR3_DDRRETEN BIT(12) + +#define PWR_MPUCR_PDDS BIT(0) +#define PWR_MPUCR_CSTDBYDIS BIT(3) +#define PWR_MPUCR_CSSF BIT(9) + +#endif /* STM32MP1_PWR_H */ diff --git a/include/drivers/st/stm32mp1_ram.h b/include/drivers/st/stm32mp1_ram.h new file mode 100644 index 0000000..38360e7 --- /dev/null +++ b/include/drivers/st/stm32mp1_ram.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_RAM_H +#define STM32MP1_RAM_H + +int stm32mp1_ddr_probe(void); + +#endif /* STM32MP1_RAM_H */ diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h new file mode 100644 index 0000000..d794225 --- /dev/null +++ b/include/drivers/st/stm32mp1_rcc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#if STM32MP13 +#include "stm32mp13_rcc.h" +#endif +#if STM32MP15 +#include "stm32mp15_rcc.h" +#endif diff --git a/include/drivers/st/stm32mp1_usb.h b/include/drivers/st/stm32mp1_usb.h new file mode 100644 index 0000000..06a34cb --- /dev/null +++ b/include/drivers/st/stm32mp1_usb.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP1_USB_H +#define STM32MP1_USB_H + +#include <drivers/usb_device.h> + +void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle, + struct pcd_handle *pcd_handle, + void *base_register); + +#endif /* STM32MP1_USB_H */ diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h new file mode 100644 index 0000000..9dd25f3 --- /dev/null +++ b/include/drivers/st/stm32mp25_rcc.h @@ -0,0 +1,4986 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_RCC_H +#define STM32MP2_RCC_H + +#include <lib/utils_def.h> + +#define RCC_SECCFGR0 U(0x0) +#define RCC_SECCFGR1 U(0x4) +#define RCC_SECCFGR2 U(0x8) +#define RCC_SECCFGR3 U(0xC) +#define RCC_PRIVCFGR0 U(0x10) +#define RCC_PRIVCFGR1 U(0x14) +#define RCC_PRIVCFGR2 U(0x18) +#define RCC_PRIVCFGR3 U(0x1C) +#define RCC_RCFGLOCKR0 U(0x20) +#define RCC_RCFGLOCKR1 U(0x24) +#define RCC_RCFGLOCKR2 U(0x28) +#define RCC_RCFGLOCKR3 U(0x2C) +#define RCC_R0CIDCFGR U(0x30) +#define RCC_R0SEMCR U(0x34) +#define RCC_R1CIDCFGR U(0x38) +#define RCC_R1SEMCR U(0x3C) +#define RCC_R2CIDCFGR U(0x40) +#define RCC_R2SEMCR U(0x44) +#define RCC_R3CIDCFGR U(0x48) +#define RCC_R3SEMCR U(0x4C) +#define RCC_R4CIDCFGR U(0x50) +#define RCC_R4SEMCR U(0x54) +#define RCC_R5CIDCFGR U(0x58) +#define RCC_R5SEMCR U(0x5C) +#define RCC_R6CIDCFGR U(0x60) +#define RCC_R6SEMCR U(0x64) +#define RCC_R7CIDCFGR U(0x68) +#define RCC_R7SEMCR U(0x6C) +#define RCC_R8CIDCFGR U(0x70) +#define RCC_R8SEMCR U(0x74) +#define RCC_R9CIDCFGR U(0x78) +#define RCC_R9SEMCR U(0x7C) +#define RCC_R10CIDCFGR U(0x80) +#define RCC_R10SEMCR U(0x84) +#define RCC_R11CIDCFGR U(0x88) +#define RCC_R11SEMCR U(0x8C) +#define RCC_R12CIDCFGR U(0x90) +#define RCC_R12SEMCR U(0x94) +#define RCC_R13CIDCFGR U(0x98) +#define RCC_R13SEMCR U(0x9C) +#define RCC_R14CIDCFGR U(0xA0) +#define RCC_R14SEMCR U(0xA4) +#define RCC_R15CIDCFGR U(0xA8) +#define RCC_R15SEMCR U(0xAC) +#define RCC_R16CIDCFGR U(0xB0) +#define RCC_R16SEMCR U(0xB4) +#define RCC_R17CIDCFGR U(0xB8) +#define RCC_R17SEMCR U(0xBC) +#define RCC_R18CIDCFGR U(0xC0) +#define RCC_R18SEMCR U(0xC4) +#define RCC_R19CIDCFGR U(0xC8) +#define RCC_R19SEMCR U(0xCC) +#define RCC_R20CIDCFGR U(0xD0) +#define RCC_R20SEMCR U(0xD4) +#define RCC_R21CIDCFGR U(0xD8) +#define RCC_R21SEMCR U(0xDC) +#define RCC_R22CIDCFGR U(0xE0) +#define RCC_R22SEMCR U(0xE4) +#define RCC_R23CIDCFGR U(0xE8) +#define RCC_R23SEMCR U(0xEC) +#define RCC_R24CIDCFGR U(0xF0) +#define RCC_R24SEMCR U(0xF4) +#define RCC_R25CIDCFGR U(0xF8) +#define RCC_R25SEMCR U(0xFC) +#define RCC_R26CIDCFGR U(0x100) +#define RCC_R26SEMCR U(0x104) +#define RCC_R27CIDCFGR U(0x108) +#define RCC_R27SEMCR U(0x10C) +#define RCC_R28CIDCFGR U(0x110) +#define RCC_R28SEMCR U(0x114) +#define RCC_R29CIDCFGR U(0x118) +#define RCC_R29SEMCR U(0x11C) +#define RCC_R30CIDCFGR U(0x120) +#define RCC_R30SEMCR U(0x124) +#define RCC_R31CIDCFGR U(0x128) +#define RCC_R31SEMCR U(0x12C) +#define RCC_R32CIDCFGR U(0x130) +#define RCC_R32SEMCR U(0x134) +#define RCC_R33CIDCFGR U(0x138) +#define RCC_R33SEMCR U(0x13C) +#define RCC_R34CIDCFGR U(0x140) +#define RCC_R34SEMCR U(0x144) +#define RCC_R35CIDCFGR U(0x148) +#define RCC_R35SEMCR U(0x14C) +#define RCC_R36CIDCFGR U(0x150) +#define RCC_R36SEMCR U(0x154) +#define RCC_R37CIDCFGR U(0x158) +#define RCC_R37SEMCR U(0x15C) +#define RCC_R38CIDCFGR U(0x160) +#define RCC_R38SEMCR U(0x164) +#define RCC_R39CIDCFGR U(0x168) +#define RCC_R39SEMCR U(0x16C) +#define RCC_R40CIDCFGR U(0x170) +#define RCC_R40SEMCR U(0x174) +#define RCC_R41CIDCFGR U(0x178) +#define RCC_R41SEMCR U(0x17C) +#define RCC_R42CIDCFGR U(0x180) +#define RCC_R42SEMCR U(0x184) +#define RCC_R43CIDCFGR U(0x188) +#define RCC_R43SEMCR U(0x18C) +#define RCC_R44CIDCFGR U(0x190) +#define RCC_R44SEMCR U(0x194) +#define RCC_R45CIDCFGR U(0x198) +#define RCC_R45SEMCR U(0x19C) +#define RCC_R46CIDCFGR U(0x1A0) +#define RCC_R46SEMCR U(0x1A4) +#define RCC_R47CIDCFGR U(0x1A8) +#define RCC_R47SEMCR U(0x1AC) +#define RCC_R48CIDCFGR U(0x1B0) +#define RCC_R48SEMCR U(0x1B4) +#define RCC_R49CIDCFGR U(0x1B8) +#define RCC_R49SEMCR U(0x1BC) +#define RCC_R50CIDCFGR U(0x1C0) +#define RCC_R50SEMCR U(0x1C4) +#define RCC_R51CIDCFGR U(0x1C8) +#define RCC_R51SEMCR U(0x1CC) +#define RCC_R52CIDCFGR U(0x1D0) +#define RCC_R52SEMCR U(0x1D4) +#define RCC_R53CIDCFGR U(0x1D8) +#define RCC_R53SEMCR U(0x1DC) +#define RCC_R54CIDCFGR U(0x1E0) +#define RCC_R54SEMCR U(0x1E4) +#define RCC_R55CIDCFGR U(0x1E8) +#define RCC_R55SEMCR U(0x1EC) +#define RCC_R56CIDCFGR U(0x1F0) +#define RCC_R56SEMCR U(0x1F4) +#define RCC_R57CIDCFGR U(0x1F8) +#define RCC_R57SEMCR U(0x1FC) +#define RCC_R58CIDCFGR U(0x200) +#define RCC_R58SEMCR U(0x204) +#define RCC_R59CIDCFGR U(0x208) +#define RCC_R59SEMCR U(0x20C) +#define RCC_R60CIDCFGR U(0x210) +#define RCC_R60SEMCR U(0x214) +#define RCC_R61CIDCFGR U(0x218) +#define RCC_R61SEMCR U(0x21C) +#define RCC_R62CIDCFGR U(0x220) +#define RCC_R62SEMCR U(0x224) +#define RCC_R63CIDCFGR U(0x228) +#define RCC_R63SEMCR U(0x22C) +#define RCC_R64CIDCFGR U(0x230) +#define RCC_R64SEMCR U(0x234) +#define RCC_R65CIDCFGR U(0x238) +#define RCC_R65SEMCR U(0x23C) +#define RCC_R66CIDCFGR U(0x240) +#define RCC_R66SEMCR U(0x244) +#define RCC_R67CIDCFGR U(0x248) +#define RCC_R67SEMCR U(0x24C) +#define RCC_R68CIDCFGR U(0x250) +#define RCC_R68SEMCR U(0x254) +#define RCC_R69CIDCFGR U(0x258) +#define RCC_R69SEMCR U(0x25C) +#define RCC_R70CIDCFGR U(0x260) +#define RCC_R70SEMCR U(0x264) +#define RCC_R71CIDCFGR U(0x268) +#define RCC_R71SEMCR U(0x26C) +#define RCC_R72CIDCFGR U(0x270) +#define RCC_R72SEMCR U(0x274) +#define RCC_R73CIDCFGR U(0x278) +#define RCC_R73SEMCR U(0x27C) +#define RCC_R74CIDCFGR U(0x280) +#define RCC_R74SEMCR U(0x284) +#define RCC_R75CIDCFGR U(0x288) +#define RCC_R75SEMCR U(0x28C) +#define RCC_R76CIDCFGR U(0x290) +#define RCC_R76SEMCR U(0x294) +#define RCC_R77CIDCFGR U(0x298) +#define RCC_R77SEMCR U(0x29C) +#define RCC_R78CIDCFGR U(0x2A0) +#define RCC_R78SEMCR U(0x2A4) +#define RCC_R79CIDCFGR U(0x2A8) +#define RCC_R79SEMCR U(0x2AC) +#define RCC_R80CIDCFGR U(0x2B0) +#define RCC_R80SEMCR U(0x2B4) +#define RCC_R81CIDCFGR U(0x2B8) +#define RCC_R81SEMCR U(0x2BC) +#define RCC_R82CIDCFGR U(0x2C0) +#define RCC_R82SEMCR U(0x2C4) +#define RCC_R83CIDCFGR U(0x2C8) +#define RCC_R83SEMCR U(0x2CC) +#define RCC_R84CIDCFGR U(0x2D0) +#define RCC_R84SEMCR U(0x2D4) +#define RCC_R85CIDCFGR U(0x2D8) +#define RCC_R85SEMCR U(0x2DC) +#define RCC_R86CIDCFGR U(0x2E0) +#define RCC_R86SEMCR U(0x2E4) +#define RCC_R87CIDCFGR U(0x2E8) +#define RCC_R87SEMCR U(0x2EC) +#define RCC_R88CIDCFGR U(0x2F0) +#define RCC_R88SEMCR U(0x2F4) +#define RCC_R89CIDCFGR U(0x2F8) +#define RCC_R89SEMCR U(0x2FC) +#define RCC_R90CIDCFGR U(0x300) +#define RCC_R90SEMCR U(0x304) +#define RCC_R91CIDCFGR U(0x308) +#define RCC_R91SEMCR U(0x30C) +#define RCC_R92CIDCFGR U(0x310) +#define RCC_R92SEMCR U(0x314) +#define RCC_R93CIDCFGR U(0x318) +#define RCC_R93SEMCR U(0x31C) +#define RCC_R94CIDCFGR U(0x320) +#define RCC_R94SEMCR U(0x324) +#define RCC_R95CIDCFGR U(0x328) +#define RCC_R95SEMCR U(0x32C) +#define RCC_R96CIDCFGR U(0x330) +#define RCC_R96SEMCR U(0x334) +#define RCC_R97CIDCFGR U(0x338) +#define RCC_R97SEMCR U(0x33C) +#define RCC_R98CIDCFGR U(0x340) +#define RCC_R98SEMCR U(0x344) +#define RCC_R99CIDCFGR U(0x348) +#define RCC_R99SEMCR U(0x34C) +#define RCC_R100CIDCFGR U(0x350) +#define RCC_R100SEMCR U(0x354) +#define RCC_R101CIDCFGR U(0x358) +#define RCC_R101SEMCR U(0x35C) +#define RCC_R102CIDCFGR U(0x360) +#define RCC_R102SEMCR U(0x364) +#define RCC_R103CIDCFGR U(0x368) +#define RCC_R103SEMCR U(0x36C) +#define RCC_R104CIDCFGR U(0x370) +#define RCC_R104SEMCR U(0x374) +#define RCC_R105CIDCFGR U(0x378) +#define RCC_R105SEMCR U(0x37C) +#define RCC_R106CIDCFGR U(0x380) +#define RCC_R106SEMCR U(0x384) +#define RCC_R107CIDCFGR U(0x388) +#define RCC_R107SEMCR U(0x38C) +#define RCC_R108CIDCFGR U(0x390) +#define RCC_R108SEMCR U(0x394) +#define RCC_R109CIDCFGR U(0x398) +#define RCC_R109SEMCR U(0x39C) +#define RCC_R110CIDCFGR U(0x3A0) +#define RCC_R110SEMCR U(0x3A4) +#define RCC_R111CIDCFGR U(0x3A8) +#define RCC_R111SEMCR U(0x3AC) +#define RCC_R112CIDCFGR U(0x3B0) +#define RCC_R112SEMCR U(0x3B4) +#define RCC_R113CIDCFGR U(0x3B8) +#define RCC_R113SEMCR U(0x3BC) +#define RCC_GRSTCSETR U(0x400) +#define RCC_C1RSTCSETR U(0x404) +#define RCC_C1P1RSTCSETR U(0x408) +#define RCC_C2RSTCSETR U(0x40C) +#define RCC_HWRSTSCLRR U(0x410) +#define RCC_C1HWRSTSCLRR U(0x414) +#define RCC_C2HWRSTSCLRR U(0x418) +#define RCC_C1BOOTRSTSSETR U(0x41C) +#define RCC_C1BOOTRSTSCLRR U(0x420) +#define RCC_C2BOOTRSTSSETR U(0x424) +#define RCC_C2BOOTRSTSCLRR U(0x428) +#define RCC_C1SREQSETR U(0x42C) +#define RCC_C1SREQCLRR U(0x430) +#define RCC_CPUBOOTCR U(0x434) +#define RCC_STBYBOOTCR U(0x438) +#define RCC_LEGBOOTCR U(0x43C) +#define RCC_BDCR U(0x440) +#define RCC_D3DCR U(0x444) +#define RCC_D3DSR U(0x448) +#define RCC_RDCR U(0x44C) +#define RCC_C1MSRDCR U(0x450) +#define RCC_PWRLPDLYCR U(0x454) +#define RCC_C1CIESETR U(0x458) +#define RCC_C1CIFCLRR U(0x45C) +#define RCC_C2CIESETR U(0x460) +#define RCC_C2CIFCLRR U(0x464) +#define RCC_IWDGC1FZSETR U(0x468) +#define RCC_IWDGC1FZCLRR U(0x46C) +#define RCC_IWDGC1CFGSETR U(0x470) +#define RCC_IWDGC1CFGCLRR U(0x474) +#define RCC_IWDGC2FZSETR U(0x478) +#define RCC_IWDGC2FZCLRR U(0x47C) +#define RCC_IWDGC2CFGSETR U(0x480) +#define RCC_IWDGC2CFGCLRR U(0x484) +#define RCC_IWDGC3CFGSETR U(0x488) +#define RCC_IWDGC3CFGCLRR U(0x48C) +#define RCC_C3CFGR U(0x490) +#define RCC_MCO1CFGR U(0x494) +#define RCC_MCO2CFGR U(0x498) +#define RCC_OCENSETR U(0x49C) +#define RCC_OCENCLRR U(0x4A0) +#define RCC_OCRDYR U(0x4A4) +#define RCC_HSICFGR U(0x4A8) +#define RCC_CSICFGR U(0x4AC) +#define RCC_RTCDIVR U(0x4B0) +#define RCC_APB1DIVR U(0x4B4) +#define RCC_APB2DIVR U(0x4B8) +#define RCC_APB3DIVR U(0x4BC) +#define RCC_APB4DIVR U(0x4C0) +#define RCC_APBDBGDIVR U(0x4C4) +#define RCC_TIMG1PRER U(0x4C8) +#define RCC_TIMG2PRER U(0x4CC) +#define RCC_LSMCUDIVR U(0x4D0) +#define RCC_DDRCPCFGR U(0x4D4) +#define RCC_DDRCAPBCFGR U(0x4D8) +#define RCC_DDRPHYCAPBCFGR U(0x4DC) +#define RCC_DDRPHYCCFGR U(0x4E0) +#define RCC_DDRCFGR U(0x4E4) +#define RCC_DDRITFCFGR U(0x4E8) +#define RCC_SYSRAMCFGR U(0x4F0) +#define RCC_VDERAMCFGR U(0x4F4) +#define RCC_SRAM1CFGR U(0x4F8) +#define RCC_SRAM2CFGR U(0x4FC) +#define RCC_RETRAMCFGR U(0x500) +#define RCC_BKPSRAMCFGR U(0x504) +#define RCC_LPSRAM1CFGR U(0x508) +#define RCC_LPSRAM2CFGR U(0x50C) +#define RCC_LPSRAM3CFGR U(0x510) +#define RCC_OSPI1CFGR U(0x514) +#define RCC_OSPI2CFGR U(0x518) +#define RCC_FMCCFGR U(0x51C) +#define RCC_DBGCFGR U(0x520) +#define RCC_STM500CFGR U(0x524) +#define RCC_ETRCFGR U(0x528) +#define RCC_GPIOACFGR U(0x52C) +#define RCC_GPIOBCFGR U(0x530) +#define RCC_GPIOCCFGR U(0x534) +#define RCC_GPIODCFGR U(0x538) +#define RCC_GPIOECFGR U(0x53C) +#define RCC_GPIOFCFGR U(0x540) +#define RCC_GPIOGCFGR U(0x544) +#define RCC_GPIOHCFGR U(0x548) +#define RCC_GPIOICFGR U(0x54C) +#define RCC_GPIOJCFGR U(0x550) +#define RCC_GPIOKCFGR U(0x554) +#define RCC_GPIOZCFGR U(0x558) +#define RCC_HPDMA1CFGR U(0x55C) +#define RCC_HPDMA2CFGR U(0x560) +#define RCC_HPDMA3CFGR U(0x564) +#define RCC_LPDMACFGR U(0x568) +#define RCC_HSEMCFGR U(0x56C) +#define RCC_IPCC1CFGR U(0x570) +#define RCC_IPCC2CFGR U(0x574) +#define RCC_RTCCFGR U(0x578) +#define RCC_SYSCPU1CFGR U(0x580) +#define RCC_BSECCFGR U(0x584) +#define RCC_IS2MCFGR U(0x58C) +#define RCC_PLL2CFGR1 U(0x590) +#define RCC_PLL2CFGR2 U(0x594) +#define RCC_PLL2CFGR3 U(0x598) +#define RCC_PLL2CFGR4 U(0x59C) +#define RCC_PLL2CFGR5 U(0x5A0) +#define RCC_PLL2CFGR6 U(0x5A8) +#define RCC_PLL2CFGR7 U(0x5AC) +#define RCC_PLL3CFGR1 U(0x5B8) +#define RCC_PLL3CFGR2 U(0x5BC) +#define RCC_PLL3CFGR3 U(0x5C0) +#define RCC_PLL3CFGR4 U(0x5C4) +#define RCC_PLL3CFGR5 U(0x5C8) +#define RCC_PLL3CFGR6 U(0x5D0) +#define RCC_PLL3CFGR7 U(0x5D4) +#define RCC_HSIFMONCR U(0x5E0) +#define RCC_HSIFVALR U(0x5E4) +#define RCC_TIM1CFGR U(0x700) +#define RCC_TIM2CFGR U(0x704) +#define RCC_TIM3CFGR U(0x708) +#define RCC_TIM4CFGR U(0x70C) +#define RCC_TIM5CFGR U(0x710) +#define RCC_TIM6CFGR U(0x714) +#define RCC_TIM7CFGR U(0x718) +#define RCC_TIM8CFGR U(0x71C) +#define RCC_TIM10CFGR U(0x720) +#define RCC_TIM11CFGR U(0x724) +#define RCC_TIM12CFGR U(0x728) +#define RCC_TIM13CFGR U(0x72C) +#define RCC_TIM14CFGR U(0x730) +#define RCC_TIM15CFGR U(0x734) +#define RCC_TIM16CFGR U(0x738) +#define RCC_TIM17CFGR U(0x73C) +#define RCC_TIM20CFGR U(0x740) +#define RCC_LPTIM1CFGR U(0x744) +#define RCC_LPTIM2CFGR U(0x748) +#define RCC_LPTIM3CFGR U(0x74C) +#define RCC_LPTIM4CFGR U(0x750) +#define RCC_LPTIM5CFGR U(0x754) +#define RCC_SPI1CFGR U(0x758) +#define RCC_SPI2CFGR U(0x75C) +#define RCC_SPI3CFGR U(0x760) +#define RCC_SPI4CFGR U(0x764) +#define RCC_SPI5CFGR U(0x768) +#define RCC_SPI6CFGR U(0x76C) +#define RCC_SPI7CFGR U(0x770) +#define RCC_SPI8CFGR U(0x774) +#define RCC_SPDIFRXCFGR U(0x778) +#define RCC_USART1CFGR U(0x77C) +#define RCC_USART2CFGR U(0x780) +#define RCC_USART3CFGR U(0x784) +#define RCC_UART4CFGR U(0x788) +#define RCC_UART5CFGR U(0x78C) +#define RCC_USART6CFGR U(0x790) +#define RCC_UART7CFGR U(0x794) +#define RCC_UART8CFGR U(0x798) +#define RCC_UART9CFGR U(0x79C) +#define RCC_LPUART1CFGR U(0x7A0) +#define RCC_I2C1CFGR U(0x7A4) +#define RCC_I2C2CFGR U(0x7A8) +#define RCC_I2C3CFGR U(0x7AC) +#define RCC_I2C4CFGR U(0x7B0) +#define RCC_I2C5CFGR U(0x7B4) +#define RCC_I2C6CFGR U(0x7B8) +#define RCC_I2C7CFGR U(0x7BC) +#define RCC_I2C8CFGR U(0x7C0) +#define RCC_SAI1CFGR U(0x7C4) +#define RCC_SAI2CFGR U(0x7C8) +#define RCC_SAI3CFGR U(0x7CC) +#define RCC_SAI4CFGR U(0x7D0) +#define RCC_MDF1CFGR U(0x7D8) +#define RCC_ADF1CFGR U(0x7DC) +#define RCC_FDCANCFGR U(0x7E0) +#define RCC_HDPCFGR U(0x7E4) +#define RCC_ADC12CFGR U(0x7E8) +#define RCC_ADC3CFGR U(0x7EC) +#define RCC_ETH1CFGR U(0x7F0) +#define RCC_ETH2CFGR U(0x7F4) +#define RCC_USB2CFGR U(0x7FC) +#define RCC_USB2PHY1CFGR U(0x800) +#define RCC_USB2PHY2CFGR U(0x804) +#define RCC_USB3DRDCFGR U(0x808) +#define RCC_USB3PCIEPHYCFGR U(0x80C) +#define RCC_PCIECFGR U(0x810) +#define RCC_USBTCCFGR U(0x814) +#define RCC_ETHSWCFGR U(0x818) +#define RCC_ETHSWACMCFGR U(0x81C) +#define RCC_ETHSWACMMSGCFGR U(0x820) +#define RCC_STGENCFGR U(0x824) +#define RCC_SDMMC1CFGR U(0x830) +#define RCC_SDMMC2CFGR U(0x834) +#define RCC_SDMMC3CFGR U(0x838) +#define RCC_GPUCFGR U(0x83C) +#define RCC_LTDCCFGR U(0x840) +#define RCC_DSICFGR U(0x844) +#define RCC_LVDSCFGR U(0x850) +#define RCC_CSI2CFGR U(0x858) +#define RCC_DCMIPPCFGR U(0x85C) +#define RCC_CCICFGR U(0x860) +#define RCC_VDECCFGR U(0x864) +#define RCC_VENCCFGR U(0x868) +#define RCC_RNGCFGR U(0x870) +#define RCC_PKACFGR U(0x874) +#define RCC_SAESCFGR U(0x878) +#define RCC_HASHCFGR U(0x87C) +#define RCC_CRYP1CFGR U(0x880) +#define RCC_CRYP2CFGR U(0x884) +#define RCC_IWDG1CFGR U(0x888) +#define RCC_IWDG2CFGR U(0x88C) +#define RCC_IWDG3CFGR U(0x890) +#define RCC_IWDG4CFGR U(0x894) +#define RCC_IWDG5CFGR U(0x898) +#define RCC_WWDG1CFGR U(0x89C) +#define RCC_WWDG2CFGR U(0x8A0) +#define RCC_BUSPERFMCFGR U(0x8A4) +#define RCC_VREFCFGR U(0x8A8) +#define RCC_TMPSENSCFGR U(0x8AC) +#define RCC_CRCCFGR U(0x8B4) +#define RCC_SERCCFGR U(0x8B8) +#define RCC_OSPIIOMCFGR U(0x8BC) +#define RCC_GICV2MCFGR U(0x8C0) +#define RCC_I3C1CFGR U(0x8C8) +#define RCC_I3C2CFGR U(0x8CC) +#define RCC_I3C3CFGR U(0x8D0) +#define RCC_I3C4CFGR U(0x8D4) +#define RCC_MUXSELCFGR U(0x1000) +#define RCC_XBAR0CFGR U(0x1018) +#define RCC_XBAR1CFGR U(0x101C) +#define RCC_XBAR2CFGR U(0x1020) +#define RCC_XBAR3CFGR U(0x1024) +#define RCC_XBAR4CFGR U(0x1028) +#define RCC_XBAR5CFGR U(0x102C) +#define RCC_XBAR6CFGR U(0x1030) +#define RCC_XBAR7CFGR U(0x1034) +#define RCC_XBAR8CFGR U(0x1038) +#define RCC_XBAR9CFGR U(0x103C) +#define RCC_XBAR10CFGR U(0x1040) +#define RCC_XBAR11CFGR U(0x1044) +#define RCC_XBAR12CFGR U(0x1048) +#define RCC_XBAR13CFGR U(0x104C) +#define RCC_XBAR14CFGR U(0x1050) +#define RCC_XBAR15CFGR U(0x1054) +#define RCC_XBAR16CFGR U(0x1058) +#define RCC_XBAR17CFGR U(0x105C) +#define RCC_XBAR18CFGR U(0x1060) +#define RCC_XBAR19CFGR U(0x1064) +#define RCC_XBAR20CFGR U(0x1068) +#define RCC_XBAR21CFGR U(0x106C) +#define RCC_XBAR22CFGR U(0x1070) +#define RCC_XBAR23CFGR U(0x1074) +#define RCC_XBAR24CFGR U(0x1078) +#define RCC_XBAR25CFGR U(0x107C) +#define RCC_XBAR26CFGR U(0x1080) +#define RCC_XBAR27CFGR U(0x1084) +#define RCC_XBAR28CFGR U(0x1088) +#define RCC_XBAR29CFGR U(0x108C) +#define RCC_XBAR30CFGR U(0x1090) +#define RCC_XBAR31CFGR U(0x1094) +#define RCC_XBAR32CFGR U(0x1098) +#define RCC_XBAR33CFGR U(0x109C) +#define RCC_XBAR34CFGR U(0x10A0) +#define RCC_XBAR35CFGR U(0x10A4) +#define RCC_XBAR36CFGR U(0x10A8) +#define RCC_XBAR37CFGR U(0x10AC) +#define RCC_XBAR38CFGR U(0x10B0) +#define RCC_XBAR39CFGR U(0x10B4) +#define RCC_XBAR40CFGR U(0x10B8) +#define RCC_XBAR41CFGR U(0x10BC) +#define RCC_XBAR42CFGR U(0x10C0) +#define RCC_XBAR43CFGR U(0x10C4) +#define RCC_XBAR44CFGR U(0x10C8) +#define RCC_XBAR45CFGR U(0x10CC) +#define RCC_XBAR46CFGR U(0x10D0) +#define RCC_XBAR47CFGR U(0x10D4) +#define RCC_XBAR48CFGR U(0x10D8) +#define RCC_XBAR49CFGR U(0x10DC) +#define RCC_XBAR50CFGR U(0x10E0) +#define RCC_XBAR51CFGR U(0x10E4) +#define RCC_XBAR52CFGR U(0x10E8) +#define RCC_XBAR53CFGR U(0x10EC) +#define RCC_XBAR54CFGR U(0x10F0) +#define RCC_XBAR55CFGR U(0x10F4) +#define RCC_XBAR56CFGR U(0x10F8) +#define RCC_XBAR57CFGR U(0x10FC) +#define RCC_XBAR58CFGR U(0x1100) +#define RCC_XBAR59CFGR U(0x1104) +#define RCC_XBAR60CFGR U(0x1108) +#define RCC_XBAR61CFGR U(0x110C) +#define RCC_XBAR62CFGR U(0x1110) +#define RCC_XBAR63CFGR U(0x1114) +#define RCC_PREDIV0CFGR U(0x1118) +#define RCC_PREDIV1CFGR U(0x111C) +#define RCC_PREDIV2CFGR U(0x1120) +#define RCC_PREDIV3CFGR U(0x1124) +#define RCC_PREDIV4CFGR U(0x1128) +#define RCC_PREDIV5CFGR U(0x112C) +#define RCC_PREDIV6CFGR U(0x1130) +#define RCC_PREDIV7CFGR U(0x1134) +#define RCC_PREDIV8CFGR U(0x1138) +#define RCC_PREDIV9CFGR U(0x113C) +#define RCC_PREDIV10CFGR U(0x1140) +#define RCC_PREDIV11CFGR U(0x1144) +#define RCC_PREDIV12CFGR U(0x1148) +#define RCC_PREDIV13CFGR U(0x114C) +#define RCC_PREDIV14CFGR U(0x1150) +#define RCC_PREDIV15CFGR U(0x1154) +#define RCC_PREDIV16CFGR U(0x1158) +#define RCC_PREDIV17CFGR U(0x115C) +#define RCC_PREDIV18CFGR U(0x1160) +#define RCC_PREDIV19CFGR U(0x1164) +#define RCC_PREDIV20CFGR U(0x1168) +#define RCC_PREDIV21CFGR U(0x116C) +#define RCC_PREDIV22CFGR U(0x1170) +#define RCC_PREDIV23CFGR U(0x1174) +#define RCC_PREDIV24CFGR U(0x1178) +#define RCC_PREDIV25CFGR U(0x117C) +#define RCC_PREDIV26CFGR U(0x1180) +#define RCC_PREDIV27CFGR U(0x1184) +#define RCC_PREDIV28CFGR U(0x1188) +#define RCC_PREDIV29CFGR U(0x118C) +#define RCC_PREDIV30CFGR U(0x1190) +#define RCC_PREDIV31CFGR U(0x1194) +#define RCC_PREDIV32CFGR U(0x1198) +#define RCC_PREDIV33CFGR U(0x119C) +#define RCC_PREDIV34CFGR U(0x11A0) +#define RCC_PREDIV35CFGR U(0x11A4) +#define RCC_PREDIV36CFGR U(0x11A8) +#define RCC_PREDIV37CFGR U(0x11AC) +#define RCC_PREDIV38CFGR U(0x11B0) +#define RCC_PREDIV39CFGR U(0x11B4) +#define RCC_PREDIV40CFGR U(0x11B8) +#define RCC_PREDIV41CFGR U(0x11BC) +#define RCC_PREDIV42CFGR U(0x11C0) +#define RCC_PREDIV43CFGR U(0x11C4) +#define RCC_PREDIV44CFGR U(0x11C8) +#define RCC_PREDIV45CFGR U(0x11CC) +#define RCC_PREDIV46CFGR U(0x11D0) +#define RCC_PREDIV47CFGR U(0x11D4) +#define RCC_PREDIV48CFGR U(0x11D8) +#define RCC_PREDIV49CFGR U(0x11DC) +#define RCC_PREDIV50CFGR U(0x11E0) +#define RCC_PREDIV51CFGR U(0x11E4) +#define RCC_PREDIV52CFGR U(0x11E8) +#define RCC_PREDIV53CFGR U(0x11EC) +#define RCC_PREDIV54CFGR U(0x11F0) +#define RCC_PREDIV55CFGR U(0x11F4) +#define RCC_PREDIV56CFGR U(0x11F8) +#define RCC_PREDIV57CFGR U(0x11FC) +#define RCC_PREDIV58CFGR U(0x1200) +#define RCC_PREDIV59CFGR U(0x1204) +#define RCC_PREDIV60CFGR U(0x1208) +#define RCC_PREDIV61CFGR U(0x120C) +#define RCC_PREDIV62CFGR U(0x1210) +#define RCC_PREDIV63CFGR U(0x1214) +#define RCC_PREDIVSR1 U(0x1218) +#define RCC_PREDIVSR2 U(0x121C) +#define RCC_FINDIV0CFGR U(0x1224) +#define RCC_FINDIV1CFGR U(0x1228) +#define RCC_FINDIV2CFGR U(0x122C) +#define RCC_FINDIV3CFGR U(0x1230) +#define RCC_FINDIV4CFGR U(0x1234) +#define RCC_FINDIV5CFGR U(0x1238) +#define RCC_FINDIV6CFGR U(0x123C) +#define RCC_FINDIV7CFGR U(0x1240) +#define RCC_FINDIV8CFGR U(0x1244) +#define RCC_FINDIV9CFGR U(0x1248) +#define RCC_FINDIV10CFGR U(0x124C) +#define RCC_FINDIV11CFGR U(0x1250) +#define RCC_FINDIV12CFGR U(0x1254) +#define RCC_FINDIV13CFGR U(0x1258) +#define RCC_FINDIV14CFGR U(0x125C) +#define RCC_FINDIV15CFGR U(0x1260) +#define RCC_FINDIV16CFGR U(0x1264) +#define RCC_FINDIV17CFGR U(0x1268) +#define RCC_FINDIV18CFGR U(0x126C) +#define RCC_FINDIV19CFGR U(0x1270) +#define RCC_FINDIV20CFGR U(0x1274) +#define RCC_FINDIV21CFGR U(0x1278) +#define RCC_FINDIV22CFGR U(0x127C) +#define RCC_FINDIV23CFGR U(0x1280) +#define RCC_FINDIV24CFGR U(0x1284) +#define RCC_FINDIV25CFGR U(0x1288) +#define RCC_FINDIV26CFGR U(0x128C) +#define RCC_FINDIV27CFGR U(0x1290) +#define RCC_FINDIV28CFGR U(0x1294) +#define RCC_FINDIV29CFGR U(0x1298) +#define RCC_FINDIV30CFGR U(0x129C) +#define RCC_FINDIV31CFGR U(0x12A0) +#define RCC_FINDIV32CFGR U(0x12A4) +#define RCC_FINDIV33CFGR U(0x12A8) +#define RCC_FINDIV34CFGR U(0x12AC) +#define RCC_FINDIV35CFGR U(0x12B0) +#define RCC_FINDIV36CFGR U(0x12B4) +#define RCC_FINDIV37CFGR U(0x12B8) +#define RCC_FINDIV38CFGR U(0x12BC) +#define RCC_FINDIV39CFGR U(0x12C0) +#define RCC_FINDIV40CFGR U(0x12C4) +#define RCC_FINDIV41CFGR U(0x12C8) +#define RCC_FINDIV42CFGR U(0x12CC) +#define RCC_FINDIV43CFGR U(0x12D0) +#define RCC_FINDIV44CFGR U(0x12D4) +#define RCC_FINDIV45CFGR U(0x12D8) +#define RCC_FINDIV46CFGR U(0x12DC) +#define RCC_FINDIV47CFGR U(0x12E0) +#define RCC_FINDIV48CFGR U(0x12E4) +#define RCC_FINDIV49CFGR U(0x12E8) +#define RCC_FINDIV50CFGR U(0x12EC) +#define RCC_FINDIV51CFGR U(0x12F0) +#define RCC_FINDIV52CFGR U(0x12F4) +#define RCC_FINDIV53CFGR U(0x12F8) +#define RCC_FINDIV54CFGR U(0x12FC) +#define RCC_FINDIV55CFGR U(0x1300) +#define RCC_FINDIV56CFGR U(0x1304) +#define RCC_FINDIV57CFGR U(0x1308) +#define RCC_FINDIV58CFGR U(0x130C) +#define RCC_FINDIV59CFGR U(0x1310) +#define RCC_FINDIV60CFGR U(0x1314) +#define RCC_FINDIV61CFGR U(0x1318) +#define RCC_FINDIV62CFGR U(0x131C) +#define RCC_FINDIV63CFGR U(0x1320) +#define RCC_FINDIVSR1 U(0x1324) +#define RCC_FINDIVSR2 U(0x1328) +#define RCC_FCALCOBS0CFGR U(0x1340) +#define RCC_FCALCOBS1CFGR U(0x1344) +#define RCC_FCALCREFCFGR U(0x1348) +#define RCC_FCALCCR1 U(0x134C) +#define RCC_FCALCCR2 U(0x1354) +#define RCC_FCALCSR U(0x1358) +#define RCC_PLL4CFGR1 U(0x1360) +#define RCC_PLL4CFGR2 U(0x1364) +#define RCC_PLL4CFGR3 U(0x1368) +#define RCC_PLL4CFGR4 U(0x136C) +#define RCC_PLL4CFGR5 U(0x1370) +#define RCC_PLL4CFGR6 U(0x1378) +#define RCC_PLL4CFGR7 U(0x137C) +#define RCC_PLL5CFGR1 U(0x1388) +#define RCC_PLL5CFGR2 U(0x138C) +#define RCC_PLL5CFGR3 U(0x1390) +#define RCC_PLL5CFGR4 U(0x1394) +#define RCC_PLL5CFGR5 U(0x1398) +#define RCC_PLL5CFGR6 U(0x13A0) +#define RCC_PLL5CFGR7 U(0x13A4) +#define RCC_PLL6CFGR1 U(0x13B0) +#define RCC_PLL6CFGR2 U(0x13B4) +#define RCC_PLL6CFGR3 U(0x13B8) +#define RCC_PLL6CFGR4 U(0x13BC) +#define RCC_PLL6CFGR5 U(0x13C0) +#define RCC_PLL6CFGR6 U(0x13C8) +#define RCC_PLL6CFGR7 U(0x13CC) +#define RCC_PLL7CFGR1 U(0x13D8) +#define RCC_PLL7CFGR2 U(0x13DC) +#define RCC_PLL7CFGR3 U(0x13E0) +#define RCC_PLL7CFGR4 U(0x13E4) +#define RCC_PLL7CFGR5 U(0x13E8) +#define RCC_PLL7CFGR6 U(0x13F0) +#define RCC_PLL7CFGR7 U(0x13F4) +#define RCC_PLL8CFGR1 U(0x1400) +#define RCC_PLL8CFGR2 U(0x1404) +#define RCC_PLL8CFGR3 U(0x1408) +#define RCC_PLL8CFGR4 U(0x140C) +#define RCC_PLL8CFGR5 U(0x1410) +#define RCC_PLL8CFGR6 U(0x1418) +#define RCC_PLL8CFGR7 U(0x141C) +#define RCC_VERR U(0xFFF4) +#define RCC_IDR U(0xFFF8) +#define RCC_SIDR U(0xFFFC) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* RCC_SECCFGR3 register fields */ +#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0) +#define RCC_SECCFGR3_SEC_SHIFT 0 + +/* RCC_PRIVCFGR3 register fields */ +#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0) +#define RCC_PRIVCFGR3_PRIV_SHIFT 0 + +/* RCC_RCFGLOCKR3 register fields */ +#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0) +#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0 + +/* RCC_R0CIDCFGR register fields */ +#define RCC_R0CIDCFGR_CFEN BIT(0) +#define RCC_R0CIDCFGR_SEM_EN BIT(1) +#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R0CIDCFGR_SCID_SHIFT 4 +#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R0SEMCR register fields */ +#define RCC_R0SEMCR_SEM_MUTEX BIT(0) +#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R0SEMCR_SEMCID_SHIFT 4 + +/* RCC_R1CIDCFGR register fields */ +#define RCC_R1CIDCFGR_CFEN BIT(0) +#define RCC_R1CIDCFGR_SEM_EN BIT(1) +#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R1CIDCFGR_SCID_SHIFT 4 +#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R1SEMCR register fields */ +#define RCC_R1SEMCR_SEM_MUTEX BIT(0) +#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R1SEMCR_SEMCID_SHIFT 4 + +/* RCC_R2CIDCFGR register fields */ +#define RCC_R2CIDCFGR_CFEN BIT(0) +#define RCC_R2CIDCFGR_SEM_EN BIT(1) +#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R2CIDCFGR_SCID_SHIFT 4 +#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R2SEMCR register fields */ +#define RCC_R2SEMCR_SEM_MUTEX BIT(0) +#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R2SEMCR_SEMCID_SHIFT 4 + +/* RCC_R3CIDCFGR register fields */ +#define RCC_R3CIDCFGR_CFEN BIT(0) +#define RCC_R3CIDCFGR_SEM_EN BIT(1) +#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R3CIDCFGR_SCID_SHIFT 4 +#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R3SEMCR register fields */ +#define RCC_R3SEMCR_SEM_MUTEX BIT(0) +#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R3SEMCR_SEMCID_SHIFT 4 + +/* RCC_R4CIDCFGR register fields */ +#define RCC_R4CIDCFGR_CFEN BIT(0) +#define RCC_R4CIDCFGR_SEM_EN BIT(1) +#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R4CIDCFGR_SCID_SHIFT 4 +#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R4SEMCR register fields */ +#define RCC_R4SEMCR_SEM_MUTEX BIT(0) +#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R4SEMCR_SEMCID_SHIFT 4 + +/* RCC_R5CIDCFGR register fields */ +#define RCC_R5CIDCFGR_CFEN BIT(0) +#define RCC_R5CIDCFGR_SEM_EN BIT(1) +#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R5CIDCFGR_SCID_SHIFT 4 +#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R5SEMCR register fields */ +#define RCC_R5SEMCR_SEM_MUTEX BIT(0) +#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R5SEMCR_SEMCID_SHIFT 4 + +/* RCC_R6CIDCFGR register fields */ +#define RCC_R6CIDCFGR_CFEN BIT(0) +#define RCC_R6CIDCFGR_SEM_EN BIT(1) +#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R6CIDCFGR_SCID_SHIFT 4 +#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R6SEMCR register fields */ +#define RCC_R6SEMCR_SEM_MUTEX BIT(0) +#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R6SEMCR_SEMCID_SHIFT 4 + +/* RCC_R7CIDCFGR register fields */ +#define RCC_R7CIDCFGR_CFEN BIT(0) +#define RCC_R7CIDCFGR_SEM_EN BIT(1) +#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R7CIDCFGR_SCID_SHIFT 4 +#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R7SEMCR register fields */ +#define RCC_R7SEMCR_SEM_MUTEX BIT(0) +#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R7SEMCR_SEMCID_SHIFT 4 + +/* RCC_R8CIDCFGR register fields */ +#define RCC_R8CIDCFGR_CFEN BIT(0) +#define RCC_R8CIDCFGR_SEM_EN BIT(1) +#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R8CIDCFGR_SCID_SHIFT 4 +#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R8SEMCR register fields */ +#define RCC_R8SEMCR_SEM_MUTEX BIT(0) +#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R8SEMCR_SEMCID_SHIFT 4 + +/* RCC_R9CIDCFGR register fields */ +#define RCC_R9CIDCFGR_CFEN BIT(0) +#define RCC_R9CIDCFGR_SEM_EN BIT(1) +#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R9CIDCFGR_SCID_SHIFT 4 +#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R9SEMCR register fields */ +#define RCC_R9SEMCR_SEM_MUTEX BIT(0) +#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R9SEMCR_SEMCID_SHIFT 4 + +/* RCC_R10CIDCFGR register fields */ +#define RCC_R10CIDCFGR_CFEN BIT(0) +#define RCC_R10CIDCFGR_SEM_EN BIT(1) +#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R10CIDCFGR_SCID_SHIFT 4 +#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R10SEMCR register fields */ +#define RCC_R10SEMCR_SEM_MUTEX BIT(0) +#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R10SEMCR_SEMCID_SHIFT 4 + +/* RCC_R11CIDCFGR register fields */ +#define RCC_R11CIDCFGR_CFEN BIT(0) +#define RCC_R11CIDCFGR_SEM_EN BIT(1) +#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R11CIDCFGR_SCID_SHIFT 4 +#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R11SEMCR register fields */ +#define RCC_R11SEMCR_SEM_MUTEX BIT(0) +#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R11SEMCR_SEMCID_SHIFT 4 + +/* RCC_R12CIDCFGR register fields */ +#define RCC_R12CIDCFGR_CFEN BIT(0) +#define RCC_R12CIDCFGR_SEM_EN BIT(1) +#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R12CIDCFGR_SCID_SHIFT 4 +#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R12SEMCR register fields */ +#define RCC_R12SEMCR_SEM_MUTEX BIT(0) +#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R12SEMCR_SEMCID_SHIFT 4 + +/* RCC_R13CIDCFGR register fields */ +#define RCC_R13CIDCFGR_CFEN BIT(0) +#define RCC_R13CIDCFGR_SEM_EN BIT(1) +#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R13CIDCFGR_SCID_SHIFT 4 +#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R13SEMCR register fields */ +#define RCC_R13SEMCR_SEM_MUTEX BIT(0) +#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R13SEMCR_SEMCID_SHIFT 4 + +/* RCC_R14CIDCFGR register fields */ +#define RCC_R14CIDCFGR_CFEN BIT(0) +#define RCC_R14CIDCFGR_SEM_EN BIT(1) +#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R14CIDCFGR_SCID_SHIFT 4 +#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R14SEMCR register fields */ +#define RCC_R14SEMCR_SEM_MUTEX BIT(0) +#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R14SEMCR_SEMCID_SHIFT 4 + +/* RCC_R15CIDCFGR register fields */ +#define RCC_R15CIDCFGR_CFEN BIT(0) +#define RCC_R15CIDCFGR_SEM_EN BIT(1) +#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R15CIDCFGR_SCID_SHIFT 4 +#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R15SEMCR register fields */ +#define RCC_R15SEMCR_SEM_MUTEX BIT(0) +#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R15SEMCR_SEMCID_SHIFT 4 + +/* RCC_R16CIDCFGR register fields */ +#define RCC_R16CIDCFGR_CFEN BIT(0) +#define RCC_R16CIDCFGR_SEM_EN BIT(1) +#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R16CIDCFGR_SCID_SHIFT 4 +#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R16SEMCR register fields */ +#define RCC_R16SEMCR_SEM_MUTEX BIT(0) +#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R16SEMCR_SEMCID_SHIFT 4 + +/* RCC_R17CIDCFGR register fields */ +#define RCC_R17CIDCFGR_CFEN BIT(0) +#define RCC_R17CIDCFGR_SEM_EN BIT(1) +#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R17CIDCFGR_SCID_SHIFT 4 +#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R17SEMCR register fields */ +#define RCC_R17SEMCR_SEM_MUTEX BIT(0) +#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R17SEMCR_SEMCID_SHIFT 4 + +/* RCC_R18CIDCFGR register fields */ +#define RCC_R18CIDCFGR_CFEN BIT(0) +#define RCC_R18CIDCFGR_SEM_EN BIT(1) +#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R18CIDCFGR_SCID_SHIFT 4 +#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R18SEMCR register fields */ +#define RCC_R18SEMCR_SEM_MUTEX BIT(0) +#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R18SEMCR_SEMCID_SHIFT 4 + +/* RCC_R19CIDCFGR register fields */ +#define RCC_R19CIDCFGR_CFEN BIT(0) +#define RCC_R19CIDCFGR_SEM_EN BIT(1) +#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R19CIDCFGR_SCID_SHIFT 4 +#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R19SEMCR register fields */ +#define RCC_R19SEMCR_SEM_MUTEX BIT(0) +#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R19SEMCR_SEMCID_SHIFT 4 + +/* RCC_R20CIDCFGR register fields */ +#define RCC_R20CIDCFGR_CFEN BIT(0) +#define RCC_R20CIDCFGR_SEM_EN BIT(1) +#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R20CIDCFGR_SCID_SHIFT 4 +#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R20SEMCR register fields */ +#define RCC_R20SEMCR_SEM_MUTEX BIT(0) +#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R20SEMCR_SEMCID_SHIFT 4 + +/* RCC_R21CIDCFGR register fields */ +#define RCC_R21CIDCFGR_CFEN BIT(0) +#define RCC_R21CIDCFGR_SEM_EN BIT(1) +#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R21CIDCFGR_SCID_SHIFT 4 +#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R21SEMCR register fields */ +#define RCC_R21SEMCR_SEM_MUTEX BIT(0) +#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R21SEMCR_SEMCID_SHIFT 4 + +/* RCC_R22CIDCFGR register fields */ +#define RCC_R22CIDCFGR_CFEN BIT(0) +#define RCC_R22CIDCFGR_SEM_EN BIT(1) +#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R22CIDCFGR_SCID_SHIFT 4 +#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R22SEMCR register fields */ +#define RCC_R22SEMCR_SEM_MUTEX BIT(0) +#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R22SEMCR_SEMCID_SHIFT 4 + +/* RCC_R23CIDCFGR register fields */ +#define RCC_R23CIDCFGR_CFEN BIT(0) +#define RCC_R23CIDCFGR_SEM_EN BIT(1) +#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R23CIDCFGR_SCID_SHIFT 4 +#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R23SEMCR register fields */ +#define RCC_R23SEMCR_SEM_MUTEX BIT(0) +#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R23SEMCR_SEMCID_SHIFT 4 + +/* RCC_R24CIDCFGR register fields */ +#define RCC_R24CIDCFGR_CFEN BIT(0) +#define RCC_R24CIDCFGR_SEM_EN BIT(1) +#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R24CIDCFGR_SCID_SHIFT 4 +#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R24SEMCR register fields */ +#define RCC_R24SEMCR_SEM_MUTEX BIT(0) +#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R24SEMCR_SEMCID_SHIFT 4 + +/* RCC_R25CIDCFGR register fields */ +#define RCC_R25CIDCFGR_CFEN BIT(0) +#define RCC_R25CIDCFGR_SEM_EN BIT(1) +#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R25CIDCFGR_SCID_SHIFT 4 +#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R25SEMCR register fields */ +#define RCC_R25SEMCR_SEM_MUTEX BIT(0) +#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R25SEMCR_SEMCID_SHIFT 4 + +/* RCC_R26CIDCFGR register fields */ +#define RCC_R26CIDCFGR_CFEN BIT(0) +#define RCC_R26CIDCFGR_SEM_EN BIT(1) +#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R26CIDCFGR_SCID_SHIFT 4 +#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R26SEMCR register fields */ +#define RCC_R26SEMCR_SEM_MUTEX BIT(0) +#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R26SEMCR_SEMCID_SHIFT 4 + +/* RCC_R27CIDCFGR register fields */ +#define RCC_R27CIDCFGR_CFEN BIT(0) +#define RCC_R27CIDCFGR_SEM_EN BIT(1) +#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R27CIDCFGR_SCID_SHIFT 4 +#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R27SEMCR register fields */ +#define RCC_R27SEMCR_SEM_MUTEX BIT(0) +#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R27SEMCR_SEMCID_SHIFT 4 + +/* RCC_R28CIDCFGR register fields */ +#define RCC_R28CIDCFGR_CFEN BIT(0) +#define RCC_R28CIDCFGR_SEM_EN BIT(1) +#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R28CIDCFGR_SCID_SHIFT 4 +#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R28SEMCR register fields */ +#define RCC_R28SEMCR_SEM_MUTEX BIT(0) +#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R28SEMCR_SEMCID_SHIFT 4 + +/* RCC_R29CIDCFGR register fields */ +#define RCC_R29CIDCFGR_CFEN BIT(0) +#define RCC_R29CIDCFGR_SEM_EN BIT(1) +#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R29CIDCFGR_SCID_SHIFT 4 +#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R29SEMCR register fields */ +#define RCC_R29SEMCR_SEM_MUTEX BIT(0) +#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R29SEMCR_SEMCID_SHIFT 4 + +/* RCC_R30CIDCFGR register fields */ +#define RCC_R30CIDCFGR_CFEN BIT(0) +#define RCC_R30CIDCFGR_SEM_EN BIT(1) +#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R30CIDCFGR_SCID_SHIFT 4 +#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R30SEMCR register fields */ +#define RCC_R30SEMCR_SEM_MUTEX BIT(0) +#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R30SEMCR_SEMCID_SHIFT 4 + +/* RCC_R31CIDCFGR register fields */ +#define RCC_R31CIDCFGR_CFEN BIT(0) +#define RCC_R31CIDCFGR_SEM_EN BIT(1) +#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R31CIDCFGR_SCID_SHIFT 4 +#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R31SEMCR register fields */ +#define RCC_R31SEMCR_SEM_MUTEX BIT(0) +#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R31SEMCR_SEMCID_SHIFT 4 + +/* RCC_R32CIDCFGR register fields */ +#define RCC_R32CIDCFGR_CFEN BIT(0) +#define RCC_R32CIDCFGR_SEM_EN BIT(1) +#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R32CIDCFGR_SCID_SHIFT 4 +#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R32SEMCR register fields */ +#define RCC_R32SEMCR_SEM_MUTEX BIT(0) +#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R32SEMCR_SEMCID_SHIFT 4 + +/* RCC_R33CIDCFGR register fields */ +#define RCC_R33CIDCFGR_CFEN BIT(0) +#define RCC_R33CIDCFGR_SEM_EN BIT(1) +#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R33CIDCFGR_SCID_SHIFT 4 +#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R33SEMCR register fields */ +#define RCC_R33SEMCR_SEM_MUTEX BIT(0) +#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R33SEMCR_SEMCID_SHIFT 4 + +/* RCC_R34CIDCFGR register fields */ +#define RCC_R34CIDCFGR_CFEN BIT(0) +#define RCC_R34CIDCFGR_SEM_EN BIT(1) +#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R34CIDCFGR_SCID_SHIFT 4 +#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R34SEMCR register fields */ +#define RCC_R34SEMCR_SEM_MUTEX BIT(0) +#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R34SEMCR_SEMCID_SHIFT 4 + +/* RCC_R35CIDCFGR register fields */ +#define RCC_R35CIDCFGR_CFEN BIT(0) +#define RCC_R35CIDCFGR_SEM_EN BIT(1) +#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R35CIDCFGR_SCID_SHIFT 4 +#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R35SEMCR register fields */ +#define RCC_R35SEMCR_SEM_MUTEX BIT(0) +#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R35SEMCR_SEMCID_SHIFT 4 + +/* RCC_R36CIDCFGR register fields */ +#define RCC_R36CIDCFGR_CFEN BIT(0) +#define RCC_R36CIDCFGR_SEM_EN BIT(1) +#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R36CIDCFGR_SCID_SHIFT 4 +#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R36SEMCR register fields */ +#define RCC_R36SEMCR_SEM_MUTEX BIT(0) +#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R36SEMCR_SEMCID_SHIFT 4 + +/* RCC_R37CIDCFGR register fields */ +#define RCC_R37CIDCFGR_CFEN BIT(0) +#define RCC_R37CIDCFGR_SEM_EN BIT(1) +#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R37CIDCFGR_SCID_SHIFT 4 +#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R37SEMCR register fields */ +#define RCC_R37SEMCR_SEM_MUTEX BIT(0) +#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R37SEMCR_SEMCID_SHIFT 4 + +/* RCC_R38CIDCFGR register fields */ +#define RCC_R38CIDCFGR_CFEN BIT(0) +#define RCC_R38CIDCFGR_SEM_EN BIT(1) +#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R38CIDCFGR_SCID_SHIFT 4 +#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R38SEMCR register fields */ +#define RCC_R38SEMCR_SEM_MUTEX BIT(0) +#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R38SEMCR_SEMCID_SHIFT 4 + +/* RCC_R39CIDCFGR register fields */ +#define RCC_R39CIDCFGR_CFEN BIT(0) +#define RCC_R39CIDCFGR_SEM_EN BIT(1) +#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R39CIDCFGR_SCID_SHIFT 4 +#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R39SEMCR register fields */ +#define RCC_R39SEMCR_SEM_MUTEX BIT(0) +#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R39SEMCR_SEMCID_SHIFT 4 + +/* RCC_R40CIDCFGR register fields */ +#define RCC_R40CIDCFGR_CFEN BIT(0) +#define RCC_R40CIDCFGR_SEM_EN BIT(1) +#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R40CIDCFGR_SCID_SHIFT 4 +#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R40SEMCR register fields */ +#define RCC_R40SEMCR_SEM_MUTEX BIT(0) +#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R40SEMCR_SEMCID_SHIFT 4 + +/* RCC_R41CIDCFGR register fields */ +#define RCC_R41CIDCFGR_CFEN BIT(0) +#define RCC_R41CIDCFGR_SEM_EN BIT(1) +#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R41CIDCFGR_SCID_SHIFT 4 +#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R41SEMCR register fields */ +#define RCC_R41SEMCR_SEM_MUTEX BIT(0) +#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R41SEMCR_SEMCID_SHIFT 4 + +/* RCC_R42CIDCFGR register fields */ +#define RCC_R42CIDCFGR_CFEN BIT(0) +#define RCC_R42CIDCFGR_SEM_EN BIT(1) +#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R42CIDCFGR_SCID_SHIFT 4 +#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R42SEMCR register fields */ +#define RCC_R42SEMCR_SEM_MUTEX BIT(0) +#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R42SEMCR_SEMCID_SHIFT 4 + +/* RCC_R43CIDCFGR register fields */ +#define RCC_R43CIDCFGR_CFEN BIT(0) +#define RCC_R43CIDCFGR_SEM_EN BIT(1) +#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R43CIDCFGR_SCID_SHIFT 4 +#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R43SEMCR register fields */ +#define RCC_R43SEMCR_SEM_MUTEX BIT(0) +#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R43SEMCR_SEMCID_SHIFT 4 + +/* RCC_R44CIDCFGR register fields */ +#define RCC_R44CIDCFGR_CFEN BIT(0) +#define RCC_R44CIDCFGR_SEM_EN BIT(1) +#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R44CIDCFGR_SCID_SHIFT 4 +#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R44SEMCR register fields */ +#define RCC_R44SEMCR_SEM_MUTEX BIT(0) +#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R44SEMCR_SEMCID_SHIFT 4 + +/* RCC_R45CIDCFGR register fields */ +#define RCC_R45CIDCFGR_CFEN BIT(0) +#define RCC_R45CIDCFGR_SEM_EN BIT(1) +#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R45CIDCFGR_SCID_SHIFT 4 +#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R45SEMCR register fields */ +#define RCC_R45SEMCR_SEM_MUTEX BIT(0) +#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R45SEMCR_SEMCID_SHIFT 4 + +/* RCC_R46CIDCFGR register fields */ +#define RCC_R46CIDCFGR_CFEN BIT(0) +#define RCC_R46CIDCFGR_SEM_EN BIT(1) +#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R46CIDCFGR_SCID_SHIFT 4 +#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R46SEMCR register fields */ +#define RCC_R46SEMCR_SEM_MUTEX BIT(0) +#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R46SEMCR_SEMCID_SHIFT 4 + +/* RCC_R47CIDCFGR register fields */ +#define RCC_R47CIDCFGR_CFEN BIT(0) +#define RCC_R47CIDCFGR_SEM_EN BIT(1) +#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R47CIDCFGR_SCID_SHIFT 4 +#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R47SEMCR register fields */ +#define RCC_R47SEMCR_SEM_MUTEX BIT(0) +#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R47SEMCR_SEMCID_SHIFT 4 + +/* RCC_R48CIDCFGR register fields */ +#define RCC_R48CIDCFGR_CFEN BIT(0) +#define RCC_R48CIDCFGR_SEM_EN BIT(1) +#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R48CIDCFGR_SCID_SHIFT 4 +#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R48SEMCR register fields */ +#define RCC_R48SEMCR_SEM_MUTEX BIT(0) +#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R48SEMCR_SEMCID_SHIFT 4 + +/* RCC_R49CIDCFGR register fields */ +#define RCC_R49CIDCFGR_CFEN BIT(0) +#define RCC_R49CIDCFGR_SEM_EN BIT(1) +#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R49CIDCFGR_SCID_SHIFT 4 +#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R49SEMCR register fields */ +#define RCC_R49SEMCR_SEM_MUTEX BIT(0) +#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R49SEMCR_SEMCID_SHIFT 4 + +/* RCC_R50CIDCFGR register fields */ +#define RCC_R50CIDCFGR_CFEN BIT(0) +#define RCC_R50CIDCFGR_SEM_EN BIT(1) +#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R50CIDCFGR_SCID_SHIFT 4 +#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R50SEMCR register fields */ +#define RCC_R50SEMCR_SEM_MUTEX BIT(0) +#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R50SEMCR_SEMCID_SHIFT 4 + +/* RCC_R51CIDCFGR register fields */ +#define RCC_R51CIDCFGR_CFEN BIT(0) +#define RCC_R51CIDCFGR_SEM_EN BIT(1) +#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R51CIDCFGR_SCID_SHIFT 4 +#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R51SEMCR register fields */ +#define RCC_R51SEMCR_SEM_MUTEX BIT(0) +#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R51SEMCR_SEMCID_SHIFT 4 + +/* RCC_R52CIDCFGR register fields */ +#define RCC_R52CIDCFGR_CFEN BIT(0) +#define RCC_R52CIDCFGR_SEM_EN BIT(1) +#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R52CIDCFGR_SCID_SHIFT 4 +#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R52SEMCR register fields */ +#define RCC_R52SEMCR_SEM_MUTEX BIT(0) +#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R52SEMCR_SEMCID_SHIFT 4 + +/* RCC_R53CIDCFGR register fields */ +#define RCC_R53CIDCFGR_CFEN BIT(0) +#define RCC_R53CIDCFGR_SEM_EN BIT(1) +#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R53CIDCFGR_SCID_SHIFT 4 +#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R53SEMCR register fields */ +#define RCC_R53SEMCR_SEM_MUTEX BIT(0) +#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R53SEMCR_SEMCID_SHIFT 4 + +/* RCC_R54CIDCFGR register fields */ +#define RCC_R54CIDCFGR_CFEN BIT(0) +#define RCC_R54CIDCFGR_SEM_EN BIT(1) +#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R54CIDCFGR_SCID_SHIFT 4 +#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R54SEMCR register fields */ +#define RCC_R54SEMCR_SEM_MUTEX BIT(0) +#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R54SEMCR_SEMCID_SHIFT 4 + +/* RCC_R55CIDCFGR register fields */ +#define RCC_R55CIDCFGR_CFEN BIT(0) +#define RCC_R55CIDCFGR_SEM_EN BIT(1) +#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R55CIDCFGR_SCID_SHIFT 4 +#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R55SEMCR register fields */ +#define RCC_R55SEMCR_SEM_MUTEX BIT(0) +#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R55SEMCR_SEMCID_SHIFT 4 + +/* RCC_R56CIDCFGR register fields */ +#define RCC_R56CIDCFGR_CFEN BIT(0) +#define RCC_R56CIDCFGR_SEM_EN BIT(1) +#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R56CIDCFGR_SCID_SHIFT 4 +#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R56SEMCR register fields */ +#define RCC_R56SEMCR_SEM_MUTEX BIT(0) +#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R56SEMCR_SEMCID_SHIFT 4 + +/* RCC_R57CIDCFGR register fields */ +#define RCC_R57CIDCFGR_CFEN BIT(0) +#define RCC_R57CIDCFGR_SEM_EN BIT(1) +#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R57CIDCFGR_SCID_SHIFT 4 +#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R57SEMCR register fields */ +#define RCC_R57SEMCR_SEM_MUTEX BIT(0) +#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R57SEMCR_SEMCID_SHIFT 4 + +/* RCC_R58CIDCFGR register fields */ +#define RCC_R58CIDCFGR_CFEN BIT(0) +#define RCC_R58CIDCFGR_SEM_EN BIT(1) +#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R58CIDCFGR_SCID_SHIFT 4 +#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R58SEMCR register fields */ +#define RCC_R58SEMCR_SEM_MUTEX BIT(0) +#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R58SEMCR_SEMCID_SHIFT 4 + +/* RCC_R59CIDCFGR register fields */ +#define RCC_R59CIDCFGR_CFEN BIT(0) +#define RCC_R59CIDCFGR_SEM_EN BIT(1) +#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R59CIDCFGR_SCID_SHIFT 4 +#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R59SEMCR register fields */ +#define RCC_R59SEMCR_SEM_MUTEX BIT(0) +#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R59SEMCR_SEMCID_SHIFT 4 + +/* RCC_R60CIDCFGR register fields */ +#define RCC_R60CIDCFGR_CFEN BIT(0) +#define RCC_R60CIDCFGR_SEM_EN BIT(1) +#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R60CIDCFGR_SCID_SHIFT 4 +#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R60SEMCR register fields */ +#define RCC_R60SEMCR_SEM_MUTEX BIT(0) +#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R60SEMCR_SEMCID_SHIFT 4 + +/* RCC_R61CIDCFGR register fields */ +#define RCC_R61CIDCFGR_CFEN BIT(0) +#define RCC_R61CIDCFGR_SEM_EN BIT(1) +#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R61CIDCFGR_SCID_SHIFT 4 +#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R61SEMCR register fields */ +#define RCC_R61SEMCR_SEM_MUTEX BIT(0) +#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R61SEMCR_SEMCID_SHIFT 4 + +/* RCC_R62CIDCFGR register fields */ +#define RCC_R62CIDCFGR_CFEN BIT(0) +#define RCC_R62CIDCFGR_SEM_EN BIT(1) +#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R62CIDCFGR_SCID_SHIFT 4 +#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R62SEMCR register fields */ +#define RCC_R62SEMCR_SEM_MUTEX BIT(0) +#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R62SEMCR_SEMCID_SHIFT 4 + +/* RCC_R63CIDCFGR register fields */ +#define RCC_R63CIDCFGR_CFEN BIT(0) +#define RCC_R63CIDCFGR_SEM_EN BIT(1) +#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R63CIDCFGR_SCID_SHIFT 4 +#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R63SEMCR register fields */ +#define RCC_R63SEMCR_SEM_MUTEX BIT(0) +#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R63SEMCR_SEMCID_SHIFT 4 + +/* RCC_R64CIDCFGR register fields */ +#define RCC_R64CIDCFGR_CFEN BIT(0) +#define RCC_R64CIDCFGR_SEM_EN BIT(1) +#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R64CIDCFGR_SCID_SHIFT 4 +#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R64SEMCR register fields */ +#define RCC_R64SEMCR_SEM_MUTEX BIT(0) +#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R64SEMCR_SEMCID_SHIFT 4 + +/* RCC_R65CIDCFGR register fields */ +#define RCC_R65CIDCFGR_CFEN BIT(0) +#define RCC_R65CIDCFGR_SEM_EN BIT(1) +#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R65CIDCFGR_SCID_SHIFT 4 +#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R65SEMCR register fields */ +#define RCC_R65SEMCR_SEM_MUTEX BIT(0) +#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R65SEMCR_SEMCID_SHIFT 4 + +/* RCC_R66CIDCFGR register fields */ +#define RCC_R66CIDCFGR_CFEN BIT(0) +#define RCC_R66CIDCFGR_SEM_EN BIT(1) +#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R66CIDCFGR_SCID_SHIFT 4 +#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R66SEMCR register fields */ +#define RCC_R66SEMCR_SEM_MUTEX BIT(0) +#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R66SEMCR_SEMCID_SHIFT 4 + +/* RCC_R67CIDCFGR register fields */ +#define RCC_R67CIDCFGR_CFEN BIT(0) +#define RCC_R67CIDCFGR_SEM_EN BIT(1) +#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R67CIDCFGR_SCID_SHIFT 4 +#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R67SEMCR register fields */ +#define RCC_R67SEMCR_SEM_MUTEX BIT(0) +#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R67SEMCR_SEMCID_SHIFT 4 + +/* RCC_R68CIDCFGR register fields */ +#define RCC_R68CIDCFGR_CFEN BIT(0) +#define RCC_R68CIDCFGR_SEM_EN BIT(1) +#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R68CIDCFGR_SCID_SHIFT 4 +#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R68SEMCR register fields */ +#define RCC_R68SEMCR_SEM_MUTEX BIT(0) +#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R68SEMCR_SEMCID_SHIFT 4 + +/* RCC_R69CIDCFGR register fields */ +#define RCC_R69CIDCFGR_CFEN BIT(0) +#define RCC_R69CIDCFGR_SEM_EN BIT(1) +#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R69CIDCFGR_SCID_SHIFT 4 +#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R69SEMCR register fields */ +#define RCC_R69SEMCR_SEM_MUTEX BIT(0) +#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R69SEMCR_SEMCID_SHIFT 4 + +/* RCC_R70CIDCFGR register fields */ +#define RCC_R70CIDCFGR_CFEN BIT(0) +#define RCC_R70CIDCFGR_SEM_EN BIT(1) +#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R70CIDCFGR_SCID_SHIFT 4 +#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R70SEMCR register fields */ +#define RCC_R70SEMCR_SEM_MUTEX BIT(0) +#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R70SEMCR_SEMCID_SHIFT 4 + +/* RCC_R71CIDCFGR register fields */ +#define RCC_R71CIDCFGR_CFEN BIT(0) +#define RCC_R71CIDCFGR_SEM_EN BIT(1) +#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R71CIDCFGR_SCID_SHIFT 4 +#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R71SEMCR register fields */ +#define RCC_R71SEMCR_SEM_MUTEX BIT(0) +#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R71SEMCR_SEMCID_SHIFT 4 + +/* RCC_R72CIDCFGR register fields */ +#define RCC_R72CIDCFGR_CFEN BIT(0) +#define RCC_R72CIDCFGR_SEM_EN BIT(1) +#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R72CIDCFGR_SCID_SHIFT 4 +#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R72SEMCR register fields */ +#define RCC_R72SEMCR_SEM_MUTEX BIT(0) +#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R72SEMCR_SEMCID_SHIFT 4 + +/* RCC_R73CIDCFGR register fields */ +#define RCC_R73CIDCFGR_CFEN BIT(0) +#define RCC_R73CIDCFGR_SEM_EN BIT(1) +#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R73CIDCFGR_SCID_SHIFT 4 +#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R73SEMCR register fields */ +#define RCC_R73SEMCR_SEM_MUTEX BIT(0) +#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R73SEMCR_SEMCID_SHIFT 4 + +/* RCC_R74CIDCFGR register fields */ +#define RCC_R74CIDCFGR_CFEN BIT(0) +#define RCC_R74CIDCFGR_SEM_EN BIT(1) +#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R74CIDCFGR_SCID_SHIFT 4 +#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R74SEMCR register fields */ +#define RCC_R74SEMCR_SEM_MUTEX BIT(0) +#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R74SEMCR_SEMCID_SHIFT 4 + +/* RCC_R75CIDCFGR register fields */ +#define RCC_R75CIDCFGR_CFEN BIT(0) +#define RCC_R75CIDCFGR_SEM_EN BIT(1) +#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R75CIDCFGR_SCID_SHIFT 4 +#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R75SEMCR register fields */ +#define RCC_R75SEMCR_SEM_MUTEX BIT(0) +#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R75SEMCR_SEMCID_SHIFT 4 + +/* RCC_R76CIDCFGR register fields */ +#define RCC_R76CIDCFGR_CFEN BIT(0) +#define RCC_R76CIDCFGR_SEM_EN BIT(1) +#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R76CIDCFGR_SCID_SHIFT 4 +#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R76SEMCR register fields */ +#define RCC_R76SEMCR_SEM_MUTEX BIT(0) +#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R76SEMCR_SEMCID_SHIFT 4 + +/* RCC_R77CIDCFGR register fields */ +#define RCC_R77CIDCFGR_CFEN BIT(0) +#define RCC_R77CIDCFGR_SEM_EN BIT(1) +#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R77CIDCFGR_SCID_SHIFT 4 +#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R77SEMCR register fields */ +#define RCC_R77SEMCR_SEM_MUTEX BIT(0) +#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R77SEMCR_SEMCID_SHIFT 4 + +/* RCC_R78CIDCFGR register fields */ +#define RCC_R78CIDCFGR_CFEN BIT(0) +#define RCC_R78CIDCFGR_SEM_EN BIT(1) +#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R78CIDCFGR_SCID_SHIFT 4 +#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R78SEMCR register fields */ +#define RCC_R78SEMCR_SEM_MUTEX BIT(0) +#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R78SEMCR_SEMCID_SHIFT 4 + +/* RCC_R79CIDCFGR register fields */ +#define RCC_R79CIDCFGR_CFEN BIT(0) +#define RCC_R79CIDCFGR_SEM_EN BIT(1) +#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R79CIDCFGR_SCID_SHIFT 4 +#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R79SEMCR register fields */ +#define RCC_R79SEMCR_SEM_MUTEX BIT(0) +#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R79SEMCR_SEMCID_SHIFT 4 + +/* RCC_R80CIDCFGR register fields */ +#define RCC_R80CIDCFGR_CFEN BIT(0) +#define RCC_R80CIDCFGR_SEM_EN BIT(1) +#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R80CIDCFGR_SCID_SHIFT 4 +#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R80SEMCR register fields */ +#define RCC_R80SEMCR_SEM_MUTEX BIT(0) +#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R80SEMCR_SEMCID_SHIFT 4 + +/* RCC_R81CIDCFGR register fields */ +#define RCC_R81CIDCFGR_CFEN BIT(0) +#define RCC_R81CIDCFGR_SEM_EN BIT(1) +#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R81CIDCFGR_SCID_SHIFT 4 +#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R81SEMCR register fields */ +#define RCC_R81SEMCR_SEM_MUTEX BIT(0) +#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R81SEMCR_SEMCID_SHIFT 4 + +/* RCC_R82CIDCFGR register fields */ +#define RCC_R82CIDCFGR_CFEN BIT(0) +#define RCC_R82CIDCFGR_SEM_EN BIT(1) +#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R82CIDCFGR_SCID_SHIFT 4 +#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R82SEMCR register fields */ +#define RCC_R82SEMCR_SEM_MUTEX BIT(0) +#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R82SEMCR_SEMCID_SHIFT 4 + +/* RCC_R83CIDCFGR register fields */ +#define RCC_R83CIDCFGR_CFEN BIT(0) +#define RCC_R83CIDCFGR_SEM_EN BIT(1) +#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R83CIDCFGR_SCID_SHIFT 4 +#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R83SEMCR register fields */ +#define RCC_R83SEMCR_SEM_MUTEX BIT(0) +#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R83SEMCR_SEMCID_SHIFT 4 + +/* RCC_R84CIDCFGR register fields */ +#define RCC_R84CIDCFGR_CFEN BIT(0) +#define RCC_R84CIDCFGR_SEM_EN BIT(1) +#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R84CIDCFGR_SCID_SHIFT 4 +#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R84SEMCR register fields */ +#define RCC_R84SEMCR_SEM_MUTEX BIT(0) +#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R84SEMCR_SEMCID_SHIFT 4 + +/* RCC_R85CIDCFGR register fields */ +#define RCC_R85CIDCFGR_CFEN BIT(0) +#define RCC_R85CIDCFGR_SEM_EN BIT(1) +#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R85CIDCFGR_SCID_SHIFT 4 +#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R85SEMCR register fields */ +#define RCC_R85SEMCR_SEM_MUTEX BIT(0) +#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R85SEMCR_SEMCID_SHIFT 4 + +/* RCC_R86CIDCFGR register fields */ +#define RCC_R86CIDCFGR_CFEN BIT(0) +#define RCC_R86CIDCFGR_SEM_EN BIT(1) +#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R86CIDCFGR_SCID_SHIFT 4 +#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R86SEMCR register fields */ +#define RCC_R86SEMCR_SEM_MUTEX BIT(0) +#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R86SEMCR_SEMCID_SHIFT 4 + +/* RCC_R87CIDCFGR register fields */ +#define RCC_R87CIDCFGR_CFEN BIT(0) +#define RCC_R87CIDCFGR_SEM_EN BIT(1) +#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R87CIDCFGR_SCID_SHIFT 4 +#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R87SEMCR register fields */ +#define RCC_R87SEMCR_SEM_MUTEX BIT(0) +#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R87SEMCR_SEMCID_SHIFT 4 + +/* RCC_R88CIDCFGR register fields */ +#define RCC_R88CIDCFGR_CFEN BIT(0) +#define RCC_R88CIDCFGR_SEM_EN BIT(1) +#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R88CIDCFGR_SCID_SHIFT 4 +#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R88SEMCR register fields */ +#define RCC_R88SEMCR_SEM_MUTEX BIT(0) +#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R88SEMCR_SEMCID_SHIFT 4 + +/* RCC_R89CIDCFGR register fields */ +#define RCC_R89CIDCFGR_CFEN BIT(0) +#define RCC_R89CIDCFGR_SEM_EN BIT(1) +#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R89CIDCFGR_SCID_SHIFT 4 +#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R89SEMCR register fields */ +#define RCC_R89SEMCR_SEM_MUTEX BIT(0) +#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R89SEMCR_SEMCID_SHIFT 4 + +/* RCC_R90CIDCFGR register fields */ +#define RCC_R90CIDCFGR_CFEN BIT(0) +#define RCC_R90CIDCFGR_SEM_EN BIT(1) +#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R90CIDCFGR_SCID_SHIFT 4 +#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R90SEMCR register fields */ +#define RCC_R90SEMCR_SEM_MUTEX BIT(0) +#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R90SEMCR_SEMCID_SHIFT 4 + +/* RCC_R91CIDCFGR register fields */ +#define RCC_R91CIDCFGR_CFEN BIT(0) +#define RCC_R91CIDCFGR_SEM_EN BIT(1) +#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R91CIDCFGR_SCID_SHIFT 4 +#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R91SEMCR register fields */ +#define RCC_R91SEMCR_SEM_MUTEX BIT(0) +#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R91SEMCR_SEMCID_SHIFT 4 + +/* RCC_R92CIDCFGR register fields */ +#define RCC_R92CIDCFGR_CFEN BIT(0) +#define RCC_R92CIDCFGR_SEM_EN BIT(1) +#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R92CIDCFGR_SCID_SHIFT 4 +#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R92SEMCR register fields */ +#define RCC_R92SEMCR_SEM_MUTEX BIT(0) +#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R92SEMCR_SEMCID_SHIFT 4 + +/* RCC_R93CIDCFGR register fields */ +#define RCC_R93CIDCFGR_CFEN BIT(0) +#define RCC_R93CIDCFGR_SEM_EN BIT(1) +#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R93CIDCFGR_SCID_SHIFT 4 +#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R93SEMCR register fields */ +#define RCC_R93SEMCR_SEM_MUTEX BIT(0) +#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R93SEMCR_SEMCID_SHIFT 4 + +/* RCC_R94CIDCFGR register fields */ +#define RCC_R94CIDCFGR_CFEN BIT(0) +#define RCC_R94CIDCFGR_SEM_EN BIT(1) +#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R94CIDCFGR_SCID_SHIFT 4 +#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R94SEMCR register fields */ +#define RCC_R94SEMCR_SEM_MUTEX BIT(0) +#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R94SEMCR_SEMCID_SHIFT 4 + +/* RCC_R95CIDCFGR register fields */ +#define RCC_R95CIDCFGR_CFEN BIT(0) +#define RCC_R95CIDCFGR_SEM_EN BIT(1) +#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R95CIDCFGR_SCID_SHIFT 4 +#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R95SEMCR register fields */ +#define RCC_R95SEMCR_SEM_MUTEX BIT(0) +#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R95SEMCR_SEMCID_SHIFT 4 + +/* RCC_R96CIDCFGR register fields */ +#define RCC_R96CIDCFGR_CFEN BIT(0) +#define RCC_R96CIDCFGR_SEM_EN BIT(1) +#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R96CIDCFGR_SCID_SHIFT 4 +#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R96SEMCR register fields */ +#define RCC_R96SEMCR_SEM_MUTEX BIT(0) +#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R96SEMCR_SEMCID_SHIFT 4 + +/* RCC_R97CIDCFGR register fields */ +#define RCC_R97CIDCFGR_CFEN BIT(0) +#define RCC_R97CIDCFGR_SEM_EN BIT(1) +#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R97CIDCFGR_SCID_SHIFT 4 +#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R97SEMCR register fields */ +#define RCC_R97SEMCR_SEM_MUTEX BIT(0) +#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R97SEMCR_SEMCID_SHIFT 4 + +/* RCC_R98CIDCFGR register fields */ +#define RCC_R98CIDCFGR_CFEN BIT(0) +#define RCC_R98CIDCFGR_SEM_EN BIT(1) +#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R98CIDCFGR_SCID_SHIFT 4 +#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R98SEMCR register fields */ +#define RCC_R98SEMCR_SEM_MUTEX BIT(0) +#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R98SEMCR_SEMCID_SHIFT 4 + +/* RCC_R99CIDCFGR register fields */ +#define RCC_R99CIDCFGR_CFEN BIT(0) +#define RCC_R99CIDCFGR_SEM_EN BIT(1) +#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R99CIDCFGR_SCID_SHIFT 4 +#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R99SEMCR register fields */ +#define RCC_R99SEMCR_SEM_MUTEX BIT(0) +#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R99SEMCR_SEMCID_SHIFT 4 + +/* RCC_R100CIDCFGR register fields */ +#define RCC_R100CIDCFGR_CFEN BIT(0) +#define RCC_R100CIDCFGR_SEM_EN BIT(1) +#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R100CIDCFGR_SCID_SHIFT 4 +#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R100SEMCR register fields */ +#define RCC_R100SEMCR_SEM_MUTEX BIT(0) +#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R100SEMCR_SEMCID_SHIFT 4 + +/* RCC_R101CIDCFGR register fields */ +#define RCC_R101CIDCFGR_CFEN BIT(0) +#define RCC_R101CIDCFGR_SEM_EN BIT(1) +#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R101CIDCFGR_SCID_SHIFT 4 +#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R101SEMCR register fields */ +#define RCC_R101SEMCR_SEM_MUTEX BIT(0) +#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R101SEMCR_SEMCID_SHIFT 4 + +/* RCC_R102CIDCFGR register fields */ +#define RCC_R102CIDCFGR_CFEN BIT(0) +#define RCC_R102CIDCFGR_SEM_EN BIT(1) +#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R102CIDCFGR_SCID_SHIFT 4 +#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R102SEMCR register fields */ +#define RCC_R102SEMCR_SEM_MUTEX BIT(0) +#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R102SEMCR_SEMCID_SHIFT 4 + +/* RCC_R103CIDCFGR register fields */ +#define RCC_R103CIDCFGR_CFEN BIT(0) +#define RCC_R103CIDCFGR_SEM_EN BIT(1) +#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R103CIDCFGR_SCID_SHIFT 4 +#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R103SEMCR register fields */ +#define RCC_R103SEMCR_SEM_MUTEX BIT(0) +#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R103SEMCR_SEMCID_SHIFT 4 + +/* RCC_R104CIDCFGR register fields */ +#define RCC_R104CIDCFGR_CFEN BIT(0) +#define RCC_R104CIDCFGR_SEM_EN BIT(1) +#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R104CIDCFGR_SCID_SHIFT 4 +#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R104SEMCR register fields */ +#define RCC_R104SEMCR_SEM_MUTEX BIT(0) +#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R104SEMCR_SEMCID_SHIFT 4 + +/* RCC_R105CIDCFGR register fields */ +#define RCC_R105CIDCFGR_CFEN BIT(0) +#define RCC_R105CIDCFGR_SEM_EN BIT(1) +#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R105CIDCFGR_SCID_SHIFT 4 +#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R105SEMCR register fields */ +#define RCC_R105SEMCR_SEM_MUTEX BIT(0) +#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R105SEMCR_SEMCID_SHIFT 4 + +/* RCC_R106CIDCFGR register fields */ +#define RCC_R106CIDCFGR_CFEN BIT(0) +#define RCC_R106CIDCFGR_SEM_EN BIT(1) +#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R106CIDCFGR_SCID_SHIFT 4 +#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R106SEMCR register fields */ +#define RCC_R106SEMCR_SEM_MUTEX BIT(0) +#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R106SEMCR_SEMCID_SHIFT 4 + +/* RCC_R107CIDCFGR register fields */ +#define RCC_R107CIDCFGR_CFEN BIT(0) +#define RCC_R107CIDCFGR_SEM_EN BIT(1) +#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R107CIDCFGR_SCID_SHIFT 4 +#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R107SEMCR register fields */ +#define RCC_R107SEMCR_SEM_MUTEX BIT(0) +#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R107SEMCR_SEMCID_SHIFT 4 + +/* RCC_R108CIDCFGR register fields */ +#define RCC_R108CIDCFGR_CFEN BIT(0) +#define RCC_R108CIDCFGR_SEM_EN BIT(1) +#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R108CIDCFGR_SCID_SHIFT 4 +#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R108SEMCR register fields */ +#define RCC_R108SEMCR_SEM_MUTEX BIT(0) +#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R108SEMCR_SEMCID_SHIFT 4 + +/* RCC_R109CIDCFGR register fields */ +#define RCC_R109CIDCFGR_CFEN BIT(0) +#define RCC_R109CIDCFGR_SEM_EN BIT(1) +#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R109CIDCFGR_SCID_SHIFT 4 +#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R109SEMCR register fields */ +#define RCC_R109SEMCR_SEM_MUTEX BIT(0) +#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R109SEMCR_SEMCID_SHIFT 4 + +/* RCC_R110CIDCFGR register fields */ +#define RCC_R110CIDCFGR_CFEN BIT(0) +#define RCC_R110CIDCFGR_SEM_EN BIT(1) +#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R110CIDCFGR_SCID_SHIFT 4 +#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R110SEMCR register fields */ +#define RCC_R110SEMCR_SEM_MUTEX BIT(0) +#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R110SEMCR_SEMCID_SHIFT 4 + +/* RCC_R111CIDCFGR register fields */ +#define RCC_R111CIDCFGR_CFEN BIT(0) +#define RCC_R111CIDCFGR_SEM_EN BIT(1) +#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R111CIDCFGR_SCID_SHIFT 4 +#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R111SEMCR register fields */ +#define RCC_R111SEMCR_SEM_MUTEX BIT(0) +#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R111SEMCR_SEMCID_SHIFT 4 + +/* RCC_R112CIDCFGR register fields */ +#define RCC_R112CIDCFGR_CFEN BIT(0) +#define RCC_R112CIDCFGR_SEM_EN BIT(1) +#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R112CIDCFGR_SCID_SHIFT 4 +#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R112SEMCR register fields */ +#define RCC_R112SEMCR_SEM_MUTEX BIT(0) +#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R112SEMCR_SEMCID_SHIFT 4 + +/* RCC_R113CIDCFGR register fields */ +#define RCC_R113CIDCFGR_CFEN BIT(0) +#define RCC_R113CIDCFGR_SEM_EN BIT(1) +#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R113CIDCFGR_SCID_SHIFT 4 +#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R113SEMCR register fields */ +#define RCC_R113SEMCR_SEM_MUTEX BIT(0) +#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R113SEMCR_SEMCID_SHIFT 4 + +/* RCC_RxCIDCFGR register fields */ +#define RCC_RxCIDCFGR_CFEN BIT(0) +#define RCC_RxCIDCFGR_SEM_EN BIT(1) +#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_RxCIDCFGR_SCID_SHIFT 4 +#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_RxSEMCR register fields */ +#define RCC_RxSEMCR_SEM_MUTEX BIT(0) +#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_RxSEMCR_SEMCID_SHIFT 4 + +/* RCC_GRSTCSETR register fields */ +#define RCC_GRSTCSETR_SYSRST BIT(0) + +/* RCC_C1RSTCSETR register fields */ +#define RCC_C1RSTCSETR_C1RST BIT(0) + +/* RCC_C1P1RSTCSETR register fields */ +#define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0) +#define RCC_C1P1RSTCSETR_C1P1RST BIT(1) + +/* RCC_C2RSTCSETR register fields */ +#define RCC_C2RSTCSETR_C2RST BIT(0) + +/* RCC_CxRSTCSETR register fields */ +#define RCC_CxRSTCSETR_CxRST BIT(0) + +/* RCC_HWRSTSCLRR register fields */ +#define RCC_HWRSTSCLRR_PORRSTF BIT(0) +#define RCC_HWRSTSCLRR_BORRSTF BIT(1) +#define RCC_HWRSTSCLRR_PADRSTF BIT(2) +#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_HWRSTSCLRR_VCORERSTF BIT(4) +#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) +#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) +#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) +#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) +#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) +#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) +#define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11) +#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) +#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) +#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) + +/* RCC_C1HWRSTSCLRR register fields */ +#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) +#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) +#define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2) + +/* RCC_C2HWRSTSCLRR register fields */ +#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) + +/* RCC_C1BOOTRSTSSETR register fields */ +#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C1BOOTRSTSCLRR register fields */ +#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSSETR register fields */ +#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSCLRR register fields */ +#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C1SREQSETR register fields */ +#define RCC_C1SREQSETR_STPREQ_P0 BIT(0) +#define RCC_C1SREQSETR_STPREQ_P1 BIT(1) +#define RCC_C1SREQSETR_ESLPREQ BIT(16) + +/* RCC_C1SREQCLRR register fields */ +#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1) +#define RCC_C1SREQCLRR_ESLPREQ BIT(16) + +/* RCC_CPUBOOTCR register fields */ +#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) +#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) + +/* RCC_STBYBOOTCR register fields */ +#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) +#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) +#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) +#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) +#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) + +/* RCC_LEGBOOTCR register fields */ +#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_LSEDIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(6) +#define RCC_BDCR_LSEGFON BIT(7) +#define RCC_BDCR_LSECSSD BIT(8) +#define RCC_BDCR_LSION BIT(9) +#define RCC_BDCR_LSIRDY BIT(10) +#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_MSIFREQSEL BIT(24) +#define RCC_BDCR_C3SYSTICKSEL BIT(25) +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSEDIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 6 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_LSIRDY_BIT 10 + +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_D3DCR register fields */ +#define RCC_D3DCR_CSION BIT(0) +#define RCC_D3DCR_CSIKERON BIT(1) +#define RCC_D3DCR_CSIRDY BIT(2) +#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16) +#define RCC_D3DCR_D3PERCKSEL_SHIFT 16 +#define RCC_D3DCR_CSIRDY_BIT 2 + +/* RCC_D3DSR register fields */ +#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0) +#define RCC_D3DSR_D3STATE_SHIFT 0 + +/* RCC_RDCR register fields */ +#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) +#define RCC_RDCR_MRD_SHIFT 16 +#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) +#define RCC_RDCR_EADLY_SHIFT 24 + +/* RCC_C1MSRDCR register fields */ +#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) +#define RCC_C1MSRDCR_C1MSRD_SHIFT 0 +#define RCC_C1MSRDCR_C1MSRST BIT(8) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) + +/* RCC_C1CIESETR register fields */ +#define RCC_C1CIESETR_LSIRDYIE BIT(0) +#define RCC_C1CIESETR_LSERDYIE BIT(1) +#define RCC_C1CIESETR_HSIRDYIE BIT(2) +#define RCC_C1CIESETR_HSERDYIE BIT(3) +#define RCC_C1CIESETR_CSIRDYIE BIT(4) +#define RCC_C1CIESETR_PLL1RDYIE BIT(5) +#define RCC_C1CIESETR_PLL2RDYIE BIT(6) +#define RCC_C1CIESETR_PLL3RDYIE BIT(7) +#define RCC_C1CIESETR_PLL4RDYIE BIT(8) +#define RCC_C1CIESETR_PLL5RDYIE BIT(9) +#define RCC_C1CIESETR_PLL6RDYIE BIT(10) +#define RCC_C1CIESETR_PLL7RDYIE BIT(11) +#define RCC_C1CIESETR_PLL8RDYIE BIT(12) +#define RCC_C1CIESETR_LSECSSIE BIT(16) +#define RCC_C1CIESETR_WKUPIE BIT(20) + +/* RCC_C1CIFCLRR register fields */ +#define RCC_C1CIFCLRR_LSIRDYF BIT(0) +#define RCC_C1CIFCLRR_LSERDYF BIT(1) +#define RCC_C1CIFCLRR_HSIRDYF BIT(2) +#define RCC_C1CIFCLRR_HSERDYF BIT(3) +#define RCC_C1CIFCLRR_CSIRDYF BIT(4) +#define RCC_C1CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C1CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C1CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C1CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C1CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C1CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C1CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C1CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C1CIFCLRR_LSECSSF BIT(16) +#define RCC_C1CIFCLRR_WKUPF BIT(20) + +/* RCC_C2CIESETR register fields */ +#define RCC_C2CIESETR_LSIRDYIE BIT(0) +#define RCC_C2CIESETR_LSERDYIE BIT(1) +#define RCC_C2CIESETR_HSIRDYIE BIT(2) +#define RCC_C2CIESETR_HSERDYIE BIT(3) +#define RCC_C2CIESETR_CSIRDYIE BIT(4) +#define RCC_C2CIESETR_PLL1RDYIE BIT(5) +#define RCC_C2CIESETR_PLL2RDYIE BIT(6) +#define RCC_C2CIESETR_PLL3RDYIE BIT(7) +#define RCC_C2CIESETR_PLL4RDYIE BIT(8) +#define RCC_C2CIESETR_PLL5RDYIE BIT(9) +#define RCC_C2CIESETR_PLL6RDYIE BIT(10) +#define RCC_C2CIESETR_PLL7RDYIE BIT(11) +#define RCC_C2CIESETR_PLL8RDYIE BIT(12) +#define RCC_C2CIESETR_LSECSSIE BIT(16) +#define RCC_C2CIESETR_WKUPIE BIT(20) + +/* RCC_C2CIFCLRR register fields */ +#define RCC_C2CIFCLRR_LSIRDYF BIT(0) +#define RCC_C2CIFCLRR_LSERDYF BIT(1) +#define RCC_C2CIFCLRR_HSIRDYF BIT(2) +#define RCC_C2CIFCLRR_HSERDYF BIT(3) +#define RCC_C2CIFCLRR_CSIRDYF BIT(4) +#define RCC_C2CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C2CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C2CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C2CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C2CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C2CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C2CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C2CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C2CIFCLRR_LSECSSF BIT(16) +#define RCC_C2CIFCLRR_WKUPF BIT(20) + +/* RCC_CxCIESETR register fields */ +#define RCC_CxCIESETR_LSIRDYIE BIT(0) +#define RCC_CxCIESETR_LSERDYIE BIT(1) +#define RCC_CxCIESETR_HSIRDYIE BIT(2) +#define RCC_CxCIESETR_HSERDYIE BIT(3) +#define RCC_CxCIESETR_CSIRDYIE BIT(4) +#define RCC_CxCIESETR_SHSIRDYIE BIT(5) +#define RCC_CxCIESETR_PLL1RDYIE BIT(6) +#define RCC_CxCIESETR_PLL2RDYIE BIT(7) +#define RCC_CxCIESETR_PLL3RDYIE BIT(8) +#define RCC_CxCIESETR_PLL4RDYIE BIT(9) +#define RCC_CxCIESETR_PLL5RDYIE BIT(10) +#define RCC_CxCIESETR_PLL6RDYIE BIT(11) +#define RCC_CxCIESETR_PLL7RDYIE BIT(12) +#define RCC_CxCIESETR_PLL8RDYIE BIT(13) +#define RCC_CxCIESETR_LSECSSIE BIT(16) +#define RCC_CxCIESETR_WKUPIE BIT(20) + +/* RCC_CxCIFCLRR register fields */ +#define RCC_CxCIFCLRR_LSIRDYF BIT(0) +#define RCC_CxCIFCLRR_LSERDYF BIT(1) +#define RCC_CxCIFCLRR_HSIRDYF BIT(2) +#define RCC_CxCIFCLRR_HSERDYF BIT(3) +#define RCC_CxCIFCLRR_CSIRDYF BIT(4) +#define RCC_CxCIFCLRR_SHSIRDYF BIT(5) +#define RCC_CxCIFCLRR_PLL1RDYF BIT(6) +#define RCC_CxCIFCLRR_PLL2RDYF BIT(7) +#define RCC_CxCIFCLRR_PLL3RDYF BIT(8) +#define RCC_CxCIFCLRR_PLL4RDYF BIT(9) +#define RCC_CxCIFCLRR_PLL5RDYF BIT(10) +#define RCC_CxCIFCLRR_PLL6RDYF BIT(11) +#define RCC_CxCIFCLRR_PLL7RDYF BIT(12) +#define RCC_CxCIFCLRR_PLL8RDYF BIT(13) +#define RCC_CxCIFCLRR_LSECSSF BIT(16) +#define RCC_CxCIFCLRR_WKUPF BIT(20) + +/* RCC_IWDGC1FZSETR register fields */ +#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1FZCLRR register fields */ +#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1CFGSETR register fields */ +#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC1CFGCLRR register fields */ +#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC2FZSETR register fields */ +#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2FZCLRR register fields */ +#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2CFGSETR register fields */ +#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC2CFGCLRR register fields */ +#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC3CFGSETR register fields */ +#define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_IWDGC3CFGCLRR register fields */ +#define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_C3CFGR register fields */ +#define RCC_C3CFGR_C3RST BIT(0) +#define RCC_C3CFGR_C3EN BIT(1) +#define RCC_C3CFGR_C3LPEN BIT(2) +#define RCC_C3CFGR_C3AMEN BIT(3) +#define RCC_C3CFGR_LPTIM3C3EN BIT(16) +#define RCC_C3CFGR_LPTIM4C3EN BIT(17) +#define RCC_C3CFGR_LPTIM5C3EN BIT(18) +#define RCC_C3CFGR_SPI8C3EN BIT(19) +#define RCC_C3CFGR_LPUART1C3EN BIT(20) +#define RCC_C3CFGR_I2C8C3EN BIT(21) +#define RCC_C3CFGR_ADF1C3EN BIT(23) +#define RCC_C3CFGR_GPIOZC3EN BIT(24) +#define RCC_C3CFGR_LPDMAC3EN BIT(25) +#define RCC_C3CFGR_RTCC3EN BIT(26) +#define RCC_C3CFGR_I3C4C3EN BIT(27) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL BIT(0) +#define RCC_MCO1CFGR_MCO1ON BIT(8) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL BIT(0) +#define RCC_MCO2CFGR_MCO2ON BIT(8) + +/* RCC_MCOxCFGR register fields */ +#define RCC_MCOxCFGR_MCOxSEL BIT(0) +#define RCC_MCOxCFGR_MCOxON BIT(8) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_HSEDIV2ON BIT(5) +#define RCC_OCENSETR_HSEDIV2BYP BIT(6) +#define RCC_OCENSETR_HSEDIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_HSEDIV2ON BIT(5) +#define RCC_OCENCLRR_HSEDIV2BYP BIT(6) +#define RCC_OCENCLRR_HSEDIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_CKREST BIT(25) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APBDBGDIVR register fields */ +#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) +#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0 +#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) + +/* RCC_APBxDIVR register fields */ +#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0) +#define RCC_APBxDIVR_APBxDIV_SHIFT 0 +#define RCC_APBxDIVR_APBxDIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMGxPRER register fields */ +#define RCC_TIMGxPRER_TIMGxPRE BIT(0) +#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31) + +/* RCC_LSMCUDIVR register fields */ +#define RCC_LSMCUDIVR_LSMCUDIV BIT(0) +#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) + +/* RCC_DDRCPCFGR register fields */ +#define RCC_DDRCPCFGR_DDRCPRST BIT(0) +#define RCC_DDRCPCFGR_DDRCPEN BIT(1) +#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) + +/* RCC_DDRCAPBCFGR register fields */ +#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) +#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) +#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) + +/* RCC_DDRPHYCAPBCFGR register fields */ +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) + +/* RCC_DDRPHYCCFGR register fields */ +#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) + +/* RCC_DDRCFGR register fields */ +#define RCC_DDRCFGR_DDRCFGRST BIT(0) +#define RCC_DDRCFGR_DDRCFGEN BIT(1) +#define RCC_DDRCFGR_DDRCFGLPEN BIT(2) + +/* RCC_DDRITFCFGR register fields */ +#define RCC_DDRITFCFGR_DDRRST BIT(0) +#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) +#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4 +#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5) +#define RCC_DDRITFCFGR_DDRSHR BIT(8) +#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) + +/* RCC_SYSRAMCFGR register fields */ +#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) +#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) + +/* RCC_VDERAMCFGR register fields */ +#define RCC_VDERAMCFGR_VDERAMEN BIT(1) +#define RCC_VDERAMCFGR_VDERAMLPEN BIT(2) + +/* RCC_SRAM1CFGR register fields */ +#define RCC_SRAM1CFGR_SRAM1EN BIT(1) +#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) + +/* RCC_SRAM2CFGR register fields */ +#define RCC_SRAM2CFGR_SRAM2EN BIT(1) +#define RCC_SRAM2CFGR_SRAM2LPEN BIT(2) + +/* RCC_RETRAMCFGR register fields */ +#define RCC_RETRAMCFGR_RETRAMEN BIT(1) +#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) + +/* RCC_BKPSRAMCFGR register fields */ +#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) +#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) + +/* RCC_LPSRAM1CFGR register fields */ +#define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1) +#define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2) +#define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3) + +/* RCC_LPSRAM2CFGR register fields */ +#define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1) +#define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2) +#define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3) + +/* RCC_LPSRAM3CFGR register fields */ +#define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1) +#define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2) +#define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3) + +/* RCC_OSPI1CFGR register fields */ +#define RCC_OSPI1CFGR_OSPI1RST BIT(0) +#define RCC_OSPI1CFGR_OSPI1EN BIT(1) +#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) +#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) +#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) + +/* RCC_OSPI2CFGR register fields */ +#define RCC_OSPI2CFGR_OSPI2RST BIT(0) +#define RCC_OSPI2CFGR_OSPI2EN BIT(1) +#define RCC_OSPI2CFGR_OSPI2LPEN BIT(2) +#define RCC_OSPI2CFGR_OTFDEC2RST BIT(8) +#define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16) + +/* RCC_OSPIxCFGR register fields */ +#define RCC_OSPIxCFGR_OSPIxRST BIT(0) +#define RCC_OSPIxCFGR_OSPIxEN BIT(1) +#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2) +#define RCC_OSPIxCFGR_OTFDECxRST BIT(8) +#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16) + +/* RCC_FMCCFGR register fields */ +#define RCC_FMCCFGR_FMCRST BIT(0) +#define RCC_FMCCFGR_FMCEN BIT(1) +#define RCC_FMCCFGR_FMCLPEN BIT(2) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_DBGEN BIT(8) +#define RCC_DBGCFGR_TRACEEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_STM500CFGR register fields */ +#define RCC_STM500CFGR_STM500EN BIT(1) +#define RCC_STM500CFGR_STM500LPEN BIT(2) + +/* RCC_ETRCFGR register fields */ +#define RCC_ETRCFGR_ETREN BIT(1) +#define RCC_ETRCFGR_ETRLPEN BIT(2) + +/* RCC_GPIOACFGR register fields */ +#define RCC_GPIOACFGR_GPIOARST BIT(0) +#define RCC_GPIOACFGR_GPIOAEN BIT(1) +#define RCC_GPIOACFGR_GPIOALPEN BIT(2) + +/* RCC_GPIOBCFGR register fields */ +#define RCC_GPIOBCFGR_GPIOBRST BIT(0) +#define RCC_GPIOBCFGR_GPIOBEN BIT(1) +#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) + +/* RCC_GPIOCCFGR register fields */ +#define RCC_GPIOCCFGR_GPIOCRST BIT(0) +#define RCC_GPIOCCFGR_GPIOCEN BIT(1) +#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) + +/* RCC_GPIODCFGR register fields */ +#define RCC_GPIODCFGR_GPIODRST BIT(0) +#define RCC_GPIODCFGR_GPIODEN BIT(1) +#define RCC_GPIODCFGR_GPIODLPEN BIT(2) + +/* RCC_GPIOECFGR register fields */ +#define RCC_GPIOECFGR_GPIOERST BIT(0) +#define RCC_GPIOECFGR_GPIOEEN BIT(1) +#define RCC_GPIOECFGR_GPIOELPEN BIT(2) + +/* RCC_GPIOFCFGR register fields */ +#define RCC_GPIOFCFGR_GPIOFRST BIT(0) +#define RCC_GPIOFCFGR_GPIOFEN BIT(1) +#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) + +/* RCC_GPIOGCFGR register fields */ +#define RCC_GPIOGCFGR_GPIOGRST BIT(0) +#define RCC_GPIOGCFGR_GPIOGEN BIT(1) +#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) + +/* RCC_GPIOHCFGR register fields */ +#define RCC_GPIOHCFGR_GPIOHRST BIT(0) +#define RCC_GPIOHCFGR_GPIOHEN BIT(1) +#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) + +/* RCC_GPIOICFGR register fields */ +#define RCC_GPIOICFGR_GPIOIRST BIT(0) +#define RCC_GPIOICFGR_GPIOIEN BIT(1) +#define RCC_GPIOICFGR_GPIOILPEN BIT(2) + +/* RCC_GPIOJCFGR register fields */ +#define RCC_GPIOJCFGR_GPIOJRST BIT(0) +#define RCC_GPIOJCFGR_GPIOJEN BIT(1) +#define RCC_GPIOJCFGR_GPIOJLPEN BIT(2) + +/* RCC_GPIOKCFGR register fields */ +#define RCC_GPIOKCFGR_GPIOKRST BIT(0) +#define RCC_GPIOKCFGR_GPIOKEN BIT(1) +#define RCC_GPIOKCFGR_GPIOKLPEN BIT(2) + +/* RCC_GPIOZCFGR register fields */ +#define RCC_GPIOZCFGR_GPIOZRST BIT(0) +#define RCC_GPIOZCFGR_GPIOZEN BIT(1) +#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) +#define RCC_GPIOZCFGR_GPIOZAMEN BIT(3) + +/* RCC_GPIOxCFGR register fields */ +#define RCC_GPIOxCFGR_GPIOxRST BIT(0) +#define RCC_GPIOxCFGR_GPIOxEN BIT(1) +#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2) +#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3) + +/* RCC_HPDMA1CFGR register fields */ +#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) +#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) +#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) + +/* RCC_HPDMA2CFGR register fields */ +#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) +#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) +#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) + +/* RCC_HPDMA3CFGR register fields */ +#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) +#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) +#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) + +/* RCC_HPDMAxCFGR register fields */ +#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0) +#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1) +#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2) + +/* RCC_LPDMACFGR register fields */ +#define RCC_LPDMACFGR_LPDMARST BIT(0) +#define RCC_LPDMACFGR_LPDMAEN BIT(1) +#define RCC_LPDMACFGR_LPDMALPEN BIT(2) +#define RCC_LPDMACFGR_LPDMAAMEN BIT(3) + +/* RCC_HSEMCFGR register fields */ +#define RCC_HSEMCFGR_HSEMRST BIT(0) +#define RCC_HSEMCFGR_HSEMEN BIT(1) +#define RCC_HSEMCFGR_HSEMLPEN BIT(2) +#define RCC_HSEMCFGR_HSEMAMEN BIT(3) + +/* RCC_IPCC1CFGR register fields */ +#define RCC_IPCC1CFGR_IPCC1RST BIT(0) +#define RCC_IPCC1CFGR_IPCC1EN BIT(1) +#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) + +/* RCC_IPCC2CFGR register fields */ +#define RCC_IPCC2CFGR_IPCC2RST BIT(0) +#define RCC_IPCC2CFGR_IPCC2EN BIT(1) +#define RCC_IPCC2CFGR_IPCC2LPEN BIT(2) +#define RCC_IPCC2CFGR_IPCC2AMEN BIT(3) + +/* RCC_RTCCFGR register fields */ +#define RCC_RTCCFGR_RTCEN BIT(1) +#define RCC_RTCCFGR_RTCLPEN BIT(2) +#define RCC_RTCCFGR_RTCAMEN BIT(3) + +/* RCC_SYSCPU1CFGR register fields */ +#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) +#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) + +/* RCC_BSECCFGR register fields */ +#define RCC_BSECCFGR_BSECEN BIT(1) +#define RCC_BSECCFGR_BSECLPEN BIT(2) + +/* RCC_IS2MCFGR register fields */ +#define RCC_IS2MCFGR_IS2MRST BIT(0) +#define RCC_IS2MCFGR_IS2MEN BIT(1) +#define RCC_IS2MCFGR_IS2MLPEN BIT(2) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_SSMODRST BIT(0) +#define RCC_PLL2CFGR1_PLLEN BIT(8) +#define RCC_PLL2CFGR1_PLLRDY BIT(24) +#define RCC_PLL2CFGR1_CKREFST BIT(28) + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL2CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL2CFGR3 register fields */ +#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL2CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL2CFGR3_DACEN BIT(25) +#define RCC_PLL2CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL2CFGR4 register fields */ +#define RCC_PLL2CFGR4_DSMEN BIT(8) +#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL2CFGR4_BYPASS BIT(10) + +/* RCC_PLL2CFGR5 register fields */ +#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL2CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL2CFGR6 register fields */ +#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL2CFGR7 register fields */ +#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_SSMODRST BIT(0) +#define RCC_PLL3CFGR1_PLLEN BIT(8) +#define RCC_PLL3CFGR1_PLLRDY BIT(24) +#define RCC_PLL3CFGR1_CKREFST BIT(28) + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL3CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL3CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL3CFGR3 register fields */ +#define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL3CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL3CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL3CFGR3_DACEN BIT(25) +#define RCC_PLL3CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL3CFGR4 register fields */ +#define RCC_PLL3CFGR4_DSMEN BIT(8) +#define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL3CFGR4_BYPASS BIT(10) + +/* RCC_PLL3CFGR5 register fields */ +#define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL3CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL3CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL3CFGR6 register fields */ +#define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL3CFGR7 register fields */ +#define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_HSIFMONCR register fields */ +#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) +#define RCC_HSIFMONCR_HSIREF_SHIFT 0 +#define RCC_HSIFMONCR_HSIMONEN BIT(15) +#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) +#define RCC_HSIFMONCR_HSIDEV_SHIFT 16 +#define RCC_HSIFMONCR_HSIMONIE BIT(30) +#define RCC_HSIFMONCR_HSIMONF BIT(31) + +/* RCC_HSIFVALR register fields */ +#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) +#define RCC_HSIFVALR_HSIVAL_SHIFT 0 + +/* RCC_TIM1CFGR register fields */ +#define RCC_TIM1CFGR_TIM1RST BIT(0) +#define RCC_TIM1CFGR_TIM1EN BIT(1) +#define RCC_TIM1CFGR_TIM1LPEN BIT(2) + +/* RCC_TIM2CFGR register fields */ +#define RCC_TIM2CFGR_TIM2RST BIT(0) +#define RCC_TIM2CFGR_TIM2EN BIT(1) +#define RCC_TIM2CFGR_TIM2LPEN BIT(2) + +/* RCC_TIM3CFGR register fields */ +#define RCC_TIM3CFGR_TIM3RST BIT(0) +#define RCC_TIM3CFGR_TIM3EN BIT(1) +#define RCC_TIM3CFGR_TIM3LPEN BIT(2) + +/* RCC_TIM4CFGR register fields */ +#define RCC_TIM4CFGR_TIM4RST BIT(0) +#define RCC_TIM4CFGR_TIM4EN BIT(1) +#define RCC_TIM4CFGR_TIM4LPEN BIT(2) + +/* RCC_TIM5CFGR register fields */ +#define RCC_TIM5CFGR_TIM5RST BIT(0) +#define RCC_TIM5CFGR_TIM5EN BIT(1) +#define RCC_TIM5CFGR_TIM5LPEN BIT(2) + +/* RCC_TIM6CFGR register fields */ +#define RCC_TIM6CFGR_TIM6RST BIT(0) +#define RCC_TIM6CFGR_TIM6EN BIT(1) +#define RCC_TIM6CFGR_TIM6LPEN BIT(2) + +/* RCC_TIM7CFGR register fields */ +#define RCC_TIM7CFGR_TIM7RST BIT(0) +#define RCC_TIM7CFGR_TIM7EN BIT(1) +#define RCC_TIM7CFGR_TIM7LPEN BIT(2) + +/* RCC_TIM8CFGR register fields */ +#define RCC_TIM8CFGR_TIM8RST BIT(0) +#define RCC_TIM8CFGR_TIM8EN BIT(1) +#define RCC_TIM8CFGR_TIM8LPEN BIT(2) + +/* RCC_TIM10CFGR register fields */ +#define RCC_TIM10CFGR_TIM10RST BIT(0) +#define RCC_TIM10CFGR_TIM10EN BIT(1) +#define RCC_TIM10CFGR_TIM10LPEN BIT(2) + +/* RCC_TIM11CFGR register fields */ +#define RCC_TIM11CFGR_TIM11RST BIT(0) +#define RCC_TIM11CFGR_TIM11EN BIT(1) +#define RCC_TIM11CFGR_TIM11LPEN BIT(2) + +/* RCC_TIM12CFGR register fields */ +#define RCC_TIM12CFGR_TIM12RST BIT(0) +#define RCC_TIM12CFGR_TIM12EN BIT(1) +#define RCC_TIM12CFGR_TIM12LPEN BIT(2) + +/* RCC_TIM13CFGR register fields */ +#define RCC_TIM13CFGR_TIM13RST BIT(0) +#define RCC_TIM13CFGR_TIM13EN BIT(1) +#define RCC_TIM13CFGR_TIM13LPEN BIT(2) + +/* RCC_TIM14CFGR register fields */ +#define RCC_TIM14CFGR_TIM14RST BIT(0) +#define RCC_TIM14CFGR_TIM14EN BIT(1) +#define RCC_TIM14CFGR_TIM14LPEN BIT(2) + +/* RCC_TIM15CFGR register fields */ +#define RCC_TIM15CFGR_TIM15RST BIT(0) +#define RCC_TIM15CFGR_TIM15EN BIT(1) +#define RCC_TIM15CFGR_TIM15LPEN BIT(2) + +/* RCC_TIM16CFGR register fields */ +#define RCC_TIM16CFGR_TIM16RST BIT(0) +#define RCC_TIM16CFGR_TIM16EN BIT(1) +#define RCC_TIM16CFGR_TIM16LPEN BIT(2) + +/* RCC_TIM17CFGR register fields */ +#define RCC_TIM17CFGR_TIM17RST BIT(0) +#define RCC_TIM17CFGR_TIM17EN BIT(1) +#define RCC_TIM17CFGR_TIM17LPEN BIT(2) + +/* RCC_TIM20CFGR register fields */ +#define RCC_TIM20CFGR_TIM20RST BIT(0) +#define RCC_TIM20CFGR_TIM20EN BIT(1) +#define RCC_TIM20CFGR_TIM20LPEN BIT(2) + +/* RCC_LPTIM1CFGR register fields */ +#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) +#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) +#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) + +/* RCC_LPTIM2CFGR register fields */ +#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) +#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) +#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) + +/* RCC_LPTIM3CFGR register fields */ +#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) +#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) +#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) +#define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3) + +/* RCC_LPTIM4CFGR register fields */ +#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) +#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) +#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) +#define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3) + +/* RCC_LPTIM5CFGR register fields */ +#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) +#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) +#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) +#define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3) + +/* RCC_LPTIMxCFGR register fields */ +#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0) +#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1) +#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2) +#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3) + +/* RCC_SPI1CFGR register fields */ +#define RCC_SPI1CFGR_SPI1RST BIT(0) +#define RCC_SPI1CFGR_SPI1EN BIT(1) +#define RCC_SPI1CFGR_SPI1LPEN BIT(2) + +/* RCC_SPI2CFGR register fields */ +#define RCC_SPI2CFGR_SPI2RST BIT(0) +#define RCC_SPI2CFGR_SPI2EN BIT(1) +#define RCC_SPI2CFGR_SPI2LPEN BIT(2) + +/* RCC_SPI3CFGR register fields */ +#define RCC_SPI3CFGR_SPI3RST BIT(0) +#define RCC_SPI3CFGR_SPI3EN BIT(1) +#define RCC_SPI3CFGR_SPI3LPEN BIT(2) + +/* RCC_SPI4CFGR register fields */ +#define RCC_SPI4CFGR_SPI4RST BIT(0) +#define RCC_SPI4CFGR_SPI4EN BIT(1) +#define RCC_SPI4CFGR_SPI4LPEN BIT(2) + +/* RCC_SPI5CFGR register fields */ +#define RCC_SPI5CFGR_SPI5RST BIT(0) +#define RCC_SPI5CFGR_SPI5EN BIT(1) +#define RCC_SPI5CFGR_SPI5LPEN BIT(2) + +/* RCC_SPI6CFGR register fields */ +#define RCC_SPI6CFGR_SPI6RST BIT(0) +#define RCC_SPI6CFGR_SPI6EN BIT(1) +#define RCC_SPI6CFGR_SPI6LPEN BIT(2) + +/* RCC_SPI7CFGR register fields */ +#define RCC_SPI7CFGR_SPI7RST BIT(0) +#define RCC_SPI7CFGR_SPI7EN BIT(1) +#define RCC_SPI7CFGR_SPI7LPEN BIT(2) + +/* RCC_SPI8CFGR register fields */ +#define RCC_SPI8CFGR_SPI8RST BIT(0) +#define RCC_SPI8CFGR_SPI8EN BIT(1) +#define RCC_SPI8CFGR_SPI8LPEN BIT(2) +#define RCC_SPI8CFGR_SPI8AMEN BIT(3) + +/* RCC_SPIxCFGR register fields */ +#define RCC_SPIxCFGR_SPIxRST BIT(0) +#define RCC_SPIxCFGR_SPIxEN BIT(1) +#define RCC_SPIxCFGR_SPIxLPEN BIT(2) +#define RCC_SPIxCFGR_SPIxAMEN BIT(3) + +/* RCC_SPDIFRXCFGR register fields */ +#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) +#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) +#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) + +/* RCC_USART1CFGR register fields */ +#define RCC_USART1CFGR_USART1RST BIT(0) +#define RCC_USART1CFGR_USART1EN BIT(1) +#define RCC_USART1CFGR_USART1LPEN BIT(2) + +/* RCC_USART2CFGR register fields */ +#define RCC_USART2CFGR_USART2RST BIT(0) +#define RCC_USART2CFGR_USART2EN BIT(1) +#define RCC_USART2CFGR_USART2LPEN BIT(2) + +/* RCC_USART3CFGR register fields */ +#define RCC_USART3CFGR_USART3RST BIT(0) +#define RCC_USART3CFGR_USART3EN BIT(1) +#define RCC_USART3CFGR_USART3LPEN BIT(2) + +/* RCC_UART4CFGR register fields */ +#define RCC_UART4CFGR_UART4RST BIT(0) +#define RCC_UART4CFGR_UART4EN BIT(1) +#define RCC_UART4CFGR_UART4LPEN BIT(2) + +/* RCC_UART5CFGR register fields */ +#define RCC_UART5CFGR_UART5RST BIT(0) +#define RCC_UART5CFGR_UART5EN BIT(1) +#define RCC_UART5CFGR_UART5LPEN BIT(2) + +/* RCC_USART6CFGR register fields */ +#define RCC_USART6CFGR_USART6RST BIT(0) +#define RCC_USART6CFGR_USART6EN BIT(1) +#define RCC_USART6CFGR_USART6LPEN BIT(2) + +/* RCC_UART7CFGR register fields */ +#define RCC_UART7CFGR_UART7RST BIT(0) +#define RCC_UART7CFGR_UART7EN BIT(1) +#define RCC_UART7CFGR_UART7LPEN BIT(2) + +/* RCC_UART8CFGR register fields */ +#define RCC_UART8CFGR_UART8RST BIT(0) +#define RCC_UART8CFGR_UART8EN BIT(1) +#define RCC_UART8CFGR_UART8LPEN BIT(2) + +/* RCC_UART9CFGR register fields */ +#define RCC_UART9CFGR_UART9RST BIT(0) +#define RCC_UART9CFGR_UART9EN BIT(1) +#define RCC_UART9CFGR_UART9LPEN BIT(2) + +/* RCC_USARTxCFGR register fields */ +#define RCC_USARTxCFGR_USARTxRST BIT(0) +#define RCC_USARTxCFGR_USARTxEN BIT(1) +#define RCC_USARTxCFGR_USARTxLPEN BIT(2) + +/* RCC_UARTxCFGR register fields */ +#define RCC_UARTxCFGR_UARTxRST BIT(0) +#define RCC_UARTxCFGR_UARTxEN BIT(1) +#define RCC_UARTxCFGR_UARTxLPEN BIT(2) + +/* RCC_LPUART1CFGR register fields */ +#define RCC_LPUART1CFGR_LPUART1RST BIT(0) +#define RCC_LPUART1CFGR_LPUART1EN BIT(1) +#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) +#define RCC_LPUART1CFGR_LPUART1AMEN BIT(3) + +/* RCC_I2C1CFGR register fields */ +#define RCC_I2C1CFGR_I2C1RST BIT(0) +#define RCC_I2C1CFGR_I2C1EN BIT(1) +#define RCC_I2C1CFGR_I2C1LPEN BIT(2) + +/* RCC_I2C2CFGR register fields */ +#define RCC_I2C2CFGR_I2C2RST BIT(0) +#define RCC_I2C2CFGR_I2C2EN BIT(1) +#define RCC_I2C2CFGR_I2C2LPEN BIT(2) + +/* RCC_I2C3CFGR register fields */ +#define RCC_I2C3CFGR_I2C3RST BIT(0) +#define RCC_I2C3CFGR_I2C3EN BIT(1) +#define RCC_I2C3CFGR_I2C3LPEN BIT(2) + +/* RCC_I2C4CFGR register fields */ +#define RCC_I2C4CFGR_I2C4RST BIT(0) +#define RCC_I2C4CFGR_I2C4EN BIT(1) +#define RCC_I2C4CFGR_I2C4LPEN BIT(2) + +/* RCC_I2C5CFGR register fields */ +#define RCC_I2C5CFGR_I2C5RST BIT(0) +#define RCC_I2C5CFGR_I2C5EN BIT(1) +#define RCC_I2C5CFGR_I2C5LPEN BIT(2) + +/* RCC_I2C6CFGR register fields */ +#define RCC_I2C6CFGR_I2C6RST BIT(0) +#define RCC_I2C6CFGR_I2C6EN BIT(1) +#define RCC_I2C6CFGR_I2C6LPEN BIT(2) + +/* RCC_I2C7CFGR register fields */ +#define RCC_I2C7CFGR_I2C7RST BIT(0) +#define RCC_I2C7CFGR_I2C7EN BIT(1) +#define RCC_I2C7CFGR_I2C7LPEN BIT(2) + +/* RCC_I2C8CFGR register fields */ +#define RCC_I2C8CFGR_I2C8RST BIT(0) +#define RCC_I2C8CFGR_I2C8EN BIT(1) +#define RCC_I2C8CFGR_I2C8LPEN BIT(2) +#define RCC_I2C8CFGR_I2C8AMEN BIT(3) + +/* RCC_I2CxCFGR register fields */ +#define RCC_I2CxCFGR_I2CxRST BIT(0) +#define RCC_I2CxCFGR_I2CxEN BIT(1) +#define RCC_I2CxCFGR_I2CxLPEN BIT(2) +#define RCC_I2CxCFGR_I2CxAMEN BIT(3) + +/* RCC_SAI1CFGR register fields */ +#define RCC_SAI1CFGR_SAI1RST BIT(0) +#define RCC_SAI1CFGR_SAI1EN BIT(1) +#define RCC_SAI1CFGR_SAI1LPEN BIT(2) + +/* RCC_SAI2CFGR register fields */ +#define RCC_SAI2CFGR_SAI2RST BIT(0) +#define RCC_SAI2CFGR_SAI2EN BIT(1) +#define RCC_SAI2CFGR_SAI2LPEN BIT(2) + +/* RCC_SAI3CFGR register fields */ +#define RCC_SAI3CFGR_SAI3RST BIT(0) +#define RCC_SAI3CFGR_SAI3EN BIT(1) +#define RCC_SAI3CFGR_SAI3LPEN BIT(2) + +/* RCC_SAI4CFGR register fields */ +#define RCC_SAI4CFGR_SAI4RST BIT(0) +#define RCC_SAI4CFGR_SAI4EN BIT(1) +#define RCC_SAI4CFGR_SAI4LPEN BIT(2) + +/* RCC_SAIxCFGR register fields */ +#define RCC_SAIxCFGR_SAIxRST BIT(0) +#define RCC_SAIxCFGR_SAIxEN BIT(1) +#define RCC_SAIxCFGR_SAIxLPEN BIT(2) + +/* RCC_MDF1CFGR register fields */ +#define RCC_MDF1CFGR_MDF1RST BIT(0) +#define RCC_MDF1CFGR_MDF1EN BIT(1) +#define RCC_MDF1CFGR_MDF1LPEN BIT(2) + +/* RCC_ADF1CFGR register fields */ +#define RCC_ADF1CFGR_ADF1RST BIT(0) +#define RCC_ADF1CFGR_ADF1EN BIT(1) +#define RCC_ADF1CFGR_ADF1LPEN BIT(2) +#define RCC_ADF1CFGR_ADF1AMEN BIT(3) + +/* RCC_FDCANCFGR register fields */ +#define RCC_FDCANCFGR_FDCANRST BIT(0) +#define RCC_FDCANCFGR_FDCANEN BIT(1) +#define RCC_FDCANCFGR_FDCANLPEN BIT(2) + +/* RCC_HDPCFGR register fields */ +#define RCC_HDPCFGR_HDPRST BIT(0) +#define RCC_HDPCFGR_HDPEN BIT(1) + +/* RCC_ADC12CFGR register fields */ +#define RCC_ADC12CFGR_ADC12RST BIT(0) +#define RCC_ADC12CFGR_ADC12EN BIT(1) +#define RCC_ADC12CFGR_ADC12LPEN BIT(2) +#define RCC_ADC12CFGR_ADC12KERSEL BIT(12) + +/* RCC_ADC3CFGR register fields */ +#define RCC_ADC3CFGR_ADC3RST BIT(0) +#define RCC_ADC3CFGR_ADC3EN BIT(1) +#define RCC_ADC3CFGR_ADC3LPEN BIT(2) +#define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12) +#define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12 + +/* RCC_ETH1CFGR register fields */ +#define RCC_ETH1CFGR_ETH1RST BIT(0) +#define RCC_ETH1CFGR_ETH1MACEN BIT(1) +#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) +#define RCC_ETH1CFGR_ETH1STPEN BIT(4) +#define RCC_ETH1CFGR_ETH1EN BIT(5) +#define RCC_ETH1CFGR_ETH1LPEN BIT(6) +#define RCC_ETH1CFGR_ETH1TXEN BIT(8) +#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) +#define RCC_ETH1CFGR_ETH1RXEN BIT(10) +#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) + +/* RCC_ETH2CFGR register fields */ +#define RCC_ETH2CFGR_ETH2RST BIT(0) +#define RCC_ETH2CFGR_ETH2MACEN BIT(1) +#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) +#define RCC_ETH2CFGR_ETH2STPEN BIT(4) +#define RCC_ETH2CFGR_ETH2EN BIT(5) +#define RCC_ETH2CFGR_ETH2LPEN BIT(6) +#define RCC_ETH2CFGR_ETH2TXEN BIT(8) +#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) +#define RCC_ETH2CFGR_ETH2RXEN BIT(10) +#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) + +/* RCC_ETHxCFGR register fields */ +#define RCC_ETHxCFGR_ETHxRST BIT(0) +#define RCC_ETHxCFGR_ETHxMACEN BIT(1) +#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2) +#define RCC_ETHxCFGR_ETHxSTPEN BIT(4) +#define RCC_ETHxCFGR_ETHxEN BIT(5) +#define RCC_ETHxCFGR_ETHxLPEN BIT(6) +#define RCC_ETHxCFGR_ETHxTXEN BIT(8) +#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9) +#define RCC_ETHxCFGR_ETHxRXEN BIT(10) +#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11) + +/* RCC_USB2CFGR register fields */ +#define RCC_USB2CFGR_USB2RST BIT(0) +#define RCC_USB2CFGR_USB2EN BIT(1) +#define RCC_USB2CFGR_USB2LPEN BIT(2) +#define RCC_USB2CFGR_USB2STPEN BIT(4) + +/* RCC_USB2PHY1CFGR register fields */ +#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB2PHY2CFGR register fields */ +#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) +#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) +#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) +#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4) +#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) + +/* RCC_USB2PHYxCFGR register fields */ +#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB3DRDCFGR register fields */ +#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0) +#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1) +#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2) +#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4) + +/* RCC_USB3PCIEPHYCFGR register fields */ +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15) + +/* RCC_PCIECFGR register fields */ +#define RCC_PCIECFGR_PCIERST BIT(0) +#define RCC_PCIECFGR_PCIEEN BIT(1) +#define RCC_PCIECFGR_PCIELPEN BIT(2) +#define RCC_PCIECFGR_PCIESTPEN BIT(4) + +/* RCC_USBTCCFGR register fields */ +#define RCC_USBTCCFGR_USBTCRST BIT(0) +#define RCC_USBTCCFGR_USBTCEN BIT(1) +#define RCC_USBTCCFGR_USBTCLPEN BIT(2) + +/* RCC_ETHSWCFGR register fields */ +#define RCC_ETHSWCFGR_ETHSWRST BIT(0) +#define RCC_ETHSWCFGR_ETHSWMACEN BIT(1) +#define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2) +#define RCC_ETHSWCFGR_ETHSWEN BIT(5) +#define RCC_ETHSWCFGR_ETHSWLPEN BIT(6) +#define RCC_ETHSWCFGR_ETHSWREFEN BIT(21) +#define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22) + +/* RCC_ETHSWACMCFGR register fields */ +#define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1) +#define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2) + +/* RCC_ETHSWACMMSGCFGR register fields */ +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1) +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2) + +/* RCC_STGENCFGR register fields */ +#define RCC_STGENCFGR_STGENEN BIT(1) +#define RCC_STGENCFGR_STGENLPEN BIT(2) +#define RCC_STGENCFGR_STGENSTPEN BIT(4) + +/* RCC_SDMMC1CFGR register fields */ +#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) +#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) +#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) + +/* RCC_SDMMC2CFGR register fields */ +#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) +#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) +#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) +#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) + +/* RCC_SDMMC3CFGR register fields */ +#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) +#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) +#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) +#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) + +/* RCC_SDMMCxCFGR register fields */ +#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0) +#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1) +#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16) + +/* RCC_GPUCFGR register fields */ +#define RCC_GPUCFGR_GPURST BIT(0) +#define RCC_GPUCFGR_GPUEN BIT(1) +#define RCC_GPUCFGR_GPULPEN BIT(2) + +/* RCC_LTDCCFGR register fields */ +#define RCC_LTDCCFGR_LTDCRST BIT(0) +#define RCC_LTDCCFGR_LTDCEN BIT(1) +#define RCC_LTDCCFGR_LTDCLPEN BIT(2) + +/* RCC_DSICFGR register fields */ +#define RCC_DSICFGR_DSIRST BIT(0) +#define RCC_DSICFGR_DSIEN BIT(1) +#define RCC_DSICFGR_DSILPEN BIT(2) +#define RCC_DSICFGR_DSIBLSEL BIT(12) +#define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15) + +/* RCC_LVDSCFGR register fields */ +#define RCC_LVDSCFGR_LVDSRST BIT(0) +#define RCC_LVDSCFGR_LVDSEN BIT(1) +#define RCC_LVDSCFGR_LVDSLPEN BIT(2) +#define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15) + +/* RCC_CSI2CFGR register fields */ +#define RCC_CSI2CFGR_CSI2RST BIT(0) +#define RCC_CSI2CFGR_CSI2EN BIT(1) +#define RCC_CSI2CFGR_CSI2LPEN BIT(2) + +/* RCC_DCMIPPCFGR register fields */ +#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) +#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) +#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) + +/* RCC_CCICFGR register fields */ +#define RCC_CCICFGR_CCIRST BIT(0) +#define RCC_CCICFGR_CCIEN BIT(1) +#define RCC_CCICFGR_CCILPEN BIT(2) + +/* RCC_VDECCFGR register fields */ +#define RCC_VDECCFGR_VDECRST BIT(0) +#define RCC_VDECCFGR_VDECEN BIT(1) +#define RCC_VDECCFGR_VDECLPEN BIT(2) + +/* RCC_VENCCFGR register fields */ +#define RCC_VENCCFGR_VENCRST BIT(0) +#define RCC_VENCCFGR_VENCEN BIT(1) +#define RCC_VENCCFGR_VENCLPEN BIT(2) + +/* RCC_RNGCFGR register fields */ +#define RCC_RNGCFGR_RNGRST BIT(0) +#define RCC_RNGCFGR_RNGEN BIT(1) +#define RCC_RNGCFGR_RNGLPEN BIT(2) + +/* RCC_PKACFGR register fields */ +#define RCC_PKACFGR_PKARST BIT(0) +#define RCC_PKACFGR_PKAEN BIT(1) +#define RCC_PKACFGR_PKALPEN BIT(2) + +/* RCC_SAESCFGR register fields */ +#define RCC_SAESCFGR_SAESRST BIT(0) +#define RCC_SAESCFGR_SAESEN BIT(1) +#define RCC_SAESCFGR_SAESLPEN BIT(2) + +/* RCC_HASHCFGR register fields */ +#define RCC_HASHCFGR_HASHRST BIT(0) +#define RCC_HASHCFGR_HASHEN BIT(1) +#define RCC_HASHCFGR_HASHLPEN BIT(2) + +/* RCC_CRYP1CFGR register fields */ +#define RCC_CRYP1CFGR_CRYP1RST BIT(0) +#define RCC_CRYP1CFGR_CRYP1EN BIT(1) +#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) + +/* RCC_CRYP2CFGR register fields */ +#define RCC_CRYP2CFGR_CRYP2RST BIT(0) +#define RCC_CRYP2CFGR_CRYP2EN BIT(1) +#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) + +/* RCC_CRYPxCFGR register fields */ +#define RCC_CRYPxCFGR_CRYPxRST BIT(0) +#define RCC_CRYPxCFGR_CRYPxEN BIT(1) +#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2) + +/* RCC_IWDG1CFGR register fields */ +#define RCC_IWDG1CFGR_IWDG1EN BIT(1) +#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) + +/* RCC_IWDG2CFGR register fields */ +#define RCC_IWDG2CFGR_IWDG2EN BIT(1) +#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) + +/* RCC_IWDG3CFGR register fields */ +#define RCC_IWDG3CFGR_IWDG3EN BIT(1) +#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) + +/* RCC_IWDG4CFGR register fields */ +#define RCC_IWDG4CFGR_IWDG4EN BIT(1) +#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) + +/* RCC_IWDGxCFGR register fields */ +#define RCC_IWDGxCFGR_IWDGxEN BIT(1) +#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2) + +/* RCC_IWDG5CFGR register fields */ +#define RCC_IWDG5CFGR_IWDG5EN BIT(1) +#define RCC_IWDG5CFGR_IWDG5LPEN BIT(2) +#define RCC_IWDG5CFGR_IWDG5AMEN BIT(3) + +/* RCC_WWDG1CFGR register fields */ +#define RCC_WWDG1CFGR_WWDG1RST BIT(0) +#define RCC_WWDG1CFGR_WWDG1EN BIT(1) +#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) + +/* RCC_WWDG2CFGR register fields */ +#define RCC_WWDG2CFGR_WWDG2RST BIT(0) +#define RCC_WWDG2CFGR_WWDG2EN BIT(1) +#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2) +#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3) + +/* RCC_BUSPERFMCFGR register fields */ +#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0) +#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1) +#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2) + +/* RCC_VREFCFGR register fields */ +#define RCC_VREFCFGR_VREFRST BIT(0) +#define RCC_VREFCFGR_VREFEN BIT(1) +#define RCC_VREFCFGR_VREFLPEN BIT(2) + +/* RCC_TMPSENSCFGR register fields */ +#define RCC_TMPSENSCFGR_TMPSENSRST BIT(0) +#define RCC_TMPSENSCFGR_TMPSENSEN BIT(1) +#define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12 + +/* RCC_CRCCFGR register fields */ +#define RCC_CRCCFGR_CRCRST BIT(0) +#define RCC_CRCCFGR_CRCEN BIT(1) +#define RCC_CRCCFGR_CRCLPEN BIT(2) + +/* RCC_SERCCFGR register fields */ +#define RCC_SERCCFGR_SERCRST BIT(0) +#define RCC_SERCCFGR_SERCEN BIT(1) +#define RCC_SERCCFGR_SERCLPEN BIT(2) + +/* RCC_OSPIIOMCFGR register fields */ +#define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0) +#define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1) +#define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2) + +/* RCC_GICV2MCFGR register fields */ +#define RCC_GICV2MCFGR_GICV2MEN BIT(1) +#define RCC_GICV2MCFGR_GICV2MLPEN BIT(2) + +/* RCC_I3C1CFGR register fields */ +#define RCC_I3C1CFGR_I3C1RST BIT(0) +#define RCC_I3C1CFGR_I3C1EN BIT(1) +#define RCC_I3C1CFGR_I3C1LPEN BIT(2) + +/* RCC_I3C2CFGR register fields */ +#define RCC_I3C2CFGR_I3C2RST BIT(0) +#define RCC_I3C2CFGR_I3C2EN BIT(1) +#define RCC_I3C2CFGR_I3C2LPEN BIT(2) + +/* RCC_I3C3CFGR register fields */ +#define RCC_I3C3CFGR_I3C3RST BIT(0) +#define RCC_I3C3CFGR_I3C3EN BIT(1) +#define RCC_I3C3CFGR_I3C3LPEN BIT(2) + +/* RCC_I3C4CFGR register fields */ +#define RCC_I3C4CFGR_I3C4RST BIT(0) +#define RCC_I3C4CFGR_I3C4EN BIT(1) +#define RCC_I3C4CFGR_I3C4LPEN BIT(2) +#define RCC_I3C4CFGR_I3C4AMEN BIT(3) + +/* RCC_I3CxCFGR register fields */ +#define RCC_I3CxCFGR_I3CxRST BIT(0) +#define RCC_I3CxCFGR_I3CxEN BIT(1) +#define RCC_I3CxCFGR_I3CxLPEN BIT(2) +#define RCC_I3CxCFGR_I3CxAMEN BIT(3) + +/* RCC_MUXSELCFGR register fields */ +#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0) +#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0 +#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4) +#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4 +#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8) +#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8 +#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12) +#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12 +#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16) +#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16 +#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) +#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20 +#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) +#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24 +#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28) +#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28 + +/* RCC_XBAR0CFGR register fields */ +#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 +#define RCC_XBAR0CFGR_XBAR0EN BIT(6) +#define RCC_XBAR0CFGR_XBAR0STS BIT(7) + +/* RCC_XBAR1CFGR register fields */ +#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0 +#define RCC_XBAR1CFGR_XBAR1EN BIT(6) +#define RCC_XBAR1CFGR_XBAR1STS BIT(7) + +/* RCC_XBAR2CFGR register fields */ +#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0 +#define RCC_XBAR2CFGR_XBAR2EN BIT(6) +#define RCC_XBAR2CFGR_XBAR2STS BIT(7) + +/* RCC_XBAR3CFGR register fields */ +#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0 +#define RCC_XBAR3CFGR_XBAR3EN BIT(6) +#define RCC_XBAR3CFGR_XBAR3STS BIT(7) + +/* RCC_XBAR4CFGR register fields */ +#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0 +#define RCC_XBAR4CFGR_XBAR4EN BIT(6) +#define RCC_XBAR4CFGR_XBAR4STS BIT(7) + +/* RCC_XBAR5CFGR register fields */ +#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0 +#define RCC_XBAR5CFGR_XBAR5EN BIT(6) +#define RCC_XBAR5CFGR_XBAR5STS BIT(7) + +/* RCC_XBAR6CFGR register fields */ +#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0 +#define RCC_XBAR6CFGR_XBAR6EN BIT(6) +#define RCC_XBAR6CFGR_XBAR6STS BIT(7) + +/* RCC_XBAR7CFGR register fields */ +#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0 +#define RCC_XBAR7CFGR_XBAR7EN BIT(6) +#define RCC_XBAR7CFGR_XBAR7STS BIT(7) + +/* RCC_XBAR8CFGR register fields */ +#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0 +#define RCC_XBAR8CFGR_XBAR8EN BIT(6) +#define RCC_XBAR8CFGR_XBAR8STS BIT(7) + +/* RCC_XBAR9CFGR register fields */ +#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0 +#define RCC_XBAR9CFGR_XBAR9EN BIT(6) +#define RCC_XBAR9CFGR_XBAR9STS BIT(7) + +/* RCC_XBAR10CFGR register fields */ +#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0 +#define RCC_XBAR10CFGR_XBAR10EN BIT(6) +#define RCC_XBAR10CFGR_XBAR10STS BIT(7) + +/* RCC_XBAR11CFGR register fields */ +#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0 +#define RCC_XBAR11CFGR_XBAR11EN BIT(6) +#define RCC_XBAR11CFGR_XBAR11STS BIT(7) + +/* RCC_XBAR12CFGR register fields */ +#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0 +#define RCC_XBAR12CFGR_XBAR12EN BIT(6) +#define RCC_XBAR12CFGR_XBAR12STS BIT(7) + +/* RCC_XBAR13CFGR register fields */ +#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0 +#define RCC_XBAR13CFGR_XBAR13EN BIT(6) +#define RCC_XBAR13CFGR_XBAR13STS BIT(7) + +/* RCC_XBAR14CFGR register fields */ +#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0 +#define RCC_XBAR14CFGR_XBAR14EN BIT(6) +#define RCC_XBAR14CFGR_XBAR14STS BIT(7) + +/* RCC_XBAR15CFGR register fields */ +#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0 +#define RCC_XBAR15CFGR_XBAR15EN BIT(6) +#define RCC_XBAR15CFGR_XBAR15STS BIT(7) + +/* RCC_XBAR16CFGR register fields */ +#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0 +#define RCC_XBAR16CFGR_XBAR16EN BIT(6) +#define RCC_XBAR16CFGR_XBAR16STS BIT(7) + +/* RCC_XBAR17CFGR register fields */ +#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0 +#define RCC_XBAR17CFGR_XBAR17EN BIT(6) +#define RCC_XBAR17CFGR_XBAR17STS BIT(7) + +/* RCC_XBAR18CFGR register fields */ +#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0 +#define RCC_XBAR18CFGR_XBAR18EN BIT(6) +#define RCC_XBAR18CFGR_XBAR18STS BIT(7) + +/* RCC_XBAR19CFGR register fields */ +#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0 +#define RCC_XBAR19CFGR_XBAR19EN BIT(6) +#define RCC_XBAR19CFGR_XBAR19STS BIT(7) + +/* RCC_XBAR20CFGR register fields */ +#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0 +#define RCC_XBAR20CFGR_XBAR20EN BIT(6) +#define RCC_XBAR20CFGR_XBAR20STS BIT(7) + +/* RCC_XBAR21CFGR register fields */ +#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0 +#define RCC_XBAR21CFGR_XBAR21EN BIT(6) +#define RCC_XBAR21CFGR_XBAR21STS BIT(7) + +/* RCC_XBAR22CFGR register fields */ +#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0 +#define RCC_XBAR22CFGR_XBAR22EN BIT(6) +#define RCC_XBAR22CFGR_XBAR22STS BIT(7) + +/* RCC_XBAR23CFGR register fields */ +#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0 +#define RCC_XBAR23CFGR_XBAR23EN BIT(6) +#define RCC_XBAR23CFGR_XBAR23STS BIT(7) + +/* RCC_XBAR24CFGR register fields */ +#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0 +#define RCC_XBAR24CFGR_XBAR24EN BIT(6) +#define RCC_XBAR24CFGR_XBAR24STS BIT(7) + +/* RCC_XBAR25CFGR register fields */ +#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0 +#define RCC_XBAR25CFGR_XBAR25EN BIT(6) +#define RCC_XBAR25CFGR_XBAR25STS BIT(7) + +/* RCC_XBAR26CFGR register fields */ +#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0 +#define RCC_XBAR26CFGR_XBAR26EN BIT(6) +#define RCC_XBAR26CFGR_XBAR26STS BIT(7) + +/* RCC_XBAR27CFGR register fields */ +#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0 +#define RCC_XBAR27CFGR_XBAR27EN BIT(6) +#define RCC_XBAR27CFGR_XBAR27STS BIT(7) + +/* RCC_XBAR28CFGR register fields */ +#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0 +#define RCC_XBAR28CFGR_XBAR28EN BIT(6) +#define RCC_XBAR28CFGR_XBAR28STS BIT(7) + +/* RCC_XBAR29CFGR register fields */ +#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0 +#define RCC_XBAR29CFGR_XBAR29EN BIT(6) +#define RCC_XBAR29CFGR_XBAR29STS BIT(7) + +/* RCC_XBAR30CFGR register fields */ +#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0 +#define RCC_XBAR30CFGR_XBAR30EN BIT(6) +#define RCC_XBAR30CFGR_XBAR30STS BIT(7) + +/* RCC_XBAR31CFGR register fields */ +#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0 +#define RCC_XBAR31CFGR_XBAR31EN BIT(6) +#define RCC_XBAR31CFGR_XBAR31STS BIT(7) + +/* RCC_XBAR32CFGR register fields */ +#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0 +#define RCC_XBAR32CFGR_XBAR32EN BIT(6) +#define RCC_XBAR32CFGR_XBAR32STS BIT(7) + +/* RCC_XBAR33CFGR register fields */ +#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0 +#define RCC_XBAR33CFGR_XBAR33EN BIT(6) +#define RCC_XBAR33CFGR_XBAR33STS BIT(7) + +/* RCC_XBAR34CFGR register fields */ +#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0 +#define RCC_XBAR34CFGR_XBAR34EN BIT(6) +#define RCC_XBAR34CFGR_XBAR34STS BIT(7) + +/* RCC_XBAR35CFGR register fields */ +#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0 +#define RCC_XBAR35CFGR_XBAR35EN BIT(6) +#define RCC_XBAR35CFGR_XBAR35STS BIT(7) + +/* RCC_XBAR36CFGR register fields */ +#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0 +#define RCC_XBAR36CFGR_XBAR36EN BIT(6) +#define RCC_XBAR36CFGR_XBAR36STS BIT(7) + +/* RCC_XBAR37CFGR register fields */ +#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0 +#define RCC_XBAR37CFGR_XBAR37EN BIT(6) +#define RCC_XBAR37CFGR_XBAR37STS BIT(7) + +/* RCC_XBAR38CFGR register fields */ +#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0 +#define RCC_XBAR38CFGR_XBAR38EN BIT(6) +#define RCC_XBAR38CFGR_XBAR38STS BIT(7) + +/* RCC_XBAR39CFGR register fields */ +#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0 +#define RCC_XBAR39CFGR_XBAR39EN BIT(6) +#define RCC_XBAR39CFGR_XBAR39STS BIT(7) + +/* RCC_XBAR40CFGR register fields */ +#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0 +#define RCC_XBAR40CFGR_XBAR40EN BIT(6) +#define RCC_XBAR40CFGR_XBAR40STS BIT(7) + +/* RCC_XBAR41CFGR register fields */ +#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0 +#define RCC_XBAR41CFGR_XBAR41EN BIT(6) +#define RCC_XBAR41CFGR_XBAR41STS BIT(7) + +/* RCC_XBAR42CFGR register fields */ +#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0 +#define RCC_XBAR42CFGR_XBAR42EN BIT(6) +#define RCC_XBAR42CFGR_XBAR42STS BIT(7) + +/* RCC_XBAR43CFGR register fields */ +#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0 +#define RCC_XBAR43CFGR_XBAR43EN BIT(6) +#define RCC_XBAR43CFGR_XBAR43STS BIT(7) + +/* RCC_XBAR44CFGR register fields */ +#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0 +#define RCC_XBAR44CFGR_XBAR44EN BIT(6) +#define RCC_XBAR44CFGR_XBAR44STS BIT(7) + +/* RCC_XBAR45CFGR register fields */ +#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0 +#define RCC_XBAR45CFGR_XBAR45EN BIT(6) +#define RCC_XBAR45CFGR_XBAR45STS BIT(7) + +/* RCC_XBAR46CFGR register fields */ +#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0 +#define RCC_XBAR46CFGR_XBAR46EN BIT(6) +#define RCC_XBAR46CFGR_XBAR46STS BIT(7) + +/* RCC_XBAR47CFGR register fields */ +#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0 +#define RCC_XBAR47CFGR_XBAR47EN BIT(6) +#define RCC_XBAR47CFGR_XBAR47STS BIT(7) + +/* RCC_XBAR48CFGR register fields */ +#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0 +#define RCC_XBAR48CFGR_XBAR48EN BIT(6) +#define RCC_XBAR48CFGR_XBAR48STS BIT(7) + +/* RCC_XBAR49CFGR register fields */ +#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0 +#define RCC_XBAR49CFGR_XBAR49EN BIT(6) +#define RCC_XBAR49CFGR_XBAR49STS BIT(7) + +/* RCC_XBAR50CFGR register fields */ +#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0 +#define RCC_XBAR50CFGR_XBAR50EN BIT(6) +#define RCC_XBAR50CFGR_XBAR50STS BIT(7) + +/* RCC_XBAR51CFGR register fields */ +#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0 +#define RCC_XBAR51CFGR_XBAR51EN BIT(6) +#define RCC_XBAR51CFGR_XBAR51STS BIT(7) + +/* RCC_XBAR52CFGR register fields */ +#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0 +#define RCC_XBAR52CFGR_XBAR52EN BIT(6) +#define RCC_XBAR52CFGR_XBAR52STS BIT(7) + +/* RCC_XBAR53CFGR register fields */ +#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0 +#define RCC_XBAR53CFGR_XBAR53EN BIT(6) +#define RCC_XBAR53CFGR_XBAR53STS BIT(7) + +/* RCC_XBAR54CFGR register fields */ +#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0 +#define RCC_XBAR54CFGR_XBAR54EN BIT(6) +#define RCC_XBAR54CFGR_XBAR54STS BIT(7) + +/* RCC_XBAR55CFGR register fields */ +#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0 +#define RCC_XBAR55CFGR_XBAR55EN BIT(6) +#define RCC_XBAR55CFGR_XBAR55STS BIT(7) + +/* RCC_XBAR56CFGR register fields */ +#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0 +#define RCC_XBAR56CFGR_XBAR56EN BIT(6) +#define RCC_XBAR56CFGR_XBAR56STS BIT(7) + +/* RCC_XBAR57CFGR register fields */ +#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0 +#define RCC_XBAR57CFGR_XBAR57EN BIT(6) +#define RCC_XBAR57CFGR_XBAR57STS BIT(7) + +/* RCC_XBAR58CFGR register fields */ +#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0 +#define RCC_XBAR58CFGR_XBAR58EN BIT(6) +#define RCC_XBAR58CFGR_XBAR58STS BIT(7) + +/* RCC_XBAR59CFGR register fields */ +#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0 +#define RCC_XBAR59CFGR_XBAR59EN BIT(6) +#define RCC_XBAR59CFGR_XBAR59STS BIT(7) + +/* RCC_XBAR60CFGR register fields */ +#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0 +#define RCC_XBAR60CFGR_XBAR60EN BIT(6) +#define RCC_XBAR60CFGR_XBAR60STS BIT(7) + +/* RCC_XBAR61CFGR register fields */ +#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0 +#define RCC_XBAR61CFGR_XBAR61EN BIT(6) +#define RCC_XBAR61CFGR_XBAR61STS BIT(7) + +/* RCC_XBAR62CFGR register fields */ +#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0 +#define RCC_XBAR62CFGR_XBAR62EN BIT(6) +#define RCC_XBAR62CFGR_XBAR62STS BIT(7) + +/* RCC_XBAR63CFGR register fields */ +#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0 +#define RCC_XBAR63CFGR_XBAR63EN BIT(6) +#define RCC_XBAR63CFGR_XBAR63STS BIT(7) + +/* RCC_XBARxCFGR register fields */ +#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0) +#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0 +#define RCC_XBARxCFGR_XBARxEN BIT(6) +#define RCC_XBARxCFGR_XBARxSTS BIT(7) + +/* RCC_PREDIV0CFGR register fields */ +#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) +#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 + +/* RCC_PREDIV1CFGR register fields */ +#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0) +#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0 + +/* RCC_PREDIV2CFGR register fields */ +#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0) +#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0 + +/* RCC_PREDIV3CFGR register fields */ +#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0) +#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0 + +/* RCC_PREDIV4CFGR register fields */ +#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0) +#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0 + +/* RCC_PREDIV5CFGR register fields */ +#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0) +#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0 + +/* RCC_PREDIV6CFGR register fields */ +#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0) +#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0 + +/* RCC_PREDIV7CFGR register fields */ +#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0) +#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0 + +/* RCC_PREDIV8CFGR register fields */ +#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0) +#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0 + +/* RCC_PREDIV9CFGR register fields */ +#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0) +#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0 + +/* RCC_PREDIV10CFGR register fields */ +#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0) +#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0 + +/* RCC_PREDIV11CFGR register fields */ +#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0) +#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0 + +/* RCC_PREDIV12CFGR register fields */ +#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0) +#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0 + +/* RCC_PREDIV13CFGR register fields */ +#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0) +#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0 + +/* RCC_PREDIV14CFGR register fields */ +#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0) +#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0 + +/* RCC_PREDIV15CFGR register fields */ +#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0) +#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0 + +/* RCC_PREDIV16CFGR register fields */ +#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0) +#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0 + +/* RCC_PREDIV17CFGR register fields */ +#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0) +#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0 + +/* RCC_PREDIV18CFGR register fields */ +#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0) +#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0 + +/* RCC_PREDIV19CFGR register fields */ +#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0) +#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0 + +/* RCC_PREDIV20CFGR register fields */ +#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0) +#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0 + +/* RCC_PREDIV21CFGR register fields */ +#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0) +#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0 + +/* RCC_PREDIV22CFGR register fields */ +#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0) +#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0 + +/* RCC_PREDIV23CFGR register fields */ +#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0) +#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0 + +/* RCC_PREDIV24CFGR register fields */ +#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0) +#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0 + +/* RCC_PREDIV25CFGR register fields */ +#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0) +#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0 + +/* RCC_PREDIV26CFGR register fields */ +#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0) +#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0 + +/* RCC_PREDIV27CFGR register fields */ +#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0) +#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0 + +/* RCC_PREDIV28CFGR register fields */ +#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0) +#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0 + +/* RCC_PREDIV29CFGR register fields */ +#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0) +#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0 + +/* RCC_PREDIV30CFGR register fields */ +#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0) +#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0 + +/* RCC_PREDIV31CFGR register fields */ +#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0) +#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0 + +/* RCC_PREDIV32CFGR register fields */ +#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0) +#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0 + +/* RCC_PREDIV33CFGR register fields */ +#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0) +#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0 + +/* RCC_PREDIV34CFGR register fields */ +#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0) +#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0 + +/* RCC_PREDIV35CFGR register fields */ +#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0) +#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0 + +/* RCC_PREDIV36CFGR register fields */ +#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0) +#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0 + +/* RCC_PREDIV37CFGR register fields */ +#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0) +#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0 + +/* RCC_PREDIV38CFGR register fields */ +#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0) +#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0 + +/* RCC_PREDIV39CFGR register fields */ +#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0) +#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0 + +/* RCC_PREDIV40CFGR register fields */ +#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0) +#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0 + +/* RCC_PREDIV41CFGR register fields */ +#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0) +#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0 + +/* RCC_PREDIV42CFGR register fields */ +#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0) +#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0 + +/* RCC_PREDIV43CFGR register fields */ +#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0) +#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0 + +/* RCC_PREDIV44CFGR register fields */ +#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0) +#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0 + +/* RCC_PREDIV45CFGR register fields */ +#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0) +#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0 + +/* RCC_PREDIV46CFGR register fields */ +#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0) +#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0 + +/* RCC_PREDIV47CFGR register fields */ +#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0) +#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0 + +/* RCC_PREDIV48CFGR register fields */ +#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0) +#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0 + +/* RCC_PREDIV49CFGR register fields */ +#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0) +#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0 + +/* RCC_PREDIV50CFGR register fields */ +#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0) +#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0 + +/* RCC_PREDIV51CFGR register fields */ +#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0) +#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0 + +/* RCC_PREDIV52CFGR register fields */ +#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0) +#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0 + +/* RCC_PREDIV53CFGR register fields */ +#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0) +#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0 + +/* RCC_PREDIV54CFGR register fields */ +#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0) +#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0 + +/* RCC_PREDIV55CFGR register fields */ +#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0) +#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0 + +/* RCC_PREDIV56CFGR register fields */ +#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0) +#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0 + +/* RCC_PREDIV57CFGR register fields */ +#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0) +#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0 + +/* RCC_PREDIV58CFGR register fields */ +#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0) +#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0 + +/* RCC_PREDIV59CFGR register fields */ +#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0) +#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0 + +/* RCC_PREDIV60CFGR register fields */ +#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0) +#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0 + +/* RCC_PREDIV61CFGR register fields */ +#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0) +#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0 + +/* RCC_PREDIV62CFGR register fields */ +#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0) +#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0 + +/* RCC_PREDIV63CFGR register fields */ +#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0) +#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0 + +/* RCC_PREDIVxCFGR register fields */ +#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0) +#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0 + +/* RCC_FINDIV0CFGR register fields */ +#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) +#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 +#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) + +/* RCC_FINDIV1CFGR register fields */ +#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0) +#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0 +#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6) + +/* RCC_FINDIV2CFGR register fields */ +#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0) +#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0 +#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6) + +/* RCC_FINDIV3CFGR register fields */ +#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0) +#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0 +#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6) + +/* RCC_FINDIV4CFGR register fields */ +#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0) +#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0 +#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6) + +/* RCC_FINDIV5CFGR register fields */ +#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0) +#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0 +#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6) + +/* RCC_FINDIV6CFGR register fields */ +#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0) +#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0 +#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6) + +/* RCC_FINDIV7CFGR register fields */ +#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0) +#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0 +#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6) + +/* RCC_FINDIV8CFGR register fields */ +#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0) +#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0 +#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6) + +/* RCC_FINDIV9CFGR register fields */ +#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0) +#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0 +#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6) + +/* RCC_FINDIV10CFGR register fields */ +#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0) +#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0 +#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6) + +/* RCC_FINDIV11CFGR register fields */ +#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0) +#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0 +#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6) + +/* RCC_FINDIV12CFGR register fields */ +#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0) +#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0 +#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6) + +/* RCC_FINDIV13CFGR register fields */ +#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0) +#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0 +#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6) + +/* RCC_FINDIV14CFGR register fields */ +#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0) +#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0 +#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6) + +/* RCC_FINDIV15CFGR register fields */ +#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0) +#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0 +#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6) + +/* RCC_FINDIV16CFGR register fields */ +#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0) +#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0 +#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6) + +/* RCC_FINDIV17CFGR register fields */ +#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0) +#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0 +#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6) + +/* RCC_FINDIV18CFGR register fields */ +#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0) +#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0 +#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6) + +/* RCC_FINDIV19CFGR register fields */ +#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0) +#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0 +#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6) + +/* RCC_FINDIV20CFGR register fields */ +#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0) +#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0 +#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6) + +/* RCC_FINDIV21CFGR register fields */ +#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0) +#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0 +#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6) + +/* RCC_FINDIV22CFGR register fields */ +#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0) +#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0 +#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6) + +/* RCC_FINDIV23CFGR register fields */ +#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0) +#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0 +#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6) + +/* RCC_FINDIV24CFGR register fields */ +#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0) +#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0 +#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6) + +/* RCC_FINDIV25CFGR register fields */ +#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0) +#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0 +#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6) + +/* RCC_FINDIV26CFGR register fields */ +#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0) +#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0 +#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6) + +/* RCC_FINDIV27CFGR register fields */ +#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0) +#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0 +#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6) + +/* RCC_FINDIV28CFGR register fields */ +#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0) +#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0 +#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6) + +/* RCC_FINDIV29CFGR register fields */ +#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0) +#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0 +#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6) + +/* RCC_FINDIV30CFGR register fields */ +#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0) +#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0 +#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6) + +/* RCC_FINDIV31CFGR register fields */ +#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0) +#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0 +#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6) + +/* RCC_FINDIV32CFGR register fields */ +#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0) +#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0 +#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6) + +/* RCC_FINDIV33CFGR register fields */ +#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0) +#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0 +#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6) + +/* RCC_FINDIV34CFGR register fields */ +#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0) +#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0 +#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6) + +/* RCC_FINDIV35CFGR register fields */ +#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0) +#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0 +#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6) + +/* RCC_FINDIV36CFGR register fields */ +#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0) +#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0 +#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6) + +/* RCC_FINDIV37CFGR register fields */ +#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0) +#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0 +#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6) + +/* RCC_FINDIV38CFGR register fields */ +#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0) +#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0 +#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6) + +/* RCC_FINDIV39CFGR register fields */ +#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0) +#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0 +#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6) + +/* RCC_FINDIV40CFGR register fields */ +#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0) +#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0 +#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6) + +/* RCC_FINDIV41CFGR register fields */ +#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0) +#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0 +#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6) + +/* RCC_FINDIV42CFGR register fields */ +#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0) +#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0 +#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6) + +/* RCC_FINDIV43CFGR register fields */ +#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0) +#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0 +#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6) + +/* RCC_FINDIV44CFGR register fields */ +#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0) +#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0 +#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6) + +/* RCC_FINDIV45CFGR register fields */ +#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0) +#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0 +#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6) + +/* RCC_FINDIV46CFGR register fields */ +#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0) +#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0 +#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6) + +/* RCC_FINDIV47CFGR register fields */ +#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0) +#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0 +#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6) + +/* RCC_FINDIV48CFGR register fields */ +#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0) +#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0 +#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6) + +/* RCC_FINDIV49CFGR register fields */ +#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0) +#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0 +#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6) + +/* RCC_FINDIV50CFGR register fields */ +#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0) +#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0 +#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6) + +/* RCC_FINDIV51CFGR register fields */ +#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0) +#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0 +#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6) + +/* RCC_FINDIV52CFGR register fields */ +#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0) +#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0 +#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6) + +/* RCC_FINDIV53CFGR register fields */ +#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0) +#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0 +#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6) + +/* RCC_FINDIV54CFGR register fields */ +#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0) +#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0 +#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6) + +/* RCC_FINDIV55CFGR register fields */ +#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0) +#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0 +#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6) + +/* RCC_FINDIV56CFGR register fields */ +#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0) +#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0 +#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6) + +/* RCC_FINDIV57CFGR register fields */ +#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0) +#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0 +#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6) + +/* RCC_FINDIV58CFGR register fields */ +#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0) +#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0 +#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6) + +/* RCC_FINDIV59CFGR register fields */ +#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0) +#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0 +#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6) + +/* RCC_FINDIV60CFGR register fields */ +#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0) +#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0 +#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6) + +/* RCC_FINDIV61CFGR register fields */ +#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0) +#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0 +#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6) + +/* RCC_FINDIV62CFGR register fields */ +#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0) +#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0 +#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6) + +/* RCC_FINDIV63CFGR register fields */ +#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0) +#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0 +#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6) + +/* RCC_FINDIVxCFGR register fields */ +#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0) +#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0 +#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6) + +/* RCC_FCALCOBS0CFGR register fields */ +#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) +#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) +#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) +#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) + +/* RCC_FCALCOBS1CFGR register fields */ +#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) +#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) + +/* RCC_FCALCREFCFGR register fields */ +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0 + +/* RCC_FCALCCR1 register fields */ +#define RCC_FCALCCR1_FCALCRUN BIT(0) + +/* RCC_FCALCCR2 register fields */ +#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) +#define RCC_FCALCCR2_FCALCMD_SHIFT 3 +#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) +#define RCC_FCALCCR2_FCALCTWC_SHIFT 11 +#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) +#define RCC_FCALCCR2_FCALCTYP_SHIFT 17 + +/* RCC_FCALCSR register fields */ +#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0) +#define RCC_FCALCSR_FVAL_SHIFT 0 +#define RCC_FCALCSR_FCALCSTS BIT(19) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_SSMODRST BIT(0) +#define RCC_PLL4CFGR1_PLLEN BIT(8) +#define RCC_PLL4CFGR1_PLLRDY BIT(24) +#define RCC_PLL4CFGR1_CKREFST BIT(28) + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL4CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL4CFGR3 register fields */ +#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL4CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL4CFGR3_DACEN BIT(25) +#define RCC_PLL4CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL4CFGR4 register fields */ +#define RCC_PLL4CFGR4_DSMEN BIT(8) +#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL4CFGR4_BYPASS BIT(10) + +/* RCC_PLL4CFGR5 register fields */ +#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL4CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL4CFGR6 register fields */ +#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL4CFGR7 register fields */ +#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL5CFGR1 register fields */ +#define RCC_PLL5CFGR1_SSMODRST BIT(0) +#define RCC_PLL5CFGR1_PLLEN BIT(8) +#define RCC_PLL5CFGR1_PLLRDY BIT(24) +#define RCC_PLL5CFGR1_CKREFST BIT(28) + +/* RCC_PLL5CFGR2 register fields */ +#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL5CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL5CFGR3 register fields */ +#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL5CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL5CFGR3_DACEN BIT(25) +#define RCC_PLL5CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL5CFGR4 register fields */ +#define RCC_PLL5CFGR4_DSMEN BIT(8) +#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL5CFGR4_BYPASS BIT(10) + +/* RCC_PLL5CFGR5 register fields */ +#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL5CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL5CFGR6 register fields */ +#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL5CFGR7 register fields */ +#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL6CFGR1 register fields */ +#define RCC_PLL6CFGR1_SSMODRST BIT(0) +#define RCC_PLL6CFGR1_PLLEN BIT(8) +#define RCC_PLL6CFGR1_PLLRDY BIT(24) +#define RCC_PLL6CFGR1_CKREFST BIT(28) + +/* RCC_PLL6CFGR2 register fields */ +#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL6CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL6CFGR3 register fields */ +#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL6CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL6CFGR3_DACEN BIT(25) +#define RCC_PLL6CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL6CFGR4 register fields */ +#define RCC_PLL6CFGR4_DSMEN BIT(8) +#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL6CFGR4_BYPASS BIT(10) + +/* RCC_PLL6CFGR5 register fields */ +#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL6CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL6CFGR6 register fields */ +#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL6CFGR7 register fields */ +#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL7CFGR1 register fields */ +#define RCC_PLL7CFGR1_SSMODRST BIT(0) +#define RCC_PLL7CFGR1_PLLEN BIT(8) +#define RCC_PLL7CFGR1_PLLRDY BIT(24) +#define RCC_PLL7CFGR1_CKREFST BIT(28) + +/* RCC_PLL7CFGR2 register fields */ +#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL7CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL7CFGR3 register fields */ +#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL7CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL7CFGR3_DACEN BIT(25) +#define RCC_PLL7CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL7CFGR4 register fields */ +#define RCC_PLL7CFGR4_DSMEN BIT(8) +#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL7CFGR4_BYPASS BIT(10) + +/* RCC_PLL7CFGR5 register fields */ +#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL7CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL7CFGR6 register fields */ +#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL7CFGR7 register fields */ +#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL8CFGR1 register fields */ +#define RCC_PLL8CFGR1_SSMODRST BIT(0) +#define RCC_PLL8CFGR1_PLLEN BIT(8) +#define RCC_PLL8CFGR1_PLLRDY BIT(24) +#define RCC_PLL8CFGR1_CKREFST BIT(28) + +/* RCC_PLL8CFGR2 register fields */ +#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL8CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL8CFGR3 register fields */ +#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL8CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL8CFGR3_DACEN BIT(25) +#define RCC_PLL8CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL8CFGR4 register fields */ +#define RCC_PLL8CFGR4_DSMEN BIT(8) +#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL8CFGR4_BYPASS BIT(10) + +/* RCC_PLL8CFGR5 register fields */ +#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL8CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL8CFGR6 register fields */ +#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL8CFGR7 register fields */ +#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +#endif /* STM32MP2_RCC_H */ diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h new file mode 100644 index 0000000..61286b2 --- /dev/null +++ b/include/drivers/st/stm32mp_clkfunc.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_CLKFUNC_H +#define STM32MP_CLKFUNC_H + +#include <stdbool.h> + +#include <libfdt.h> + +#include <platform_def.h> + +int fdt_osc_read_freq(const char *name, uint32_t *freq); +bool fdt_clk_read_bool(const char *node_label, const char *prop_name); +uint32_t fdt_clk_read_uint32_default(const char *node_label, + const char *prop_name, + uint32_t dflt_value); + +int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count, + uint32_t *array); +int fdt_rcc_subnode_offset(const char *name); +const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); +bool fdt_get_rcc_secure_state(void); + +int fdt_get_clock_id(int node); +unsigned long fdt_get_uart_clock_freq(uintptr_t instance); + +void stm32mp_stgen_config(unsigned long rate); +void stm32mp_stgen_restore_counter(unsigned long long value, + unsigned long long offset_in_ms); +unsigned long long stm32mp_stgen_get_counter(void); + +#endif /* STM32MP_CLKFUNC_H */ diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h new file mode 100644 index 0000000..4535e3c --- /dev/null +++ b/include/drivers/st/stm32mp_ddr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP_DDR_H +#define STM32MP_DDR_H + +#include <platform_def.h> + +enum stm32mp_ddr_base_type { + DDR_BASE, + DDRPHY_BASE, + NONE_BASE +}; + +enum stm32mp_ddr_reg_type { + REG_REG, + REG_TIMING, + REG_PERF, + REG_MAP, + REGPHY_REG, + REGPHY_TIMING, + REG_TYPE_NB +}; + +struct stm32mp_ddr_reg_desc { + const char *name; + uint16_t offset; /* Offset for base address */ + uint8_t par_offset; /* Offset for parameter array */ +}; + +struct stm32mp_ddr_reg_info { + const char *name; + const struct stm32mp_ddr_reg_desc *desc; + uint8_t size; + enum stm32mp_ddr_base_type base; +}; + +struct stm32mp_ddr_size { + uint64_t base; + uint64_t size; +}; + +struct stm32mp_ddr_priv { + struct stm32mp_ddr_size info; + struct stm32mp_ddrctl *ctl; + struct stm32mp_ddrphy *phy; + uintptr_t pwr; + uintptr_t rcc; +}; + +struct stm32mp_ddr_info { + const char *name; + uint32_t speed; /* in kHz */ + size_t size; /* Memory size in byte = col * row * width */ +}; + +#define TIMEOUT_US_1S 1000000U + +void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type, + const void *param, const struct stm32mp_ddr_reg_info *ddr_registers); +void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl); +void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl); +void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl); +int stm32mp_board_ddr_power_init(enum ddr_type ddr_type); + +#endif /* STM32MP_DDR_H */ diff --git a/include/drivers/st/stm32mp_ddr_test.h b/include/drivers/st/stm32mp_ddr_test.h new file mode 100644 index 0000000..cef5b48 --- /dev/null +++ b/include/drivers/st/stm32mp_ddr_test.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_DDR_TEST_H +#define STM32MP_DDR_TEST_H + +#include <stdint.h> + +uintptr_t stm32mp_ddr_test_rw_access(void); +uintptr_t stm32mp_ddr_test_data_bus(void); +uintptr_t stm32mp_ddr_test_addr_bus(size_t size); +size_t stm32mp_ddr_check_size(void); + +#endif /* STM32MP_DDR_TEST_H */ diff --git a/include/drivers/st/stm32mp_ddrctrl_regs.h b/include/drivers/st/stm32mp_ddrctrl_regs.h new file mode 100644 index 0000000..79de86b --- /dev/null +++ b/include/drivers/st/stm32mp_ddrctrl_regs.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + */ + +#ifndef STM32MP_DDRCTRL_REGS_H +#define STM32MP_DDRCTRL_REGS_H + +#include <cdefs.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +/* DDR Controller (DDRCTRL) registers */ +struct stm32mp_ddrctl { + uint32_t mstr ; /* 0x0 Master */ + uint32_t stat; /* 0x4 Operating Mode Status */ + uint8_t reserved008[0x10 - 0x8]; + uint32_t mrctrl0; /* 0x10 Control 0 */ + uint32_t mrctrl1; /* 0x14 Control 1 */ + uint32_t mrstat; /* 0x18 Status */ + uint32_t mrctrl2; /* 0x1c Control 2 */ + uint32_t derateen; /* 0x20 Temperature Derate Enable */ + uint32_t derateint; /* 0x24 Temperature Derate Interval */ + uint32_t reserved028; + uint32_t deratectl; /* 0x2c Temperature Derate Control */ + uint32_t pwrctl; /* 0x30 Low Power Control */ + uint32_t pwrtmg; /* 0x34 Low Power Timing */ + uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */ + uint8_t reserved03c[0x50 - 0x3c]; + uint32_t rfshctl0; /* 0x50 Refresh Control 0 */ + uint32_t rfshctl1; /* 0x54 Refresh Control 1 */ + uint32_t reserved058; /* 0x58 Refresh Control 2 */ + uint32_t reserved05C; + uint32_t rfshctl3; /* 0x60 Refresh Control 0 */ + uint32_t rfshtmg; /* 0x64 Refresh Timing */ + uint32_t rfshtmg1; /* 0x68 Refresh Timing 1 */ + uint8_t reserved06c[0xc0 - 0x6c]; + uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */ + uint32_t crcparctl1; /* 0xc4 CRC Parity Control1 */ + uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */ + uint32_t crcparstat; /* 0xcc CRC Parity Status */ + uint32_t init0; /* 0xd0 SDRAM Initialization 0 */ + uint32_t init1; /* 0xd4 SDRAM Initialization 1 */ + uint32_t init2; /* 0xd8 SDRAM Initialization 2 */ + uint32_t init3; /* 0xdc SDRAM Initialization 3 */ + uint32_t init4; /* 0xe0 SDRAM Initialization 4 */ + uint32_t init5; /* 0xe4 SDRAM Initialization 5 */ + uint32_t init6; /* 0xe8 SDRAM Initialization 6 */ + uint32_t init7; /* 0xec SDRAM Initialization 7 */ + uint32_t dimmctl; /* 0xf0 DIMM Control */ + uint32_t rankctl; /* 0xf4 Rank Control */ + uint8_t reserved0f4[0x100 - 0xf8]; + uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ + uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */ + uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */ + uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */ + uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */ + uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */ + uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */ + uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */ + uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */ + uint32_t dramtmg9; /* 0x124 SDRAM Timing 9 */ + uint32_t dramtmg10; /* 0x128 SDRAM Timing 10 */ + uint32_t dramtmg11; /* 0x12c SDRAM Timing 11 */ + uint32_t dramtmg12; /* 0x130 SDRAM Timing 12 */ + uint32_t dramtmg13; /* 0x134 SDRAM Timing 13 */ + uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */ + uint32_t dramtmg15; /* 0x13c SDRAM Timing 15 */ + uint8_t reserved140[0x180 - 0x140]; + uint32_t zqctl0; /* 0x180 ZQ Control 0 */ + uint32_t zqctl1; /* 0x184 ZQ Control 1 */ + uint32_t zqctl2; /* 0x188 ZQ Control 2 */ + uint32_t zqstat; /* 0x18c ZQ Status */ + uint32_t dfitmg0; /* 0x190 DFI Timing 0 */ + uint32_t dfitmg1; /* 0x194 DFI Timing 1 */ + uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */ + uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */ + uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */ + uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */ + uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */ + uint32_t reserved1ac; + uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */ + uint32_t dfitmg2; /* 0x1b4 DFI Timing 2 */ + uint32_t dfitmg3; /* 0x1b8 DFI Timing 3 */ + uint32_t dfistat; /* 0x1bc DFI Status */ + uint32_t dbictl; /* 0x1c0 DM/DBI Control */ + uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */ + uint8_t reserved1c8[0x200 - 0x1c8]; + uint32_t addrmap0; /* 0x200 Address Map 0 */ + uint32_t addrmap1; /* 0x204 Address Map 1 */ + uint32_t addrmap2; /* 0x208 Address Map 2 */ + uint32_t addrmap3; /* 0x20c Address Map 3 */ + uint32_t addrmap4; /* 0x210 Address Map 4 */ + uint32_t addrmap5; /* 0x214 Address Map 5 */ + uint32_t addrmap6; /* 0x218 Address Map 6 */ + uint32_t addrmap7; /* 0x21c Address Map 7 */ + uint32_t addrmap8; /* 0x220 Address Map 8 */ + uint32_t addrmap9; /* 0x224 Address Map 9 */ + uint32_t addrmap10; /* 0x228 Address Map 10 */ + uint32_t addrmap11; /* 0x22C Address Map 11 */ + uint8_t reserved230[0x240 - 0x230]; + uint32_t odtcfg; /* 0x240 ODT Configuration */ + uint32_t odtmap; /* 0x244 ODT/Rank Map */ + uint8_t reserved248[0x250 - 0x248]; + uint32_t sched; /* 0x250 Scheduler Control */ + uint32_t sched1; /* 0x254 Scheduler Control 1 */ + uint32_t reserved258; + uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */ + uint32_t reserved260; + uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */ + uint32_t reserved268; + uint32_t perfwr1; /* 0x26c Write CAM 1 */ + uint8_t reserved27c[0x300 - 0x270]; + uint32_t dbg0; /* 0x300 Debug 0 */ + uint32_t dbg1; /* 0x304 Debug 1 */ + uint32_t dbgcam; /* 0x308 CAM Debug */ + uint32_t dbgcmd; /* 0x30c Command Debug */ + uint32_t dbgstat; /* 0x310 Status Debug */ + uint8_t reserved314[0x320 - 0x314]; + uint32_t swctl; /* 0x320 Software Programming Control Enable */ + uint32_t swstat; /* 0x324 Software Programming Control Status */ + uint8_t reserved328[0x36c - 0x328]; + uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */ + uint32_t poisonstat; /* 0x370 AXI Poison Status Register */ + uint8_t reserved374[0x3f0 - 0x374]; + uint32_t deratestat; /* 0x3f0 Temperature Derate Status */ + uint8_t reserved3f4[0x3fc - 0x3f4]; + + /* Multi Port registers */ + uint32_t pstat; /* 0x3fc Port Status */ + uint32_t pccfg; /* 0x400 Port Common Configuration */ + + /* PORT 0 */ + uint32_t pcfgr_0; /* 0x404 Configuration Read */ + uint32_t pcfgw_0; /* 0x408 Configuration Write */ + uint8_t reserved40c[0x490 - 0x40c]; + uint32_t pctrl_0; /* 0x490 Port Control Register */ + uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */ + uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */ + uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */ + uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */ + uint8_t reserved4a4[0x4b4 - 0x4a4]; + +#if STM32MP_DDR_DUAL_AXI_PORT + /* PORT 1 */ + uint32_t pcfgr_1; /* 0x4b4 Configuration Read */ + uint32_t pcfgw_1; /* 0x4b8 Configuration Write */ + uint8_t reserved4bc[0x540 - 0x4bc]; + uint32_t pctrl_1; /* 0x540 Port 2 Control Register */ + uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */ + uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */ + uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */ + uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */ +#endif + + uint8_t reserved554[0xff0 - 0x554]; + uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */ +} __packed; + +/* DDR Controller registers offsets */ +#define DDRCTRL_MSTR 0x000 +#define DDRCTRL_STAT 0x004 +#define DDRCTRL_MRCTRL0 0x010 +#define DDRCTRL_MRSTAT 0x018 +#define DDRCTRL_PWRCTL 0x030 +#define DDRCTRL_PWRTMG 0x034 +#define DDRCTRL_HWLPCTL 0x038 +#define DDRCTRL_RFSHCTL3 0x060 +#define DDRCTRL_RFSHTMG 0x064 +#define DDRCTRL_INIT0 0x0D0 +#define DDRCTRL_DFIMISC 0x1B0 +#define DDRCTRL_DBG1 0x304 +#define DDRCTRL_DBGCAM 0x308 +#define DDRCTRL_DBGCMD 0x30C +#define DDRCTRL_DBGSTAT 0x310 +#define DDRCTRL_SWCTL 0x320 +#define DDRCTRL_SWSTAT 0x324 +#define DDRCTRL_PSTAT 0x3FC +#define DDRCTRL_PCTRL_0 0x490 +#if STM32MP_DDR_DUAL_AXI_PORT +#define DDRCTRL_PCTRL_1 0x540 +#endif + +/* DDR Controller Register fields */ +#define DDRCTRL_MSTR_DDR3 BIT(0) +#define DDRCTRL_MSTR_LPDDR2 BIT(2) +#define DDRCTRL_MSTR_LPDDR3 BIT(3) +#define DDRCTRL_MSTR_DDR4 BIT(4) +#define DDRCTRL_MSTR_LPDDR4 BIT(5) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0 +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12) +#define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13) +#define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) + +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0) +#define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1)) +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5)) +#define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5) + +#define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0) +/* Only one rank supported */ +#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRCTRL_MRCTRL0_MR_RANK_ALL \ + BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT) +#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) +#define DDRCTRL_MRCTRL0_MR_WR BIT(31) + +#define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) + +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) +#define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) + +#define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) +#define DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL BIT(1) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) +#define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 + +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30) +#define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) +#define DDRCTRL_DFIMISC_DFI_INIT_START BIT(5) + +#define DDRCTRL_DFISTAT_DFI_INIT_COMPLETE BIT(0) + +#define DDRCTRL_DBG1_DIS_HIF BIT(1) + +#define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) +#define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) +#define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) +#define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) +#define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) +#define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ + (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ + DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) +#define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ + (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ + DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ + DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) + +#define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) + +#define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +#endif /* STM32MP_DDRCTRL_REGS_H */ diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h new file mode 100644 index 0000000..303c571 --- /dev/null +++ b/include/drivers/st/stm32mp_pmic.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_PMIC_H +#define STM32MP_PMIC_H + +#include <stdbool.h> + +#include <platform_def.h> + +/* + * dt_pmic_status - Check PMIC status from device tree + * + * Returns the status of the PMIC (secure, non-secure), or a negative value on + * error + */ +int dt_pmic_status(void); + +/* + * initialize_pmic_i2c - Initialize I2C for the PMIC control + * + * Returns true if PMIC is available, false if not found, panics on errors + */ +bool initialize_pmic_i2c(void); + +/* + * initialize_pmic - Main PMIC initialization function, called at platform init + * + * Panics on errors + */ +void initialize_pmic(void); + +#if DEBUG +void print_pmic_info_and_debug(void); +#else +static inline void print_pmic_info_and_debug(void) +{ +} +#endif + +/* + * pmic_ddr_power_init - Initialize regulators required for DDR + * + * Returns 0 on success, and negative values on errors + */ +int pmic_ddr_power_init(enum ddr_type ddr_type); + +/* + * pmic_voltages_init - Update voltages for platform init + * + * Returns 0 on success, and negative values on errors + */ +int pmic_voltages_init(void); + +#endif /* STM32MP_PMIC_H */ diff --git a/include/drivers/st/stm32mp_ram.h b/include/drivers/st/stm32mp_ram.h new file mode 100644 index 0000000..6e1e21d --- /dev/null +++ b/include/drivers/st/stm32mp_ram.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef STM32MP_RAM_H +#define STM32MP_RAM_H + +#include <stdbool.h> + +#include <drivers/st/stm32mp_ddr.h> + +#define PARAM(x, y) \ + { \ + .name = x, \ + .offset = offsetof(struct stm32mp_ddr_config, y), \ + .size = sizeof(config.y) / sizeof(uint32_t), \ + } + +#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) +#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) + +struct stm32mp_ddr_param { + const char *name; /* Name in DT */ + const uint32_t offset; /* Offset in config struct */ + const uint32_t size; /* Size of parameters */ +}; + +int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info); +int stm32mp_ddr_dt_get_param(void *fdt, int node, const struct stm32mp_ddr_param *param, + uint32_t param_size, uintptr_t config); + +#endif /* STM32MP_RAM_H */ diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h new file mode 100644 index 0000000..8444805 --- /dev/null +++ b/include/drivers/st/stm32mp_reset.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP_RESET_H +#define STM32MP_RESET_H + +#include <stdint.h> + +/* + * Assert target reset, if @to_us non null, wait until reset is asserted + * + * @reset_id: Reset controller ID + * @to_us: Timeout in microsecond, or 0 if not waiting + * Return 0 on success and -ETIMEDOUT if waiting and timeout expired + */ +int stm32mp_reset_assert(uint32_t reset_id, unsigned int to_us); + +/* + * Enable reset control for target resource + * + * @reset_id: Reset controller ID + */ +static inline void stm32mp_reset_set(uint32_t reset_id) +{ + (void)stm32mp_reset_assert(reset_id, 0U); +} + +/* + * Deassert target reset, if @to_us non null, wait until reset is deasserted + * + * @reset_id: Reset controller ID + * @to_us: Timeout in microsecond, or 0 if not waiting + * Return 0 on success and -ETIMEDOUT if waiting and timeout expired + */ +int stm32mp_reset_deassert(uint32_t reset_id, unsigned int to_us); + +/* + * Release reset control for target resource + * + * @reset_id: Reset controller ID + */ +static inline void stm32mp_reset_release(uint32_t reset_id) +{ + (void)stm32mp_reset_deassert(reset_id, 0U); +} + +#endif /* STM32MP_RESET_H */ diff --git a/include/drivers/st/stpmic1.h b/include/drivers/st/stpmic1.h new file mode 100644 index 0000000..2dfc7f8 --- /dev/null +++ b/include/drivers/st/stpmic1.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STPMIC1_H +#define STPMIC1_H + +#include <drivers/st/stm32_i2c.h> +#include <lib/utils_def.h> + +#define TURN_ON_REG 0x1U +#define TURN_OFF_REG 0x2U +#define ICC_LDO_TURN_OFF_REG 0x3U +#define ICC_BUCK_TURN_OFF_REG 0x4U +#define RESET_STATUS_REG 0x5U +#define VERSION_STATUS_REG 0x6U +#define MAIN_CONTROL_REG 0x10U +#define PADS_PULL_REG 0x11U +#define BUCK_PULL_DOWN_REG 0x12U +#define LDO14_PULL_DOWN_REG 0x13U +#define LDO56_PULL_DOWN_REG 0x14U +#define VIN_CONTROL_REG 0x15U +#define PONKEY_TIMER_REG 0x16U +#define MASK_RANK_BUCK_REG 0x17U +#define MASK_RESET_BUCK_REG 0x18U +#define MASK_RANK_LDO_REG 0x19U +#define MASK_RESET_LDO_REG 0x1AU +#define WATCHDOG_CONTROL_REG 0x1BU +#define WATCHDOG_TIMER_REG 0x1CU +#define BUCK_ICC_TURNOFF_REG 0x1DU +#define LDO_ICC_TURNOFF_REG 0x1EU +#define BUCK_APM_CONTROL_REG 0x1FU +#define BUCK1_CONTROL_REG 0x20U +#define BUCK2_CONTROL_REG 0x21U +#define BUCK3_CONTROL_REG 0x22U +#define BUCK4_CONTROL_REG 0x23U +#define VREF_DDR_CONTROL_REG 0x24U +#define LDO1_CONTROL_REG 0x25U +#define LDO2_CONTROL_REG 0x26U +#define LDO3_CONTROL_REG 0x27U +#define LDO4_CONTROL_REG 0x28U +#define LDO5_CONTROL_REG 0x29U +#define LDO6_CONTROL_REG 0x2AU +#define BUCK1_PWRCTRL_REG 0x30U +#define BUCK2_PWRCTRL_REG 0x31U +#define BUCK3_PWRCTRL_REG 0x32U +#define BUCK4_PWRCTRL_REG 0x33U +#define VREF_DDR_PWRCTRL_REG 0x34U +#define LDO1_PWRCTRL_REG 0x35U +#define LDO2_PWRCTRL_REG 0x36U +#define LDO3_PWRCTRL_REG 0x37U +#define LDO4_PWRCTRL_REG 0x38U +#define LDO5_PWRCTRL_REG 0x39U +#define LDO6_PWRCTRL_REG 0x3AU +#define FREQUENCY_SPREADING_REG 0x3BU +#define USB_CONTROL_REG 0x40U +#define ITLATCH1_REG 0x50U +#define ITLATCH2_REG 0x51U +#define ITLATCH3_REG 0x52U +#define ITLATCH4_REG 0x53U +#define ITSETLATCH1_REG 0x60U +#define ITSETLATCH2_REG 0x61U +#define ITSETLATCH3_REG 0x62U +#define ITSETLATCH4_REG 0x63U +#define ITCLEARLATCH1_REG 0x70U +#define ITCLEARLATCH2_REG 0x71U +#define ITCLEARLATCH3_REG 0x72U +#define ITCLEARLATCH4_REG 0x73U +#define ITMASK1_REG 0x80U +#define ITMASK2_REG 0x81U +#define ITMASK3_REG 0x82U +#define ITMASK4_REG 0x83U +#define ITSETMASK1_REG 0x90U +#define ITSETMASK2_REG 0x91U +#define ITSETMASK3_REG 0x92U +#define ITSETMASK4_REG 0x93U +#define ITCLEARMASK1_REG 0xA0U +#define ITCLEARMASK2_REG 0xA1U +#define ITCLEARMASK3_REG 0xA2U +#define ITCLEARMASK4_REG 0xA3U +#define ITSOURCE1_REG 0xB0U +#define ITSOURCE2_REG 0xB1U +#define ITSOURCE3_REG 0xB2U +#define ITSOURCE4_REG 0xB3U + +/* Registers masks */ +#define LDO_VOLTAGE_MASK GENMASK(6, 2) +#define BUCK_VOLTAGE_MASK GENMASK(7, 2) +#define LDO_BUCK_VOLTAGE_SHIFT 2 +#define LDO_BUCK_ENABLE_MASK BIT(0) +#define LDO_BUCK_HPLP_ENABLE_MASK BIT(1) +#define LDO_BUCK_HPLP_SHIFT 1 +#define LDO_BUCK_RANK_MASK BIT(0) +#define LDO_BUCK_RESET_MASK BIT(0) +#define LDO_BUCK_PULL_DOWN_MASK GENMASK(1, 0) + +/* Pull down register */ +#define BUCK1_PULL_DOWN_SHIFT 0 +#define BUCK2_PULL_DOWN_SHIFT 2 +#define BUCK3_PULL_DOWN_SHIFT 4 +#define BUCK4_PULL_DOWN_SHIFT 6 +#define VREF_DDR_PULL_DOWN_SHIFT 4 + +/* ICC register */ +#define BUCK1_ICC_SHIFT 0 +#define BUCK2_ICC_SHIFT 1 +#define BUCK3_ICC_SHIFT 2 +#define BUCK4_ICC_SHIFT 3 +#define PWR_SW1_ICC_SHIFT 4 +#define PWR_SW2_ICC_SHIFT 5 +#define BOOST_ICC_SHIFT 6 + +#define LDO1_ICC_SHIFT 0 +#define LDO2_ICC_SHIFT 1 +#define LDO3_ICC_SHIFT 2 +#define LDO4_ICC_SHIFT 3 +#define LDO5_ICC_SHIFT 4 +#define LDO6_ICC_SHIFT 5 + +/* Buck Mask reset register */ +#define BUCK1_MASK_RESET 0 +#define BUCK2_MASK_RESET 1 +#define BUCK3_MASK_RESET 2 +#define BUCK4_MASK_RESET 3 + +/* LDO Mask reset register */ +#define LDO1_MASK_RESET 0 +#define LDO2_MASK_RESET 1 +#define LDO3_MASK_RESET 2 +#define LDO4_MASK_RESET 3 +#define LDO5_MASK_RESET 4 +#define LDO6_MASK_RESET 5 +#define VREF_DDR_MASK_RESET 6 + +/* LDO3 Special modes */ +#define LDO3_BYPASS BIT(7) +#define LDO3_DDR_SEL 31U + +/* Main PMIC Control Register (MAIN_CONTROL_REG) */ +#define ICC_EVENT_ENABLED BIT(4) +#define PWRCTRL_POLARITY_HIGH BIT(3) +#define PWRCTRL_PIN_VALID BIT(2) +#define RESTART_REQUEST_ENABLED BIT(1) +#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0) + +/* Main PMIC PADS Control Register (PADS_PULL_REG) */ +#define WAKEUP_DETECTOR_DISABLED BIT(4) +#define PWRCTRL_PD_ACTIVE BIT(3) +#define PWRCTRL_PU_ACTIVE BIT(2) +#define WAKEUP_PD_ACTIVE BIT(1) +#define PONKEY_PU_ACTIVE BIT(0) + +/* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */ +#define SWIN_DETECTOR_ENABLED BIT(7) +#define SWOUT_DETECTOR_ENABLED BIT(6) +#define VINLOW_HYST_MASK GENMASK(1, 0) +#define VINLOW_HYST_SHIFT 4 +#define VINLOW_THRESHOLD_MASK GENMASK(2, 0) +#define VINLOW_THRESHOLD_SHIFT 1 +#define VINLOW_ENABLED BIT(0) +#define VINLOW_CTRL_REG_MASK GENMASK(7, 0) + +/* USB Control Register */ +#define BOOST_OVP_DISABLED BIT(7) +#define VBUS_OTG_DETECTION_DISABLED BIT(6) +#define SW_OUT_DISCHARGE BIT(5) +#define VBUS_OTG_DISCHARGE BIT(4) +#define OCP_LIMIT_HIGH BIT(3) +#define SWIN_SWOUT_ENABLED BIT(2) +#define USBSW_OTG_SWITCH_ENABLED BIT(1) +#define BOOST_ENABLED BIT(0) + +int stpmic1_powerctrl_on(void); +int stpmic1_switch_off(void); +int stpmic1_register_read(uint8_t register_id, uint8_t *value); +int stpmic1_register_write(uint8_t register_id, uint8_t value); +int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask); +int stpmic1_regulator_enable(const char *name); +int stpmic1_regulator_disable(const char *name); +bool stpmic1_is_regulator_enabled(const char *name); +int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts); +int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels, + size_t *levels_count); +int stpmic1_regulator_voltage_get(const char *name); +int stpmic1_regulator_pull_down_set(const char *name); +int stpmic1_regulator_mask_reset_set(const char *name); +int stpmic1_regulator_icc_set(const char *name); +int stpmic1_regulator_sink_mode_set(const char *name); +int stpmic1_regulator_bypass_mode_set(const char *name); +int stpmic1_active_discharge_mode_set(const char *name); +void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr); + +int stpmic1_get_version(unsigned long *version); +void stpmic1_dump_regulators(void); + +#endif /* STPMIC1_H */ |