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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
| commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
| tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /include/plat | |
| parent | Initial commit. (diff) | |
| download | arm-trusted-firmware-upstream.tar.xz arm-trusted-firmware-upstream.zip | |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'include/plat')
54 files changed, 5872 insertions, 0 deletions
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h new file mode 100644 index 0000000..1963bf0 --- /dev/null +++ b/include/plat/arm/board/common/board_css_def.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOARD_CSS_DEF_H +#define BOARD_CSS_DEF_H + +#include <lib/utils_def.h> +#include <plat/arm/board/common/v2m_def.h> +#include <plat/arm/soc/common/soc_css_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSS-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 +#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 +#define BOARD_CSS_PLAT_TYPE_RTL 0x00 +#define BOARD_CSS_PLAT_TYPE_FPGA 0x01 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 +#define BOARD_CSS_PLAT_TYPE_FVP 0x03 + +#ifndef __ASSEMBLER__ + +#include <lib/mmio.h> + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLER__ */ + + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* Reserve the last block of flash for PSCI MEM PROTECT flag */ +#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +#if ARM_GPT_SUPPORT +/* + * Offset of the FIP in the GPT image. BL1 component uses this option + * as it does not load the partition table to get the FIP base + * address. At sector 34 by default (i.e. after reserved sectors 0-33) + * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 + */ +#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 +#endif /* ARM_GPT_SUPPORT */ + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ + +#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ + +#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + +#endif /* BOARD_CSS_DEF_H */ diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h new file mode 100644 index 0000000..cb11dac --- /dev/null +++ b/include/plat/arm/board/common/v2m_def.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef V2M_DEF_H +#define V2M_DEF_H + +#include <lib/utils_def.h> + +/* Base address of all V2M */ +#ifdef PLAT_V2M_OFFSET +#define V2M_OFFSET PLAT_V2M_OFFSET +#else +#define V2M_OFFSET UL(0) +#endif + +/* V2M motherboard system registers & offsets */ +#define V2M_SYSREGS_BASE UL(0x1c010000) +#define V2M_SYS_ID UL(0x0) +#define V2M_SYS_SWITCH UL(0x4) +#define V2M_SYS_LED UL(0x8) +#define V2M_SYS_NVFLAGS UL(0x38) +#define V2M_SYS_NVFLAGSSET UL(0x38) +#define V2M_SYS_NVFLAGSCLR UL(0x3c) +#define V2M_SYS_CFGDATA UL(0xa0) +#define V2M_SYS_CFGCTRL UL(0xa4) +#define V2M_SYS_CFGSTATUS UL(0xa8) + +#define V2M_CFGCTRL_START BIT_32(31) +#define V2M_CFGCTRL_RW BIT_32(30) +#define V2M_CFGCTRL_FUNC_SHIFT 20 +#define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) +#define V2M_FUNC_CLK_GEN U(0x01) +#define V2M_FUNC_TEMP U(0x04) +#define V2M_FUNC_DB_RESET U(0x05) +#define V2M_FUNC_SCC_CFG U(0x06) +#define V2M_FUNC_SHUTDOWN U(0x08) +#define V2M_FUNC_REBOOT U(0x09) + +/* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ + #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define V2M_SYS_LED_SS_SHIFT 0x0 +#define V2M_SYS_LED_EL_SHIFT 0x1 +#define V2M_SYS_LED_EC_SHIFT 0x3 + +#define V2M_SYS_LED_SS_MASK U(0x1) +#define V2M_SYS_LED_EL_MASK U(0x3) +#define V2M_SYS_LED_EC_MASK U(0x1f) + +/* V2M sysid register bits */ +#define V2M_SYS_ID_REV_SHIFT 28 +#define V2M_SYS_ID_HBI_SHIFT 16 +#define V2M_SYS_ID_BLD_SHIFT 12 +#define V2M_SYS_ID_ARCH_SHIFT 8 +#define V2M_SYS_ID_FPGA_SHIFT 0 + +#define V2M_SYS_ID_REV_MASK U(0xf) +#define V2M_SYS_ID_HBI_MASK U(0xfff) +#define V2M_SYS_ID_BLD_MASK U(0xf) +#define V2M_SYS_ID_ARCH_MASK U(0xf) +#define V2M_SYS_ID_FPGA_MASK U(0xff) + +#define V2M_SYS_ID_BLD_LENGTH 4 + + +/* NOR Flash */ +#define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000)) +#define V2M_FLASH0_SIZE UL(0x04000000) +#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ + +#define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000)) +#define V2M_IOFPGA_SIZE UL(0x03000000) + +/* PL011 UART related constants */ +#define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000)) +#define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000)) +#define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000)) +#define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000)) + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 + +/* SP804 timer related constants */ +#define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000)) +#define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000)) + +/* SP810 controller */ +#define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000)) +#define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) +#define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) +#define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) +#define V2M_SP810_CTRL_TIM3_SEL BIT_32(21) + +/* + * The flash can be mapped either as read-only or read-write. + * + * If it is read-write then it should also be mapped as device memory because + * NOR flash programming involves sending a fixed, ordered sequence of commands. + * + * If it is read-only then it should also be mapped as: + * - Normal memory, because reading from NOR flash is transparent, it is like + * reading from RAM. + * - Non-executable by default. If some parts of the flash need to be executable + * then platform code is responsible for re-mapping the appropriate portion + * of it as executable. + */ +#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_RO_DATA | MT_SECURE) + +#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ + V2M_IOFPGA_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */ +#define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \ + V2M_IOFPGA_BASE, \ + V2M_IOFPGA_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE | MT_USER) + + +#endif /* V2M_DEF_H */ diff --git a/include/plat/arm/board/fvp_r/fvp_r_bl1.h b/include/plat/arm/board/fvp_r/fvp_r_bl1.h new file mode 100644 index 0000000..0b41e67 --- /dev/null +++ b/include/plat/arm/board/fvp_r/fvp_r_bl1.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FVP_R_BL1_H +#define FVP_R_BL1_H + +void bl1_load_bl33(void); +void bl1_transfer_bl33(void); + +#endif /* FVP_R_BL1_H */ diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S new file mode 100644 index 0000000..8aacfb0 --- /dev/null +++ b/include/plat/arm/common/aarch64/arm_macros.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_MACROS_S +#define ARM_MACROS_S + +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gicv3.h> +#include <platform_def.h> + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t 0x" +prefix: + .asciz "0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on ARM standard platforms. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro arm_print_gic_regs + /* Check for GICv3/v4 system register access. + * ID_AA64PFR0_GIC indicates presence of the CPU + * system registers by either 0b0011 or 0xb0001. + * A value of 0b000 means CPU system registers aren't + * available and the code needs to use the memory + * mapped registers like in GICv2. + */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #0 + b.eq print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + + /* Print "0x" */ + adr x4, prefix + bl asm_print_str + + /* Print offset */ + sub x4, x7, x16 + mov x5, #12 + bl asm_print_hex_bits + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +#endif /* ARM_MACROS_S */ diff --git a/include/plat/arm/common/aarch64/cci_macros.S b/include/plat/arm/common/aarch64/cci_macros.S new file mode 100644 index 0000000..07f7cd3 --- /dev/null +++ b/include/plat/arm/common/aarch64/cci_macros.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef CCI_MACROS_S +#define CCI_MACROS_S + +#include <drivers/arm/cci.h> +#include <platform_def.h> + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro print_cci_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + +#endif /* CCI_MACROS_S */ diff --git a/include/plat/arm/common/arm_config.h b/include/plat/arm/common/arm_config.h new file mode 100644 index 0000000..c2b28df --- /dev/null +++ b/include/plat/arm/common/arm_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_CONFIG_H +#define ARM_CONFIG_H + +#include <stdint.h> + +#include <lib/utils_def.h> + +/* Whether Base memory map is in use */ +#define ARM_CONFIG_BASE_MMAP BIT(1) + +/* Whether TZC should be configured */ +#define ARM_CONFIG_HAS_TZC BIT(2) + +/* FVP model has shifted affinity */ +#define ARM_CONFIG_FVP_SHIFTED_AFF BIT(3) + +/* FVP model has SMMUv3 affinity */ +#define ARM_CONFIG_FVP_HAS_SMMUV3 BIT(4) + +/* FVP model has CCI (400 or 500/550) devices */ +#define ARM_CONFIG_FVP_HAS_CCI400 BIT(5) +#define ARM_CONFIG_FVP_HAS_CCI5XX BIT(6) + +typedef struct arm_config { + unsigned long flags; +} arm_config_t; + + +/* If used, arm_config must be defined and populated in the platform port */ +extern arm_config_t arm_config; + +static inline const arm_config_t *get_arm_config(void) +{ + return &arm_config; +} + + +#endif /* ARM_CONFIG_H */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h new file mode 100644 index 0000000..e098c10 --- /dev/null +++ b/include/plat/arm/common/arm_def.h @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_DEF_H +#define ARM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Root of trust key lengths + */ +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +#define ARM_SYSTEM_COUNT U(1) + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 +#define ARM_PWR_LVL3 MPIDR_AFFLVL3 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET U(1) +/* Local power state for OFF/power-down. Valid for CPU and cluster power + domains */ +#define ARM_LOCAL_STATE_OFF U(2) + +/* Memory location options for TSP */ +#define ARM_TRUSTED_SRAM_ID 0 +#define ARM_TRUSTED_DRAM_ID 1 +#define ARM_DRAM_ID 2 + +#ifdef PLAT_ARM_TRUSTED_SRAM_BASE +#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE +#else +#define ARM_TRUSTED_SRAM_BASE UL(0x04000000) +#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ + +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +/* + * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as + * follows: + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled + * - REALM DRAM: Reserved for Realm world if RME is enabled + * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM + * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + * + * RME enabled(64MB) RME not enabled(16MB) + * -------------------- ------------------- + * | | | | + * | AP TZC (~28MB) | | AP TZC (~14MB) | + * -------------------- ------------------- + * | Event Log | | Event Log | + * | (4KB) | | (4KB) | + * -------------------- ------------------- + * | REALM (RMM) | | | + * | (32MB - 4KB) | | EL3 TZC (2MB) | + * -------------------- ------------------- + * | | | | + * | TF-A <-> RMM | | SCP TZC | + * | SHARED (4KB) | 0xFFFF_FFFF------------------- + * -------------------- + * | | + * | EL3 TZC (3MB) | + * -------------------- + * | L1 GPT + SCP TZC | + * | (~1MB) | + * 0xFFFF_FFFF -------------------- + */ +#if ENABLE_RME +#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ +/* + * Define a region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be + * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. + */ +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ +#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ +/* 32MB - ARM_EL3_RMM_SHARED_SIZE */ +#define ARM_REALM_SIZE (UL(0x02000000) - \ + ARM_EL3_RMM_SHARED_SIZE) +#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ +#else +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ +#define ARM_L1_GPT_SIZE UL(0) +#define ARM_REALM_SIZE UL(0) +#define ARM_EL3_RMM_SHARED_SIZE UL(0) +#endif /* ENABLE_RME */ + +#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE)) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1U) + +# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ + +#if ENABLE_RME +#define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ + ARM_EVENT_LOG_DRAM1_SIZE) +#else +#define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ + ARM_EVENT_LOG_DRAM1_SIZE) +#endif /* ENABLE_RME */ +#define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ + ARM_EVENT_LOG_DRAM1_SIZE - \ + 1U) +#else +#define ARM_EVENT_LOG_DRAM1_SIZE UL(0) +#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ + +#if ENABLE_RME +#define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_L1_GPT_SIZE) +#define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ + ARM_L1_GPT_SIZE - 1U) + +#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ + ARM_REALM_SIZE) + +#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) + +#define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_L1_GPT_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) + +#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ + ARM_EL3_RMM_SHARED_SIZE - 1U) +#endif /* ENABLE_RME */ + +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) +#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ + ARM_EL3_TZC_DRAM1_SIZE - 1U) + +#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE + \ + ARM_REALM_SIZE + \ + ARM_L1_GPT_SIZE + \ + ARM_EVENT_LOG_DRAM1_SIZE)) + +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1U) + +/* Define the Access permissions for Secure peripherals to NS_DRAM */ +#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE + +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE) +#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) +#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ + ARM_OPTEE_PAGEABLE_LOAD_BASE, \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging + * support is enabled). + */ +#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) + +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1U) +#ifdef PLAT_ARM_DRAM1_BASE +#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE +#else +#define ARM_DRAM1_BASE ULL(0x80000000) +#endif /* PLAT_ARM_DRAM1_BASE */ + +#define ARM_DRAM1_SIZE ULL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1U) + +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE +#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE +#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ + ARM_DRAM2_SIZE - 1U) +/* Number of DRAM banks */ +#define ARM_DRAM_NUM_BANKS 2UL + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ + GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ + GIC_INTR_CFG_EDGE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | EL3_PAS) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, \ + ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if ARM_BL31_IN_DRAM +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_MAP_EVENT_LOG_DRAM1 \ + MAP_REGION_FLAT( \ + ARM_EVENT_LOG_DRAM1_BASE, \ + ARM_EVENT_LOG_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ + +#if ENABLE_RME +/* + * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. + * Else we end up requiring more pagetables in BL2 for ROMLIB build. + */ +#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_RMM_BASE, \ + (PLAT_ARM_RMM_SIZE + \ + ARM_EL3_RMM_SHARED_SIZE), \ + MT_MEMORY | MT_RW | MT_REALM) + + +#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ + ARM_L1_GPT_ADDR_BASE, \ + ARM_L1_GPT_SIZE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +#define ARM_MAP_EL3_RMM_SHARED_MEM \ + MAP_REGION_FLAT( \ + ARM_EL3_RMM_SHARED_BASE, \ + ARM_EL3_RMM_SHARED_SIZE, \ + MT_MEMORY | MT_RW | MT_REALM) + +#endif /* ENABLE_RME */ + +/* + * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to + * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides + * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order + * to be able to access the heap. + */ +#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ + BL1_RW_BASE, \ + BL1_RW_LIMIT - BL1_RW_BASE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +/* + * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section + * otherwise one region is defined containing both. + */ +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) +#else +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS) +#endif +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) +#endif +#if USE_ROMLIB +#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ + ROMLIB_RO_BASE, \ + ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ + MT_CODE | EL3_PAS) + +#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ + ROMLIB_RW_BASE, \ + ROMLIB_RW_END - ROMLIB_RW_BASE,\ + MT_MEMORY | MT_RW | EL3_PAS) +#endif + +/* + * Map mem_protect flash region with read and write permissions + */ +#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ + V2M_FLASH_BLOCK_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +/* + * Map the region for device tree configuration with read and write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ + (ARM_FW_CONFIGS_LIMIT \ + - ARM_BL_RAM_BASE), \ + MT_MEMORY | MT_RW | EL3_PAS) +/* + * Map L0_GPT with read and write permissions + */ +#if ENABLE_RME +#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ + ARM_L0_GPT_SIZE, \ + MT_MEMORY | MT_RW | MT_ROOT) +#endif + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 7 + +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#ifdef PLAT_ARM_SYS_CNTCTL_BASE +#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE +#else +#define ARM_SYS_CNTCTL_BASE UL(0x2a430000) +#endif + +#ifdef PLAT_ARM_SYS_CNTREAD_BASE +#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE +#else +#define ARM_SYS_CNTREAD_BASE UL(0x2a800000) +#endif + +#ifdef PLAT_ARM_SYS_TIMCTL_BASE +#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE +#else +#define ARM_SYS_TIMCTL_BASE UL(0x2a810000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_S +#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S +#else +#define ARM_SYS_CNT_BASE_S UL(0x2a820000) +#endif + +#ifdef PLAT_ARM_SYS_CNT_BASE_NS +#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS +#else +#define ARM_SYS_CNT_BASE_NS UL(0x2a830000) +#endif + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* Trusted Watchdog constants */ +#ifdef PLAT_ARM_SP805_TWDG_BASE +#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE +#else +#define ARM_SP805_TWDG_BASE UL(0x2a490000) +#endif +#define ARM_SP805_TWDG_CLK_HZ 32768 +/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) + +/* + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ + + (PAGE_SIZE / 2U)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) +#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ + + (PAGE_SIZE / 2U)) + +/* + * Define limit of firmware configuration memory: + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory + */ +#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) + +#if ENABLE_RME +/* + * Store the L0 GPT on Trusted SRAM next to firmware + * configuration memory, 4KB aligned. + */ +#define ARM_L0_GPT_SIZE (PAGE_SIZE) +#define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) +#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) +#else +#define ARM_L0_GPT_SIZE U(0) +#endif + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#ifdef PLAT_BL1_RO_LIMIT +#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT +#else +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + + (PLAT_ARM_TRUSTED_ROM_SIZE - \ + PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +#endif + +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + (PLAT_ARM_MAX_BL1_RW_SIZE +\ + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ + (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) + +#define ROMLIB_RO_BASE BL1_RO_LIMIT +#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) + +#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) +#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#if RESET_TO_BL2 +#if ENABLE_PIE +/* + * As the BL31 image size appears to be increased when built with the ENABLE_PIE + * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. + */ +#define BL2_OFFSET (0x5000) +#else +/* Put BL2 towards the middle of the Trusted SRAM */ +#define BL2_OFFSET (0x2000) +#endif /* ENABLE_PIE */ + +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ + BL2_OFFSET) +#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +#else +/* + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE +#endif + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION +/* + * Put BL31 at the bottom of TZC secured DRAM + */ +#define BL31_BASE ARM_AP_TZC_DRAM1_BASE +#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ +#elif (RESET_TO_BL31) +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif +/* + * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely + * used for building BL31 and not used for loading BL31. + */ +# define BL31_BASE 0x0 +# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE +#else +/* Put BL31 below BL2 in the Trusted SRAM.*/ +#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ + - PLAT_ARM_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL2_BASE +/* + * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. + * This is because in the RESET_TO_BL2 configuration, + * BL2 is always resident. + */ +#if RESET_TO_BL2 +#define BL31_LIMIT BL2_BASE +#else +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#endif +#endif + +/****************************************************************************** + * RMM specific defines + *****************************************************************************/ +#if ENABLE_RME +#define RMM_BASE (ARM_REALM_BASE) +#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) +#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) +#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) +#endif + +#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME +/******************************************************************************* + * BL32 specific defines for EL3 runtime in AArch32 mode + ******************************************************************************/ +# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +# if !ENABLE_PIE +# error "BL32 must be a PIE if RESET_TO_SP_MIN=1." +#endif +/* + * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely + * used for building BL32 and not used for loading BL32. + */ +# define BL32_BASE 0x0 +# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE +# else +/* Put BL32 below BL2 in the Trusted SRAM.*/ +# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ + - PLAT_ARM_MAX_BL32_SIZE) +# define BL32_PROGBITS_LIMIT BL2_BASE +# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ + +#else +/******************************************************************************* + * BL32 specific defines for EL3 runtime in AArch64 mode + ******************************************************************************/ +/* + * On ARM standard platforms, the TSP can execute from Trusted SRAM, + * Trusted DRAM (if available) or the DRAM region secured by the TrustZone + * controller. + */ +# if SPM_MM || SPMC_AT_EL3 +# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) +# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) +# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +# elif defined(SPD_spmd) +# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) +# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) +# define BL32_BASE PLAT_ARM_SPMC_BASE +# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ + PLAT_ARM_SPMC_SIZE) +# elif ARM_BL31_IN_DRAM +# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ + PLAT_ARM_MAX_BL31_SIZE) +# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID +# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE +# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE +# define TSP_PROGBITS_LIMIT BL31_BASE +# define BL32_BASE ARM_FW_CONFIGS_LIMIT +# define BL32_LIMIT BL31_BASE +# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID +# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE +# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ + + SZ_4M) +# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID +# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +# define BL32_BASE ARM_AP_TZC_DRAM1_BASE +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +# else +# error "Unsupported ARM_TSP_RAM_LOCATION_ID value" +# endif +#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ + +/* + * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no + * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be + * used as BL32. + */ +#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME +# if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 +# undef BL32_BASE +# endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ +#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ + +/******************************************************************************* + * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. + ******************************************************************************/ +#define BL2U_BASE BL2_BASE +#define BL2U_LIMIT BL2_LIMIT + +#define NS_BL2U_BASE ARM_NS_DRAM1_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + +/* Priority levels for ARM platforms */ +#if ENABLE_FEAT_RAS && FFH_SUPPORT +#define PLAT_RAS_PRI 0x10 +#endif +#define PLAT_SDEI_CRITICAL_PRI 0x60 +#define PLAT_SDEI_NORMAL_PRI 0x70 + +/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ +#define PLAT_CORE_FAULT_IRQ 17 + +/* ARM platforms use 3 upper bits of secure interrupt priority */ +#define PLAT_PRI_BITS 3 + +/* SGI used for SDEI signalling */ +#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 + +#if SDEI_IN_FCONF +/* ARM SDEI dynamic private event max count */ +#define ARM_SDEI_DP_EVENT_MAX_CNT 3 + +/* ARM SDEI dynamic shared event max count */ +#define ARM_SDEI_DS_EVENT_MAX_CNT 3 +#else +/* ARM SDEI dynamic private event numbers */ +#define ARM_SDEI_DP_EVENT_0 1000 +#define ARM_SDEI_DP_EVENT_1 1001 +#define ARM_SDEI_DP_EVENT_2 1002 + +/* ARM SDEI dynamic shared event numbers */ +#define ARM_SDEI_DS_EVENT_0 2000 +#define ARM_SDEI_DS_EVENT_1 2001 +#define ARM_SDEI_DS_EVENT_2 2002 + +#define ARM_SDEI_PRIVATE_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) + +#define ARM_SDEI_SHARED_EVENTS \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) +#endif /* SDEI_IN_FCONF */ + +#endif /* ARM_DEF_H */ diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h new file mode 100644 index 0000000..ff00fe7 --- /dev/null +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_DYN_CFG_HELPERS_H +#define ARM_DYN_CFG_HELPERS_H + +#include <stddef.h> +#include <stdint.h> + +/* Function declarations */ +int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); +int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, + size_t heap_size); + +#endif /* ARM_DYN_CFG_HELPERS_H */ diff --git a/include/plat/arm/common/arm_fconf_getter.h b/include/plat/arm/common/arm_fconf_getter.h new file mode 100644 index 0000000..8fd8c7a --- /dev/null +++ b/include/plat/arm/common/arm_fconf_getter.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARM_FCONF_GETTER +#define ARM_FCONF_GETTER + +#include <assert.h> + +#include <lib/fconf/fconf.h> + +/* ARM io policies */ +#define arm__io_policies_getter(id) __extension__ ({ \ + assert((id) < MAX_NUMBER_IDS); \ + &policies[id]; \ +}) + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +extern struct plat_io_policy policies[]; +int fconf_populate_arm_io_policies(uintptr_t config); + +#endif /* ARM_FCONF_GETTER */ diff --git a/include/plat/arm/common/arm_fconf_io_storage.h b/include/plat/arm/common/arm_fconf_io_storage.h new file mode 100644 index 0000000..02ee66c --- /dev/null +++ b/include/plat/arm/common/arm_fconf_io_storage.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_FCONF_IO_STORAGE_H +#define ARM_FCONF_IO_STORAGE_H + +#include <stdint.h> + +/* IO devices handle */ +extern uintptr_t memmap_dev_handle; +extern uintptr_t fip_dev_handle; + +/* Function declarations */ +int open_fip(const uintptr_t spec); +int open_memmap(const uintptr_t spec); + +#endif /* ARM_FCONF_IO_STORAGE_H */ diff --git a/include/plat/arm/common/arm_pas_def.h b/include/plat/arm/common/arm_pas_def.h new file mode 100644 index 0000000..fba8d2c --- /dev/null +++ b/include/plat/arm/common/arm_pas_def.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_PAS_DEF_H +#define ARM_PAS_DEF_H + +#include <lib/gpt_rme/gpt_rme.h> +#include <plat/arm/common/arm_def.h> + +/***************************************************************************** + * PAS regions used to initialize the Granule Protection Table (GPT) + ****************************************************************************/ + +/* + * The PA space is initially mapped in the GPT as follows: + * + * ============================================================================ + * Base Addr| Size |L? GPT|PAS |Content |Comment + * ============================================================================ + * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping + * | | | |TSRAM (EL3 data) | + * 00000000 | | | |IO (incl.UARTs & GIC) | + * ---------------------------------------------------------------------------- + * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping + * 40000000 | | | | | + * ---------------------------------------------------------------------------- + * 2GB |2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip + * 80000000 | | | | | + * ---------------------------------------------------------------------------- + * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip + * FC000000 | | | | | + * ---------------------------------------------------------------------------- + * 4GB-32MB | | | | | + * -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip + * FDC00000 | | | | | + * ---------------------------------------------------------------------------- + * 4GB-3MB | | | | | + * -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip + * FFC00000 | | | | | + * ---------------------------------------------------------------------------- + * 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping + * FFF00000 | | | | | + * ---------------------------------------------------------------------------- + * 34GB |2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip + * 880000000| | | | | + * ============================================================================ + * + * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. + * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). + * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by + * the GPT. + * - The DRAM TZC area is split into three regions: the L1 GPT region and + * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region + * below that is defined as GPT_GPI_REALM and the rest of it is defined as + * GPT_GPI_SECURE. + */ + +/* TODO: This might not be the best way to map the PAS */ + +/* Device memory 0 to 2GB */ +#define ARM_PAS_1_BASE (U(0)) +#define ARM_PAS_1_SIZE ((ULL(1) << 31)) /* 2GB */ + +/* NS memory 2GB to (end - 64MB) */ +#define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) +#define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) + +/* Shared area between EL3 and RMM */ +#define ARM_PAS_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) +#define ARM_PAS_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) + +/* Secure TZC region */ +#define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) +#define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) + +/* NS memory 2GB */ +#define ARM_PAS_4_BASE ARM_DRAM2_BASE +#define ARM_PAS_4_SIZE ((ULL(1) << 31)) /* 2GB */ + +#define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ + ARM_PAS_1_SIZE, \ + GPT_GPI_ANY) + +#define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ + ARM_PAS_2_SIZE, \ + GPT_GPI_NS) + +#define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ + ARM_PAS_3_SIZE, \ + GPT_GPI_SECURE) + +#define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \ + ARM_PAS_4_SIZE, \ + GPT_GPI_NS) +/* + * REALM and Shared area share the same PAS, so consider them a single + * PAS region to configure in GPT. + */ +#define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ + (ARM_PAS_SHARED_SIZE + \ + ARM_REALM_SIZE), \ + GPT_GPI_REALM) + +#define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + GPT_GPI_ROOT) + +#define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_ADDR_BASE, \ + ARM_L1_GPT_SIZE, \ + GPT_GPI_ROOT) + +/* GPT Configuration options */ +#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS + +#endif /* ARM_PAS_DEF_H */ diff --git a/include/plat/arm/common/arm_reclaim_init.ld.S b/include/plat/arm/common/arm_reclaim_init.ld.S new file mode 100644 index 0000000..a77c964 --- /dev/null +++ b/include/plat/arm/common/arm_reclaim_init.ld.S @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_RECLAIM_INIT_LD_S +#define ARM_RECLAIM_INIT_LD_S + +SECTIONS +{ + .init __STACKS_START__ : { + . = . + PLATFORM_STACK_SIZE; + . = ALIGN(PAGE_SIZE); + __INIT_CODE_START__ = .; + *(*text.init.*); + __INIT_CODE_END__ = .; + INIT_CODE_END_ALIGNED = ALIGN(PAGE_SIZE); + } >RAM + +#ifdef BL31_PROGBITS_LIMIT + ASSERT(__INIT_CODE_END__ <= BL31_PROGBITS_LIMIT, + "BL31 init has exceeded progbits limit.") +#endif +} + +#define ABS ABSOLUTE + +#define STACK_SECTION \ + .stacks (NOLOAD) : { \ + __STACKS_START__ = .; \ + *(.tzfw_normal_stacks) \ + __STACKS_END__ = .; \ + /* Allow room for the init section where necessary. */ \ + OFFSET = ABS(SIZEOF(.init) - (. - __STACKS_START__)); \ + /* Offset sign */ \ + SIGN = ABS(OFFSET) & (1 << 63); \ + /* Offset mask */ \ + MASK = ABS(SIGN >> 63) - 1; \ + . += ABS(OFFSET) & ABS(MASK); \ + . = ALIGN(PAGE_SIZE); \ + } + +#endif /* ARM_RECLAIM_INIT_LD_S */ diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h new file mode 100644 index 0000000..266092e --- /dev/null +++ b/include/plat/arm/common/arm_sip_svc.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016-2019,2021-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ARM_SIP_SVC_H +#define ARM_SIP_SVC_H + +#include <lib/utils_def.h> + +/* SMC function IDs for SiP Service queries */ + +#define ARM_SIP_SVC_CALL_COUNT U(0x8200ff00) +#define ARM_SIP_SVC_UID U(0x8200ff01) +/* U(0x8200ff02) is reserved */ +#define ARM_SIP_SVC_VERSION U(0x8200ff03) + +/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */ +/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */ + +/* Function ID for requesting state switch of lower EL */ +#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020) + +/* DEBUGFS_SMC_32 0x82000030U */ +/* DEBUGFS_SMC_64 0xC2000030U */ + +/* + * Arm(R) Ethos(TM)-N NPU SiP SMC function IDs + * 0xC2000050-0xC200005F + * 0x82000050-0x8200005F + */ + +/* ARM SiP Service Calls version numbers */ +#define ARM_SIP_SVC_VERSION_MAJOR U(0x0) +#define ARM_SIP_SVC_VERSION_MINOR U(0x2) + +/* + * Arm SiP SMC calls that are primarily used for testing purposes. + */ +#if PLAT_TEST_SPM +#define ARM_SIP_SET_INTERRUPT_PENDING U(0x82000100) +#endif + +/* SiP handler specific to each Arm platform. */ +uintptr_t plat_arm_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +#endif /* ARM_SIP_SVC_H */ diff --git a/include/plat/arm/common/arm_spm_def.h b/include/plat/arm/common/arm_spm_def.h new file mode 100644 index 0000000..c43583d --- /dev/null +++ b/include/plat/arm/common/arm_spm_def.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_SPM_DEF_H +#define ARM_SPM_DEF_H + +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> + +/* + * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the + * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition + * at the base of DRAM. + */ +#define ARM_SP_IMAGE_BASE BL32_BASE +#define ARM_SP_IMAGE_LIMIT BL32_LIMIT +/* The maximum size of the S-EL0 payload can be 3MB */ +#define ARM_SP_IMAGE_SIZE ULL(0x300000) + +#ifdef IMAGE_BL2 +/* SPM Payload memory. Mapped as RW in BL2. */ +#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ + ARM_SP_IMAGE_BASE, \ + ARM_SP_IMAGE_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +#ifdef IMAGE_BL31 +/* SPM Payload memory. Mapped as code in S-EL1 */ +#define ARM_SP_IMAGE_MMAP MAP_REGION2( \ + ARM_SP_IMAGE_BASE, \ + ARM_SP_IMAGE_BASE, \ + ARM_SP_IMAGE_SIZE, \ + MT_CODE | MT_SECURE | MT_USER, \ + PAGE_SIZE) +#endif + +/* + * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into + * S-EL0, so it is mapped with RW permission from EL3 and with RO permission + * from S-EL0. Placed after SPM Payload memory. + */ +#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) +#define PLAT_SPM_BUF_SIZE ULL(0x100000) + +#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ + PLAT_SPM_BUF_BASE, \ + PLAT_SPM_BUF_SIZE, \ + MT_RW_DATA | MT_SECURE) +#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ + PLAT_SPM_BUF_BASE, \ + PLAT_SPM_BUF_BASE, \ + PLAT_SPM_BUF_SIZE, \ + MT_RO_DATA | MT_SECURE | MT_USER,\ + PAGE_SIZE) + +/* + * Memory shared between Normal world and S-EL0 for passing data during service + * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and + * S-EL0. + */ +#define PLAT_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) +#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) +#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ + PLAT_SP_IMAGE_NS_BUF_BASE, \ + PLAT_SP_IMAGE_NS_BUF_BASE, \ + PLAT_SP_IMAGE_NS_BUF_SIZE, \ + MT_RW_DATA | MT_NS | MT_USER, \ + PAGE_SIZE) + +/* + * RW memory, which uses the remaining Trusted DRAM. Placed after the memory + * shared between Secure and Non-secure worlds, or after the platform specific + * buffers, if defined. First there is the stack memory for all CPUs and then + * there is the common heap memory. Both are mapped with RW permissions. + */ +#define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE +#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) +#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ + PLAT_SP_IMAGE_STACK_PCPU_SIZE) + +#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ + ARM_SP_IMAGE_STACK_TOTAL_SIZE) +#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) + +#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ + PLAT_SP_IMAGE_STACK_BASE, \ + PLAT_SP_IMAGE_STACK_BASE, \ + (ARM_SP_IMAGE_LIMIT - \ + PLAT_SP_IMAGE_STACK_BASE), \ + MT_RW_DATA | MT_SECURE | MT_USER,\ + PAGE_SIZE) + +/* Total number of memory regions with distinct properties */ +#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 + +/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ +#define PLAT_SPM_COOKIE_0 ULL(0) +#define PLAT_SPM_COOKIE_1 ULL(0) + +#endif /* ARM_SPM_DEF_H */ diff --git a/include/plat/arm/common/arm_tzc_dram.ld.S b/include/plat/arm/common/arm_tzc_dram.ld.S new file mode 100644 index 0000000..c790bb9 --- /dev/null +++ b/include/plat/arm/common/arm_tzc_dram.ld.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef ARM_TZC_DRAM_LD_S +#define ARM_TZC_DRAM_LD_S + +#include <lib/xlat_tables/xlat_tables_defs.h> + +MEMORY { + EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE +} + +SECTIONS +{ + . = ARM_EL3_TZC_DRAM1_BASE; + ASSERT(. == ALIGN(PAGE_SIZE), + "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.") + .el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { + __EL3_SEC_DRAM_START__ = .; + *(.arm_el3_tzc_dram) + __EL3_SEC_DRAM_UNALIGNED_END__ = .; + + . = ALIGN(PAGE_SIZE); + __EL3_SEC_DRAM_END__ = .; + } >EL3_SEC_DRAM +} + +#endif /* ARM_TZC_DRAM_LD_S */ diff --git a/include/plat/arm/common/fconf_arm_sp_getter.h b/include/plat/arm/common/fconf_arm_sp_getter.h new file mode 100644 index 0000000..96ed963 --- /dev/null +++ b/include/plat/arm/common/fconf_arm_sp_getter.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_ARM_SP_GETTER_H +#define FCONF_ARM_SP_GETTER_H + +#include <common/tbbr/tbbr_img_def.h> +#include <lib/fconf/fconf.h> +#include <tools_share/uuid.h> + +/* arm_sp getter */ +#define arm__sp_getter(prop) arm_sp.prop + +#define ARM_SP_MAX_SIZE U(0xb0000) +#define ARM_SP_OWNER_NAME_LEN U(8) + +struct arm_sp_t { + unsigned int number_of_sp; + union uuid_helper_t uuids[MAX_SP_IDS]; + uintptr_t load_addr[MAX_SP_IDS]; + char owner[MAX_SP_IDS][ARM_SP_OWNER_NAME_LEN]; +}; + +int fconf_populate_arm_sp(uintptr_t config); + +extern struct arm_sp_t arm_sp; + +extern bl_mem_params_node_t sp_mem_params_descs[MAX_SP_IDS]; + +#endif /* FCONF_ARM_SP_GETTER_H */ diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h new file mode 100644 index 0000000..d45c269 --- /dev/null +++ b/include/plat/arm/common/fconf_ethosn_getter.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_ETHOSN_GETTER_H +#define FCONF_ETHOSN_GETTER_H + +#include <assert.h> +#include <stdbool.h> + +#include <lib/fconf/fconf.h> + +#define hw_config__ethosn_config_getter(prop) ethosn_config.prop +#define hw_config__ethosn_device_getter(dev_idx) __extension__ ({ \ + assert(dev_idx < ethosn_config.num_devices); \ + ðosn_config.devices[dev_idx]; \ +}) + +#define ETHOSN_DEV_NUM_MAX U(2) +#define ETHOSN_DEV_CORE_NUM_MAX U(8) +#define ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX U(16) + +struct ethosn_allocator_t { + uint32_t stream_id; +}; + +struct ethosn_main_allocator_t { + struct ethosn_allocator_t firmware; + struct ethosn_allocator_t working_data; +}; + +struct ethosn_asset_allocator_t { + struct ethosn_allocator_t command_stream; + struct ethosn_allocator_t weight_data; + struct ethosn_allocator_t buffer_data; + struct ethosn_allocator_t intermediate_data; +}; + +struct ethosn_core_t { + uint64_t addr; + struct ethosn_main_allocator_t main_allocator; +}; + +struct ethosn_device_t { + bool has_reserved_memory; + uint64_t reserved_memory_addr; + uint32_t num_cores; + struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX]; + uint32_t num_allocators; + struct ethosn_asset_allocator_t asset_allocators[ETHOSN_DEV_ASSET_ALLOCATOR_NUM_MAX]; +}; + +struct ethosn_config_t { + uint32_t num_devices; + struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX]; +}; + +extern struct ethosn_config_t ethosn_config; + +#endif /* FCONF_ETHOSN_GETTER_H */ diff --git a/include/plat/arm/common/fconf_nv_cntr_getter.h b/include/plat/arm/common/fconf_nv_cntr_getter.h new file mode 100644 index 0000000..80a6000 --- /dev/null +++ b/include/plat/arm/common/fconf_nv_cntr_getter.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_NV_CNTR_GETTER_H +#define FCONF_NV_CNTR_GETTER_H + +#include <common/nv_cntr_ids.h> +#include <lib/fconf/fconf.h> + +#define cot__nv_cntr_addr_getter(id) nv_cntr_base_addr[id] + +extern uintptr_t nv_cntr_base_addr[MAX_NV_CTR_IDS]; + +#endif /* FCONF_NV_CNTR_GETTER_H */ diff --git a/include/plat/arm/common/fconf_sdei_getter.h b/include/plat/arm/common/fconf_sdei_getter.h new file mode 100644 index 0000000..e0a97a6 --- /dev/null +++ b/include/plat/arm/common/fconf_sdei_getter.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_SDEI_GETTER_H +#define FCONF_SDEI_GETTER_H + +#include <lib/fconf/fconf.h> + +#include <platform_def.h> + +#define sdei__dyn_config_getter(id) sdei_dyn_config.id + +struct sdei_dyn_config_t { + uint32_t private_ev_cnt; + int32_t private_ev_nums[PLAT_SDEI_DP_EVENT_MAX_CNT]; + unsigned int private_ev_intrs[PLAT_SDEI_DP_EVENT_MAX_CNT]; + unsigned int private_ev_flags[PLAT_SDEI_DP_EVENT_MAX_CNT]; + uint32_t shared_ev_cnt; + int32_t shared_ev_nums[PLAT_SDEI_DS_EVENT_MAX_CNT]; + unsigned int shared_ev_intrs[PLAT_SDEI_DS_EVENT_MAX_CNT]; + unsigned int shared_ev_flags[PLAT_SDEI_DS_EVENT_MAX_CNT]; +}; + +int fconf_populate_sdei_dyn_config(uintptr_t config); + +extern struct sdei_dyn_config_t sdei_dyn_config; + +#endif /* FCONF_SDEI_GETTER_H */ diff --git a/include/plat/arm/common/fconf_sec_intr_config.h b/include/plat/arm/common/fconf_sec_intr_config.h new file mode 100644 index 0000000..5d6b594 --- /dev/null +++ b/include/plat/arm/common/fconf_sec_intr_config.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FCONF_SEC_INTR_CONFIG_H +#define FCONF_SEC_INTR_CONFIG_H + +#include <lib/fconf/fconf.h> + +#include <platform_def.h> + +#define hw_config__sec_intr_prop_getter(id) sec_intr_prop.id + +#define SEC_INT_COUNT_MAX U(15) + +struct sec_intr_prop_t { + interrupt_prop_t descriptor[SEC_INT_COUNT_MAX]; + uint32_t count; +}; + +int fconf_populate_sec_intr_config(uintptr_t config); + +extern struct sec_intr_prop_t sec_intr_prop; + +#endif /* FCONF_SEC_INTR_CONFIG_H */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h new file mode 100644 index 0000000..0fb06a6 --- /dev/null +++ b/include/plat/arm/common/plat_arm.h @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLAT_ARM_H +#define PLAT_ARM_H + +#include <stdbool.h> +#include <stdint.h> + +#include <drivers/arm/tzc_common.h> +#include <lib/bakery_lock.h> +#include <lib/cassert.h> +#include <lib/el3_runtime/cpu_data.h> +#include <lib/spinlock.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_compat.h> + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct meminfo; +struct image_info; +struct bl_params; + +typedef struct arm_tzc_regions_info { + unsigned long long base; + unsigned long long end; + unsigned int sec_attr; + unsigned int nsaid_permissions; +} arm_tzc_regions_info_t; + +/******************************************************************************* + * Default mapping definition of the TrustZone Controller for ARM standard + * platforms. + * Configure: + * - Region 0 with no access; + * - Region 1 with secure access only; + * - the remaining DRAM regions access from the given Non-Secure masters. + ******************************************************************************/ + +#if ENABLE_RME +#define ARM_TZC_RME_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ + {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + /* Realm and Shared area share the same PAS */ \ + {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} +#endif + +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) +#define ARM_TZC_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ + TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ + PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} + +#elif ENABLE_RME +#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF, \ + {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ + TZC_REGION_S_RDWR, 0} +#else +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF +#endif + +#else +#define ARM_TZC_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ + TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} +#endif + +#define ARM_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ + assert_plat_arm_mmap_mismatch); \ + CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions); + +void arm_setup_romlib(void); + +#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) +/* + * Use this macro to instantiate lock before it is used in below + * arm_lock_xxx() macros + */ +#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) +#define ARM_LOCK_GET_INSTANCE (&arm_lock) + +#if !HW_ASSISTED_COHERENCY +#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) +#else +#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock +#endif +#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) + +/* + * These are wrapper macros to the Coherent Memory Bakery Lock API. + */ +#define arm_lock_init() bakery_lock_init(&arm_lock) +#define arm_lock_get() bakery_lock_get(&arm_lock) +#define arm_lock_release() bakery_lock_release(&arm_lock) + +#else + +/* + * Empty macros for all other BL stages other than BL31 and BL32 + */ +#define ARM_INSTANTIATE_LOCK static int arm_lock __unused +#define ARM_LOCK_GET_INSTANCE 0 +#define arm_lock_init() +#define arm_lock_get() +#define arm_lock_release() + +#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ + +#if ARM_RECOM_STATE_ID_ENC +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define ARM_LOCAL_PSTATE_WIDTH 4 +#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) + +#if PSCI_OS_INIT_MODE +#define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ + (ARM_LOCAL_PSTATE_WIDTH * \ + (PLAT_MAX_PWR_LVL + 1))) +#endif /* __PSCI_OS_INIT_MODE__ */ + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) +#else +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +/* Make composite power state parameter till power level 1 */ +#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ + arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* Make composite power state parameter till power level 2 */ +#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ + arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) + +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + +/* ARM State switch error codes */ +#define STATE_SW_E_PARAM (-2) +#define STATE_SW_E_DENIED (-3) + +/* plat_get_rotpk_info() flags */ +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 +#define ARM_ROTPK_DEVEL_ECDSA_ID 3 +#define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 +#define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 + +#define ARM_USE_DEVEL_ROTPK \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) + +/* IO storage utility functions */ +int arm_io_setup(void); + +/* Set image specification in IO block policy */ +int arm_set_image_source(unsigned int image_id, const char *part_name, + uintptr_t *dev_handle, uintptr_t *image_spec); +void arm_set_fip_addr(uint32_t active_fw_bank_idx); + +/* Security utility functions */ +void arm_tzc400_setup(uintptr_t tzc_base, + const arm_tzc_regions_info_t *tzc_regions); +struct tzc_dmc500_driver_data; +void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, + const arm_tzc_regions_info_t *tzc_regions); + +/* Console utility functions */ +void arm_console_boot_init(void); +void arm_console_boot_end(void); +void arm_console_runtime_init(void); +void arm_console_runtime_end(void); + +/* Systimer utility function */ +void arm_configure_sys_timer(void); + +/* PM utility functions */ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); +int arm_validate_psci_entrypoint(uintptr_t entrypoint); +int arm_validate_ns_entrypoint(uintptr_t entrypoint); +void arm_system_pwr_domain_save(void); +void arm_system_pwr_domain_resume(void); +int arm_psci_read_mem_protect(int *enabled); +int arm_nor_psci_write_mem_protect(int val); +void arm_nor_psci_do_static_mem_protect(void); +void arm_nor_psci_do_dyn_mem_protect(void); +int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); + +/* Topology utility function */ +int arm_check_mpidr(u_register_t mpidr); + +/* BL1 utility functions */ +void arm_bl1_early_platform_setup(void); +void arm_bl1_platform_setup(void); +void arm_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); +void arm_bl2_platform_setup(void); +void arm_bl2_plat_arch_setup(void); +uint32_t arm_get_spsr_for_bl32_entry(void); +uint32_t arm_get_spsr_for_bl33_entry(void); +int arm_bl2_plat_handle_post_image_load(unsigned int image_id); +int arm_bl2_handle_post_image_load(unsigned int image_id); +struct bl_params *arm_get_next_bl_params(void); + +/* BL2 at EL3 functions */ +void arm_bl2_el3_early_platform_setup(void); +void arm_bl2_el3_plat_arch_setup(void); + +/* BL2U utility functions */ +void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, + void *plat_info); +void arm_bl2u_platform_setup(void); +void arm_bl2u_plat_arch_setup(void); + +/* BL31 utility functions */ +void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2); +void arm_bl31_platform_setup(void); +void arm_bl31_plat_runtime_setup(void); +void arm_bl31_plat_arch_setup(void); + +/* TSP utility functions */ +void arm_tsp_early_platform_setup(void); + +/* SP_MIN utility functions */ +void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2); +void arm_sp_min_plat_runtime_setup(void); +void arm_sp_min_plat_arch_setup(void); + +/* FIP TOC validity check */ +bool arm_io_is_toc_valid(void); + +/* Utility functions for Dynamic Config */ +void arm_bl2_dyn_cfg_init(void); +void arm_bl1_set_mbedtls_heap(void); +int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); + +#if MEASURED_BOOT +int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); +int arm_set_nt_fw_info( +/* + * Currently OP-TEE does not support reading DTBs from Secure memory + * and this option should be removed when feature is supported. + */ +#ifdef SPD_opteed + uintptr_t log_addr, +#endif + size_t log_size, uintptr_t *ns_log_addr); +int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, + size_t log_max_size); +int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, + size_t *log_max_size); +#endif /* MEASURED_BOOT */ + +/* + * Free the memory storing initialization code only used during an images boot + * time so it can be reclaimed for runtime data + */ +void arm_free_init_memory(void); + +/* + * Make the higher level translation tables read-only + */ +void arm_xlat_make_tables_readonly(void); + +/* + * Mandatory functions required in ARM standard platforms + */ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); +void plat_arm_gic_driver_init(void); +void plat_arm_gic_init(void); +void plat_arm_gic_cpuif_enable(void); +void plat_arm_gic_cpuif_disable(void); +void plat_arm_gic_redistif_on(void); +void plat_arm_gic_redistif_off(void); +void plat_arm_gic_pcpu_init(void); +void plat_arm_gic_save(void); +void plat_arm_gic_resume(void); +void plat_arm_security_setup(void); +void plat_arm_pwrc_setup(void); +void plat_arm_interconnect_init(void); +void plat_arm_interconnect_enter_coherency(void); +void plat_arm_interconnect_exit_coherency(void); +void plat_arm_program_trusted_mailbox(uintptr_t address); +bool plat_arm_bl1_fwu_needed(void); +__dead2 void plat_arm_error_handler(int err); +__dead2 void plat_arm_system_reset(void); + +/* + * Optional functions in ARM standard platforms + */ +void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); +int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, + unsigned int *flags); + +#if ARM_PLAT_MT +unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); +#endif + +/* + * This function is called after loading SCP_BL2 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); + +/* + * Optional functions required in ARM standard platforms + */ +void plat_arm_io_setup(void); +int plat_arm_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_arm_calc_core_pos(u_register_t mpidr); +const mmap_region_t *plat_arm_get_mmap(void); + +/* Allow platform to override psci_pm_ops during runtime */ +const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); + +/* Execution state switch in ARM platforms */ +int arm_execution_state_switch(unsigned int smc_fid, + uint32_t pc_hi, + uint32_t pc_lo, + uint32_t cookie_hi, + uint32_t cookie_lo, + void *handle); + +/* Optional functions for SP_MIN */ +void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3); + +/* global variables */ +extern plat_psci_ops_t plat_arm_psci_pm_ops; +extern const mmap_region_t plat_arm_mmap[]; +extern const unsigned int arm_pm_idle_states[]; + +/* secure watchdog */ +void plat_arm_secure_wdt_start(void); +void plat_arm_secure_wdt_stop(void); +void plat_arm_secure_wdt_refresh(void); + +/* Get SOC-ID of ARM platform */ +uint32_t plat_arm_get_soc_id(void); + +#endif /* PLAT_ARM_H */ diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h new file mode 100644 index 0000000..0f4e573 --- /dev/null +++ b/include/plat/arm/common/smccc_def.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef SMCCC_DEF_H +#define SMCCC_DEF_H + +/* Defines used to retrieve ARM SOC revision */ +#define ARM_SOC_CONTINUATION_CODE U(0x4) +#define ARM_SOC_IDENTIFICATION_CODE U(0x3B) + +#endif /* SMCCC_DEF_H */ diff --git a/include/plat/arm/css/common/aarch64/css_macros.S b/include/plat/arm/css/common/aarch64/css_macros.S new file mode 100644 index 0000000..85a7044 --- /dev/null +++ b/include/plat/arm/css/common/aarch64/css_macros.S @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef CSS_MACROS_S +#define CSS_MACROS_S + +#include <arm_macros.S> +#include <platform_def.h> + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro css_print_gic_regs + mov_imm x16, PLAT_ARM_GICD_BASE + mov_imm x17, PLAT_ARM_GICC_BASE + arm_print_gic_regs + .endm + +#endif /* CSS_MACROS_S */ diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h new file mode 100644 index 0000000..f87f857 --- /dev/null +++ b/include/plat/arm/css/common/css_def.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSS_DEF_H +#define CSS_DEF_H + +#include <common/interrupt_props.h> +#include <drivers/arm/gic_common.h> +#include <drivers/arm/tzc400.h> + +/************************************************************************* + * Definitions common to all ARM Compute SubSystems (CSS) + *************************************************************************/ +#define NSROM_BASE 0x1f000000 +#define NSROM_SIZE 0x00001000 + +/* Following covers CSS Peripherals excluding NSROM and NSRAM */ +#define CSS_DEVICE_BASE 0x20000000 +#define CSS_DEVICE_SIZE 0x0e000000 + +/* System Security Control Registers */ +#define SSC_REG_BASE 0x2a420000 +#define SSC_GPRETN (SSC_REG_BASE + 0x030) + +/* System ID Registers Unit */ +#define SID_REG_BASE 0x2a4a0000 +#define SID_SYSTEM_ID_OFFSET 0x40 +#define SID_SYSTEM_CFG_OFFSET 0x70 +#define SID_NODE_ID_OFFSET 0x60 +#define SID_CHIP_ID_MASK 0xFF +#define SID_MULTI_CHIP_MODE_MASK 0x100 +#define SID_MULTI_CHIP_MODE_SHIFT 8 + +/* The slave_bootsecure controls access to GPU, DMC and CS. */ +#define CSS_NIC400_SLAVE_BOOTSECURE 8 + +/* Interrupt handling constants */ +#define CSS_IRQ_MHU 69 +#define CSS_IRQ_GPU_SMMU_0 71 +#define CSS_IRQ_TZC 80 +#define CSS_IRQ_TZ_WDOG 86 +#define CSS_IRQ_SEC_SYS_TIMER 91 + +/* MHU register offsets */ +#define MHU_CPU_INTR_S_SET_OFFSET 0x308 + +/* + * Define a list of Group 1 Secure interrupt properties as per GICv3 + * terminology. On a GICv2 system or mode, the interrupts will be treated as + * Group 0 interrupts. + */ +#define CSS_G1S_INT_PROPS(grp) \ + INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#define CSS_G1S_IRQ_PROPS(grp) \ + CSS_G1S_INT_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL) + +#if CSS_USE_SCMI_SDS_DRIVER +/* Memory region for shared data storage */ +#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE +#define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ +/* + * The SCMI Channel is placed right after the SDS region + */ +#define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) +#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET + +/* Trusted mailbox base address common to all CSS */ +/* If SDS is present, then mailbox is at top of SRAM */ +#define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) + +/* Number of retries for SCP_RAM_READY flag */ +#define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ + +#else +/* + * SCP <=> AP boot configuration + * + * The SCP/AP boot configuration is a 32-bit word located at a known offset from + * the start of the Trusted SRAM. + * + * Note that the value stored at this address is only valid at boot time, before + * the SCP_BL2 image is transferred to SCP. + */ +#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE + +/* Trusted mailbox base address common to all CSS */ +/* If SDS is not present, then the mailbox is at the bottom of SRAM */ +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + +#endif /* CSS_USE_SCMI_SDS_DRIVER */ + +#define CSS_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_DEVICE_BASE, \ + CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define CSS_MAP_NSRAM MAP_REGION_FLAT( \ + NSRAM_BASE, \ + NSRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_NS) + +#if defined(IMAGE_BL2U) +#define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ + SCP_BL2U_BASE, \ + SCP_BL2U_LIMIT \ + - SCP_BL2U_BASE,\ + MT_RW_DATA | MT_SECURE) +#endif + +/* Platform ID address */ +#define SSC_VERSION_OFFSET 0x040 + +#define SSC_VERSION_CONFIG_SHIFT 28 +#define SSC_VERSION_MAJOR_REV_SHIFT 24 +#define SSC_VERSION_MINOR_REV_SHIFT 20 +#define SSC_VERSION_DESIGNER_ID_SHIFT 12 +#define SSC_VERSION_PART_NUM_SHIFT 0x0 +#define SSC_VERSION_CONFIG_MASK 0xf +#define SSC_VERSION_MAJOR_REV_MASK 0xf +#define SSC_VERSION_MINOR_REV_MASK 0xf +#define SSC_VERSION_DESIGNER_ID_MASK 0xff +#define SSC_VERSION_PART_NUM_MASK 0xfff + +#define SID_SYSTEM_ID_PART_NUM_MASK 0xfff + +/* SSC debug configuration registers */ +#define SSC_DBGCFG_SET 0x14 +#define SSC_DBGCFG_CLR 0x18 + +#define SPNIDEN_INT_CLR_SHIFT 4 +#define SPNIDEN_SEL_SET_SHIFT 5 +#define SPIDEN_INT_CLR_SHIFT 6 +#define SPIDEN_SEL_SET_SHIFT 7 + +#ifndef __ASSEMBLER__ + +/* SSC_VERSION related accessors */ + +/* Returns the part number of the platform */ +#define GET_SSC_VERSION_PART_NUM(val) \ + (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ + SSC_VERSION_PART_NUM_MASK) + +/* Returns the configuration number of the platform */ +#define GET_SSC_VERSION_CONFIG(val) \ + (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ + SSC_VERSION_CONFIG_MASK) + +#endif /* __ASSEMBLER__ */ + +/************************************************************************* + * Required platform porting definitions common to all + * ARM Compute SubSystems (CSS) + ************************************************************************/ + +/* + * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there + * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). + * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load + * an SCP_BL2/SCP_BL2U image. + */ +#if CSS_LOAD_SCP_IMAGES + +#if ARM_BL31_IN_DRAM +#error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" +#endif + +/* + * Load address of SCP_BL2 in CSS platform ports + * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 + * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and + * BL31 is loaded over the top. + */ +#define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) +#define SCP_BL2_LIMIT BL2_BASE + +#define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) +#define SCP_BL2U_LIMIT BL2_BASE +#endif /* CSS_LOAD_SCP_IMAGES */ + +/* Load address of Non-Secure Image for CSS platform ports */ +#define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) + +/* + * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP + * command + */ +#define CSS_CLUSTER_PWR_STATE_ON 0 +#define CSS_CLUSTER_PWR_STATE_OFF 3 + +#define CSS_CPU_PWR_STATE_ON 1 +#define CSS_CPU_PWR_STATE_OFF 0 +#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) + +#endif /* CSS_DEF_H */ diff --git a/include/plat/arm/css/common/css_pm.h b/include/plat/arm/css/common/css_pm.h new file mode 100644 index 0000000..84e6b38 --- /dev/null +++ b/include/plat/arm/css/common/css_pm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CSS_PM_H +#define CSS_PM_H + +#include <cdefs.h> +#include <stdint.h> + +#include <lib/psci/psci.h> + +/* SGI used to trigger per-core power down request */ +#define CSS_CPU_PWR_DOWN_REQ_INTR ARM_IRQ_SEC_SGI_7 + +/* Macros to read the CSS power domain state */ +#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] +#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] + +static inline unsigned int css_system_pwr_state(const psci_power_state_t *state) +{ +#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) + return state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL]; +#else + return 0; +#endif +} + +int css_pwr_domain_on(u_register_t mpidr); +void css_pwr_domain_on_finish(const psci_power_state_t *target_state); +void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state); +void css_pwr_domain_off(const psci_power_state_t *target_state); +void css_pwr_domain_suspend(const psci_power_state_t *target_state); +void css_pwr_domain_suspend_finish( + const psci_power_state_t *target_state); +void __dead2 css_system_off(void); +void __dead2 css_system_reset(void); +void css_cpu_standby(plat_local_state_t cpu_state); +void css_get_sys_suspend_power_state(psci_power_state_t *req_state); +int css_node_hw_state(u_register_t mpidr, unsigned int power_level); +void css_setup_cpu_pwr_down_intr(void); +int css_reboot_interrupt_handler(uint32_t intr_raw, uint32_t flags, + void *handle, void *cookie); + +/* + * This mapping array has to be exported by the platform. Each element at + * a given index maps that core to an SCMI power domain. + */ +extern const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[]; + +#define SCMI_DOMAIN_ID_MASK U(0xFFFF) +#define SCMI_CHANNEL_ID_MASK U(0xFFFF) +#define SCMI_CHANNEL_ID_SHIFT U(16) + +#define SET_SCMI_CHANNEL_ID(n) (((n) & SCMI_CHANNEL_ID_MASK) << \ + SCMI_CHANNEL_ID_SHIFT) +#define SET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) +#define GET_SCMI_CHANNEL_ID(n) (((n) >> SCMI_CHANNEL_ID_SHIFT) & \ + SCMI_CHANNEL_ID_MASK) +#define GET_SCMI_DOMAIN_ID(n) ((n) & SCMI_DOMAIN_ID_MASK) + +#endif /* CSS_PM_H */ diff --git a/include/plat/arm/soc/common/soc_css.h b/include/plat/arm/soc/common/soc_css.h new file mode 100644 index 0000000..469928d --- /dev/null +++ b/include/plat/arm/soc/common/soc_css.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOC_CSS_H +#define SOC_CSS_H + +/* + * Utility functions for ARM CSS SoCs + */ +void soc_css_init_nic400(void); +void soc_css_init_pcie(void); + +static inline void soc_css_security_setup(void) +{ + soc_css_init_nic400(); + soc_css_init_pcie(); +} + +#endif /* SOC_CSS_H */ diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h new file mode 100644 index 0000000..b4b6ba8 --- /dev/null +++ b/include/plat/arm/soc/common/soc_css_def.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOC_CSS_DEF_H +#define SOC_CSS_DEF_H + +#include <lib/utils_def.h> +#include <plat/common/common_def.h> + +/* + * Definitions common to all ARM CSS SoCs + */ + +/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ +#define SOC_CSS_DEVICE_BASE 0x40000000 +#define SOC_CSS_DEVICE_SIZE 0x40000000 +#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 + +/* PL011 UART related constants */ +#define SOC_CSS_UART0_BASE 0x7ff80000 +#define SOC_CSS_UART1_BASE 0x7ff70000 + +#define SOC_CSS_UART0_CLK_IN_HZ 7372800 +#define SOC_CSS_UART1_CLK_IN_HZ 7372800 + +/* SoC NIC-400 Global Programmers View (GPV) */ +#define SOC_CSS_NIC400_BASE 0x7fd00000 + +#define SOC_CSS_NIC400_USB_EHCI 0 +#define SOC_CSS_NIC400_TLX_MASTER 1 +#define SOC_CSS_NIC400_USB_OHCI 2 +#define SOC_CSS_NIC400_PL354_SMC 3 +/* + * The apb4_bridge controls access to: + * - the PCIe configuration registers + * - the MMU units for USB, HDLCD and DMA + */ +#define SOC_CSS_NIC400_APB4_BRIDGE 4 + +/* Non-volatile counters */ +#define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 +#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) +#define TFW_NVCTR_SIZE 4 +#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) +#define NTFW_CTR_SIZE 4 + +/* Keys */ +#define SOC_KEYS_BASE 0x7fe80000 +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE 32 +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE 16 +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE 32 + +#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + +/* + * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. + */ +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) + +/* + * Required platform porting definitions common to all ARM CSS SoCs + */ +#if JUNO_AARCH32_EL3_RUNTIME +/* + * Following change is required to initialize TZC + * for enabling access to the HI_VECTOR (0xFFFF0000) + * location needed for JUNO AARCH32 support. + */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) +#else +/* 2MB used for SCP DDR retraining */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) +#endif + +#endif /* SOC_CSS_DEF_H */ diff --git a/include/plat/brcm/common/bcm_console.h b/include/plat/brcm/common/bcm_console.h new file mode 100644 index 0000000..7b653d8 --- /dev/null +++ b/include/plat/brcm/common/bcm_console.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BCM_CONSOLE_H +#define BCM_CONSOLE_H + +void bcm_console_boot_init(void); +void bcm_console_boot_end(void); +void bcm_console_runtime_init(void); +void bcm_console_runtime_end(void); + +#endif /* BCM_CONSOLE_H */ diff --git a/include/plat/brcm/common/bcm_elog.h b/include/plat/brcm/common/bcm_elog.h new file mode 100644 index 0000000..ea4b169 --- /dev/null +++ b/include/plat/brcm/common/bcm_elog.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BCM_ELOG_H +#define BCM_ELOG_H + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +#if defined(BCM_ELOG) && (defined(IMAGE_BL2) || defined(IMAGE_BL31)) +int bcm_elog_init(void *base, uint32_t size, unsigned int level); +void bcm_elog_exit(void); +int bcm_elog_copy_log(void *dst, uint32_t max_size); +void bcm_elog(const char *fmt, ...); +#else +static inline int bcm_elog_init(void *base, uint32_t size, + unsigned int level) +{ + return 0; +} +static inline void bcm_elog_exit(void) +{ +} +static inline int bcm_elog_copy_log(void *dst, uint32_t max_size) +{ + return 0; +} +static inline void bcm_elog(const char *fmt, ...) +{ +} +#endif /* BCM_ELOG */ + +#endif /* __ASSEMBLER__ */ +#endif /* BCM_ELOG_H */ diff --git a/include/plat/brcm/common/brcm_def.h b/include/plat/brcm/common/brcm_def.h new file mode 100644 index 0000000..c9137bc --- /dev/null +++ b/include/plat/brcm/common/brcm_def.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016 - 2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BRCM_DEF_H +#define BRCM_DEF_H + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables.h> +#include <plat/common/common_def.h> + +#include <platform_def.h> + +#define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(32) +#define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(32) + +#define BL11_DAUTH_ID 0x796C51ab +#define BL11_DAUTH_BASE BL11_RW_BASE + +/* We keep a table at the end of ROM for function pointers */ +#define ROM_TABLE_SIZE 32 +#define BL1_ROM_TABLE (BL1_RO_LIMIT - ROM_TABLE_SIZE) + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ +#define BRCM_TZC_DRAM1_SIZE ULL(0x01000000) + +#define BRCM_SCP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ + BRCM_DRAM1_SIZE - \ + BRCM_SCP_TZC_DRAM1_SIZE) +#define BRCM_SCP_TZC_DRAM1_SIZE PLAT_BRCM_SCP_TZC_DRAM1_SIZE + +#define BRCM_AP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \ + BRCM_DRAM1_SIZE - \ + BRCM_TZC_DRAM1_SIZE) +#define BRCM_AP_TZC_DRAM1_SIZE (BRCM_TZC_DRAM1_SIZE - \ + BRCM_SCP_TZC_DRAM1_SIZE) + +#define BRCM_NS_DRAM1_BASE BRCM_DRAM1_BASE +#define BRCM_NS_DRAM1_SIZE (BRCM_DRAM1_SIZE - \ + BRCM_TZC_DRAM1_SIZE) + +#ifdef BRCM_SHARED_DRAM_BASE +#define BRCM_NS_SHARED_DRAM_BASE BRCM_SHARED_DRAM_BASE +#define BRCM_NS_SHARED_DRAM_SIZE BRCM_SHARED_DRAM_SIZE +#endif + +#define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + BRCM_SHARED_RAM_BASE, \ + BRCM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + BRCM_NS_DRAM1_BASE, \ + BRCM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BRCM_SHARED_DRAM_BASE +#define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \ + BRCM_NS_SHARED_DRAM_BASE, \ + BRCM_NS_SHARED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) +#endif + +#ifdef BRCM_EXT_SRAM_BASE +#define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \ + BRCM_EXT_SRAM_BASE, \ + BRCM_EXT_SRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\ + NAND_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\ + QSPI_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \ + HSLS_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \ + CCN_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \ + GIC500_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#ifdef PERIPH0_BASE +#define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \ + PERIPH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef PERIPH1_BASE +#define PERIPH1_REGION MAP_REGION_FLAT(PERIPH1_BASE, \ + PERIPH1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef PERIPH2_BASE +#define PERIPH2_REGION MAP_REGION_FLAT(PERIPH2_BASE, \ + PERIPH2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#if BRCM_BL31_IN_DRAM +#if IMAGE_BL2 +#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_BRCM_MAX_BL31_SIZE,\ + MT_DEVICE | MT_RW | MT_SECURE) +#else +#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_BRCM_MAX_BL31_SIZE,\ + MT_MEMORY | MT_RW | MT_SECURE) +#endif +#endif + +#if defined(USB_BASE) && defined(DRIVER_USB_ENABLE) +#define USB_REGION MAP_REGION_FLAT( \ + USB_BASE, \ + USB_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef USE_CRMU_SRAM +#define CRMU_SRAM_REGION MAP_REGION_FLAT( \ + CRMU_SRAM_BASE, \ + CRMU_SRAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define BRCM_BL_REGIONS 3 +#else +#define BRCM_BL_REGIONS 2 +#endif + +#endif /* BRCM_DEF_H */ diff --git a/include/plat/brcm/common/plat_brcm.h b/include/plat/brcm/common/plat_brcm.h new file mode 100644 index 0000000..66ed2cb --- /dev/null +++ b/include/plat/brcm/common/plat_brcm.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019-2020, Broadcom + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_BRCM_H +#define PLAT_BRCM_H + +#include <stdint.h> + +#include <lib/cassert.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables.h> + +#include <platform_def.h> + +struct image_info; + +/* Global variables */ +extern const mmap_region_t plat_brcm_mmap[]; + +uint32_t brcm_get_spsr_for_bl32_entry(void); +uint32_t brcm_get_spsr_for_bl33_entry(void); +const mmap_region_t *plat_brcm_get_mmap(void); +int bcm_bl2_handle_scp_bl2(struct image_info *image_info); +unsigned int plat_brcm_calc_core_pos(u_register_t mpidr); +void plat_brcm_gic_driver_init(void); +void plat_brcm_gic_init(void); +void plat_brcm_gic_cpuif_enable(void); +void plat_brcm_gic_cpuif_disable(void); +void plat_brcm_gic_pcpu_init(void); +void plat_brcm_gic_redistif_on(void); +void plat_brcm_gic_redistif_off(void); +void plat_brcm_interconnect_init(void); +void plat_brcm_interconnect_enter_coherency(void); +void plat_brcm_interconnect_exit_coherency(void); +void plat_brcm_io_setup(void); +void plat_brcm_process_flags(uint16_t plat_toc_flags); + +#endif /* PLAT_BRCM_H */ diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h new file mode 100644 index 0000000..1d3ac15 --- /dev/null +++ b/include/plat/common/common_def.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef COMMON_DEF_H +#define COMMON_DEF_H + +#include <common/bl_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> + +#include <platform_def.h> + +#define SZ_32 U(0x00000020) +#define SZ_64 U(0x00000040) +#define SZ_128 U(0x00000080) +#define SZ_256 U(0x00000100) +#define SZ_512 U(0x00000200) + +#define SZ_1K U(0x00000400) +#define SZ_2K U(0x00000800) +#define SZ_4K U(0x00001000) +#define SZ_8K U(0x00002000) +#define SZ_16K U(0x00004000) +#define SZ_32K U(0x00008000) +#define SZ_64K U(0x00010000) +#define SZ_128K U(0x00020000) +#define SZ_256K U(0x00040000) +#define SZ_512K U(0x00080000) + +#define SZ_1M U(0x00100000) +#define SZ_2M U(0x00200000) +#define SZ_4M U(0x00400000) +#define SZ_8M U(0x00800000) +#define SZ_16M U(0x01000000) +#define SZ_32M U(0x02000000) +#define SZ_64M U(0x04000000) +#define SZ_128M U(0x08000000) +#define SZ_256M U(0x10000000) +#define SZ_512M U(0x20000000) + +#define SZ_1G U(0x40000000) +#define SZ_2G U(0x80000000) + +/****************************************************************************** + * Required platform porting definitions that are expected to be common to + * all platforms + *****************************************************************************/ + +/* + * Platform binary types for linking + */ +#ifdef __aarch64__ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 +#else +#define PLATFORM_LINKER_FORMAT "elf32-littlearm" +#define PLATFORM_LINKER_ARCH arm +#endif /* __aarch64__ */ + +/* + * Generic platform constants + */ +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL2_IMAGE_DESC { \ + .image_id = BL2_IMAGE_ID, \ + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ + VERSION_2, image_info_t, 0), \ + .image_info.image_base = BL2_BASE, \ + .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ + .ep_info.pc = BL2_BASE, \ +} + +/* + * The following constants identify the extents of the code & read-only data + * regions. These addresses are used by the MMU setup code and therefore they + * must be page-aligned. + * + * When the code and read-only data are mapped as a single atomic section + * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as + * code by specifying the read-only data section as empty. + * + * BL1 is different than the other images in the sense that its read-write data + * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at + * run-time. Therefore, the read-write data in ROM can be mapped with the same + * memory attributes as the read-only data region. For this reason, BL1 uses + * different macros. + * + * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it + * just points to the end of BL1's actual content in Trusted ROM. Therefore it + * needs to be rounded up to the next page size in order to map the whole last + * page of it with the right memory attributes. + */ +#if SEPARATE_CODE_AND_RODATA + +#define BL1_CODE_END BL_CODE_END +#define BL1_RO_DATA_BASE BL_RO_DATA_BASE +#define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) +#if BL2_IN_XIP_MEM +#define BL2_CODE_END BL_CODE_END +#define BL2_RO_DATA_BASE BL_RO_DATA_BASE +#define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE) +#endif /* BL2_IN_XIP_MEM */ +#else +#define BL_RO_DATA_BASE UL(0) +#define BL_RO_DATA_END UL(0) +#define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) +#if BL2_IN_XIP_MEM +#define BL2_RO_DATA_BASE UL(0) +#define BL2_RO_DATA_END UL(0) +#define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE) +#endif /* BL2_IN_XIP_MEM */ +#endif /* SEPARATE_CODE_AND_RODATA */ + +#if MEASURED_BOOT +/* + * Start critical data Ids from 2^32/2 reserving Ids from 0 to (2^32/2 - 1) + * for Images, It is a critical data Id base for all platforms. + */ +#define CRITICAL_DATA_ID_BASE U(0x80000000) +#endif /* MEASURED_BOOT */ + +#endif /* COMMON_DEF_H */ diff --git a/include/plat/common/plat_drtm.h b/include/plat/common/plat_drtm.h new file mode 100644 index 0000000..e96e719 --- /dev/null +++ b/include/plat/common/plat_drtm.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_DRTM_H +#define PLAT_DRTM_H + +#include <stdint.h> +#include <lib/xlat_tables/xlat_tables_compat.h> + +typedef struct { + uint8_t max_num_mem_prot_regions; + uint8_t dma_protection_support; +} plat_drtm_dma_prot_features_t; + +typedef struct { + bool tpm_based_hash_support; + uint32_t firmware_hash_algorithm; +} plat_drtm_tpm_features_t; + +typedef struct { + uint64_t region_address; + uint64_t region_size_type; +} __attribute__((packed)) drtm_mem_region_t; + +/* + * Memory region descriptor table structure as per DRTM beta0 section 3.13 + * Table 11 MEMORY_REGION_DESCRIPTOR_TABLE + */ +typedef struct { + uint16_t revision; + uint16_t reserved; + uint32_t num_regions; + drtm_mem_region_t region[]; +} __attribute__((packed)) drtm_memory_region_descriptor_table_t; + +/* platform specific address map functions */ +const mmap_region_t *plat_get_addr_mmap(void); + +/* platform-specific DMA protection functions */ +bool plat_has_non_host_platforms(void); +bool plat_has_unmanaged_dma_peripherals(void); +unsigned int plat_get_total_smmus(void); +void plat_enumerate_smmus(const uintptr_t **smmus_out, + size_t *smmu_count_out); +const plat_drtm_dma_prot_features_t *plat_drtm_get_dma_prot_features(void); +uint64_t plat_drtm_dma_prot_get_max_table_bytes(void); + +/* platform-specific TPM functions */ +const plat_drtm_tpm_features_t *plat_drtm_get_tpm_features(void); + +/* + * TODO: Implement these functions as per the platform use case, + * as of now none of the platform uses these functions + */ +uint64_t plat_drtm_get_min_size_normal_world_dce(void); +uint64_t plat_drtm_get_tcb_hash_table_size(void); +uint64_t plat_drtm_get_imp_def_dlme_region_size(void); +uint64_t plat_drtm_get_tcb_hash_features(void); + +/* DRTM error handling functions */ +int plat_set_drtm_error(uint64_t error_code); +int plat_get_drtm_error(uint64_t *error_code); + +/* + * Platform-specific function to ensure passed region lies within + * Non-Secure region of DRAM + */ +int plat_drtm_validate_ns_region(uintptr_t region_start, + size_t region_size); + +#endif /* PLAT_DRTM_H */ diff --git a/include/plat/common/plat_trng.h b/include/plat/common/plat_trng.h new file mode 100644 index 0000000..a9f73b6 --- /dev/null +++ b/include/plat/common/plat_trng.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_TRNG_H +#define PLAT_TRNG_H + +#include <tools_share/uuid.h> + +/* TRNG platform functions */ + +extern uuid_t plat_trng_uuid; +void plat_entropy_setup(void); +bool plat_get_entropy(uint64_t *out); + +#endif /* PLAT_TRNG_H */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h new file mode 100644 index 0000000..4d1b1c1 --- /dev/null +++ b/include/plat/common/platform.h @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_H +#define PLATFORM_H + +#include <stdint.h> + +#include <lib/psci/psci.h> +#if defined(SPD_spmd) +#include <services/spm_core_manifest.h> +#endif +#if ENABLE_RME +#include <services/rmm_core_manifest.h> +#endif +#include <drivers/fwu/fwu_metadata.h> +#if TRNG_SUPPORT +#include "plat_trng.h" +#endif /* TRNG_SUPPORT */ +#if DRTM_SUPPORT +#include "plat_drtm.h" +#endif /* DRTM_SUPPORT */ + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct auth_img_desc_s; +struct meminfo; +struct image_info; +struct entry_point_info; +struct image_desc; +struct bl_load_info; +struct bl_params; +struct mmap_region; +struct spm_mm_boot_info; +struct sp_res_desc; +struct rmm_manifest; +enum fw_enc_status_t; + +/******************************************************************************* + * plat_get_rotpk_info() flags + ******************************************************************************/ +#define ROTPK_IS_HASH (1 << 0) + +/* Flag used to skip verification of the certificate ROTPK while the platform + ROTPK is not deployed */ +#define ROTPK_NOT_DEPLOYED (1 << 1) + +static inline bool is_rotpk_flags_valid(unsigned int flags) +{ + unsigned int valid_flags = ROTPK_IS_HASH; + return (flags == ROTPK_NOT_DEPLOYED) || ((flags & ~valid_flags) == 0); +} + +/******************************************************************************* + * plat_get_enc_key_info() flags + ******************************************************************************/ +/* + * Flag used to notify caller that information provided in key buffer is an + * identifier rather than an actual key. + */ +#define ENC_KEY_IS_IDENTIFIER (1 << 0) + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void); + +int plat_get_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +uintptr_t plat_get_ns_image_entrypoint(void); +unsigned int plat_my_core_pos(void); +int plat_core_pos_by_mpidr(u_register_t mpidr); +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size); + +/******************************************************************************* + * Simple routine to determine whether a mpidr is valid or not. + ******************************************************************************/ +static inline bool is_valid_mpidr(u_register_t mpidr) +{ + int pos = plat_core_pos_by_mpidr(mpidr); + + if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) { + return false; + } + + return true; +} + +#if STACK_PROTECTOR_ENABLED +/* + * Return a new value to be used for the stack protection's canary. + * + * Ideally, this value is a random number that is impossible to predict by an + * attacker. + */ +u_register_t plat_get_stack_protector_canary(void); +#endif /* STACK_PROTECTOR_ENABLED */ + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +/******************************************************************************* + * Optional interrupt management functions, depending on chosen EL3 components. + ******************************************************************************/ +unsigned int plat_ic_get_running_priority(void); +int plat_ic_is_spi(unsigned int id); +int plat_ic_is_ppi(unsigned int id); +int plat_ic_is_sgi(unsigned int id); +unsigned int plat_ic_get_interrupt_active(unsigned int id); +void plat_ic_disable_interrupt(unsigned int id); +void plat_ic_enable_interrupt(unsigned int id); +bool plat_ic_has_interrupt_type(unsigned int type); +void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); +void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); +void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_ns_sgi(int sgi_num, u_register_t target); +void plat_ic_raise_s_el1_sgi(int sgi_num, u_register_t target); +void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, + u_register_t mpidr); +void plat_ic_set_interrupt_pending(unsigned int id); +void plat_ic_clear_interrupt_pending(unsigned int id); +unsigned int plat_ic_set_priority_mask(unsigned int mask); +unsigned int plat_ic_get_interrupt_id(unsigned int raw); + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +uintptr_t plat_get_my_stack(void); +void plat_report_exception(unsigned int exception_type); +void plat_report_prefetch_abort(unsigned int fault_address); +void plat_report_data_abort(unsigned int fault_address); +int plat_crash_console_init(void); +int plat_crash_console_putc(int c); +void plat_crash_console_flush(void); +void plat_error_handler(int err) __dead2; +void plat_panic_handler(void) __dead2; +void plat_system_reset(void) __dead2; +const char *plat_log_get_prefix(unsigned int log_level); +void bl2_plat_preload_setup(void); +int plat_try_next_boot_source(void); + +#if MEASURED_BOOT +int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data); +int plat_mboot_measure_critical_data(unsigned int critical_data_id, + const void *base, + size_t size); +int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len); +#else +static inline int plat_mboot_measure_image(unsigned int image_id __unused, + image_info_t *image_data __unused) +{ + return 0; +} +static inline int plat_mboot_measure_critical_data( + unsigned int critical_data_id __unused, + const void *base __unused, + size_t size __unused) +{ + return 0; +} +static inline int plat_mboot_measure_key(const void *pk_oid __unused, + const void *pk_ptr __unused, + size_t pk_len __unused) +{ + return 0; +} +#endif /* MEASURED_BOOT */ + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_early_platform_setup(void); +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); + +/******************************************************************************* + * Optional EL3 component functions in BL31 + ******************************************************************************/ + +/* SDEI platform functions */ +#if SDEI_SUPPORT +void plat_sdei_setup(void); +int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode); +void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr); +#endif + +void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, + void *handle, uint64_t flags); +void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, + void *handle, uint64_t flags); + +/* + * The following function is mandatory when the + * firmware update feature is used. + */ +int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size, + unsigned int flags); + +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +/* + * The following functions are used for image loading process in BL1. + */ +void bl1_plat_set_ep_info(unsigned int image_id, + struct entry_point_info *ep_info); +/* + * The following functions are mandatory when firmware update + * feature is used and optional otherwise. + */ +unsigned int bl1_plat_get_next_image_id(void); +struct image_desc *bl1_plat_get_image_desc(unsigned int image_id); + +/* + * The following functions are used by firmware update + * feature and may optionally be overridden. + */ +__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved); + +/* + * This BL1 function can be used by the platforms to update/use image + * information for a given `image_id`. + */ +int bl1_plat_handle_pre_image_load(unsigned int image_id); +int bl1_plat_handle_post_image_load(unsigned int image_id); + +#if MEASURED_BOOT +void bl1_plat_mboot_init(void); +void bl1_plat_mboot_finish(void); +#else +static inline void bl1_plat_mboot_init(void) +{ +} +static inline void bl1_plat_mboot_finish(void) +{ +} +#endif /* MEASURED_BOOT */ + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3); +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +/* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + */ +int bl2_plat_handle_pre_image_load(unsigned int image_id); +int bl2_plat_handle_post_image_load(unsigned int image_id); + +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ +#if MEASURED_BOOT +void bl2_plat_mboot_init(void); +void bl2_plat_mboot_finish(void); +#else +static inline void bl2_plat_mboot_init(void) +{ +} +static inline void bl2_plat_mboot_finish(void) +{ +} +#endif /* MEASURED_BOOT */ + +/******************************************************************************* + * Mandatory BL2 at EL3 functions: Must be implemented + * if RESET_TO_BL2 image is supported + ******************************************************************************/ +void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3); +void bl2_el3_plat_arch_setup(void); + +/******************************************************************************* + * Optional BL2 at EL3 functions (may be overridden) + ******************************************************************************/ +void bl2_el3_plat_prepare_exit(void); + +/******************************************************************************* + * Mandatory BL2U functions. + ******************************************************************************/ +void bl2u_early_platform_setup(struct meminfo *mem_layout, + void *plat_info); +void bl2u_plat_arch_setup(void); +void bl2u_platform_setup(void); + +/******************************************************************************* + * Conditionally mandatory BL2U functions for CSS platforms. + ******************************************************************************/ +/* + * This function is used to perform any platform-specific actions required to + * handle the BL2U_SCP firmware. + */ +int bl2u_plat_handle_scp_bl2u(void); + +/******************************************************************************* + * Mandatory BL31 functions + ******************************************************************************/ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3); +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +void bl31_plat_runtime_setup(void); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); + +/******************************************************************************* + * Mandatory PSCI functions (BL31) + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops); +const unsigned char *plat_get_power_domain_tree_desc(void); + +/******************************************************************************* + * Optional PSCI functions (BL31). + ******************************************************************************/ +void plat_psci_stat_accounting_start(const psci_power_state_t *state_info); +void plat_psci_stat_accounting_stop(const psci_power_state_t *state_info); +u_register_t plat_psci_stat_get_residency(unsigned int lvl, + const psci_power_state_t *state_info, + unsigned int last_cpu_idx); +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu); + +/******************************************************************************* + * Mandatory BL31 functions when ENABLE_RME=1 + ******************************************************************************/ +#if ENABLE_RME +int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, + uintptr_t hash, size_t hash_size); +int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, + unsigned int type); +size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared); +int plat_rmmd_load_manifest(struct rmm_manifest *manifest); +#endif + +/******************************************************************************* + * Optional BL31 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Optional BL32 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Trusted Board Boot functions + ******************************************************************************/ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr); +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr); +int plat_set_nv_ctr2(void *cookie, const struct auth_img_desc_s *img_desc, + unsigned int nv_ctr); +int get_mbedtls_heap_helper(void **heap_addr, size_t *heap_size); +int plat_get_enc_key_info(enum fw_enc_status_t fw_enc_status, uint8_t *key, + size_t *key_len, unsigned int *flags, + const uint8_t *img_id, size_t img_id_len); + +/******************************************************************************* + * Secure Partitions functions + ******************************************************************************/ +const struct mmap_region *plat_get_secure_partition_mmap(void *cookie); +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( + void *cookie); +int plat_spm_sp_rd_load(struct sp_res_desc *rd, const void *ptr, size_t size); +int plat_spm_sp_get_next_address(void **sp_base, size_t *sp_size, + void **rd_base, size_t *rd_size); +#if defined(SPD_spmd) +int plat_spm_core_manifest_load(spmc_manifest_attribute_t *manifest, + const void *pm_addr); +#endif +#if defined(SPMC_AT_EL3) +int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size); +#endif + +/******************************************************************************* + * Mandatory BL image load functions(may be overridden). + ******************************************************************************/ +/* + * This function returns pointer to the list of images that the + * platform has populated to load. + */ +struct bl_load_info *plat_get_bl_image_load_info(void); + +/* + * This function returns a pointer to the shared memory that the + * platform has kept aside to pass trusted firmware related + * information that next BL image could need. + */ +struct bl_params *plat_get_next_bl_params(void); + +/* + * This function flushes to main memory all the params that are + * passed to next image. + */ +void plat_flush_next_bl_params(void); + +/* + * The below function enable Trusted Firmware components like SPDs which + * haven't migrated to the new platform API to compile on platforms which + * have the compatibility layer disabled. + */ +unsigned int platform_core_pos_helper(unsigned long mpidr); + +/* + * Optional function to get SOC version + */ +int32_t plat_get_soc_version(void); + +/* + * Optional function to get SOC revision + */ +int32_t plat_get_soc_revision(void); + +/* + * Optional function to check for SMCCC function availability for platform + */ +int32_t plat_is_smccc_feature_available(u_register_t fid); + +/******************************************************************************* + * FWU platform specific functions + ******************************************************************************/ +int plat_fwu_set_metadata_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +void plat_fwu_set_images_source(const struct fwu_metadata *metadata); +uint32_t plat_fwu_get_boot_idx(void); + +/* + * Optional function to indicate if cache management operations can be + * performed. + */ +#if CONDITIONAL_CMO +uint64_t plat_can_cmo(void); +#else +static inline uint64_t plat_can_cmo(void) +{ + return 1; +} +#endif /* CONDITIONAL_CMO */ + +#endif /* PLATFORM_H */ diff --git a/include/plat/marvell/armada/a3k/common/armada_common.h b/include/plat/marvell/armada/a3k/common/armada_common.h new file mode 100644 index 0000000..c6953fb --- /dev/null +++ b/include/plat/marvell/armada/a3k/common/armada_common.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef ARMADA_COMMON_H +#define ARMADA_COMMON_H + +#include <stdint.h> + +#include <io_addr_dec.h> + +int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size); + +#endif /* ARMADA_COMMON_H */ diff --git a/include/plat/marvell/armada/a3k/common/board_marvell_def.h b/include/plat/marvell/armada/a3k/common/board_marvell_def.h new file mode 100644 index 0000000..bc3e04f --- /dev/null +++ b/include/plat/marvell/armada/a3k/common/board_marvell_def.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef BOARD_MARVELL_DEF_H +#define BOARD_MARVELL_DEF_H + +/* + * Required platform porting definitions common to all ARM + * development platforms + */ + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +#else +# define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif IMAGE_BL31 +# define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* + * PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if IMAGE_BLE +# define PLAT_MARVELL_MMAP_ENTRIES 3 +#endif +#if IMAGE_BL1 +# if TRUSTED_BOARD_BOOT +# define PLAT_MARVELL_MMAP_ENTRIES 7 +# else +# define PLAT_MARVELL_MMAP_ENTRIES 6 +# endif /* TRUSTED_BOARD_BOOT */ +#endif +#if IMAGE_BL2 +# define PLAT_MARVELL_MMAP_ENTRIES 8 +#endif +#if IMAGE_BL31 +#define PLAT_MARVELL_MMAP_ENTRIES 5 +#endif + +/* + * Platform specific page table and MMU setup constants + */ +#if IMAGE_BL1 +#define MAX_XLAT_TABLES 4 +#elif IMAGE_BLE +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL2 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL32 +# define MAX_XLAT_TABLES 4 +#endif + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a3k/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h new file mode 100644 index 0000000..1394c05 --- /dev/null +++ b/include/plat/marvell/armada/a3k/common/marvell_def.h @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MARVELL_DEF_H +#define MARVELL_DEF_H + +#include <platform_def.h> + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/common_def.h> + +/**************************************************************************** + * Definitions common to all MARVELL standard platforms + **************************************************************************** + */ +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLAT_MARVELL_NORTHB_COUNT 1 + +#define PLAT_MARVELL_CLUSTER_COUNT 1 + +#define MARVELL_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 +#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 +#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in Marvell platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define MARVELL_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define MARVELL_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. + * Valid for CPU and cluster power domains + */ +#define MARVELL_LOCAL_STATE_OFF 2 + +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE +#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ + MARVELL_SHARED_RAM_SIZE) +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ + MARVELL_SHARED_RAM_SIZE) + +#define MARVELL_DRAM_BASE ULL(0x0) +#define MARVELL_DRAM_SIZE ULL(0x20000000) +#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ + MARVELL_DRAM_SIZE - 1) + +#define MARVELL_IRQ_SEC_PHY_TIMER 29 + +#define MARVELL_IRQ_SEC_SGI_0 8 +#define MARVELL_IRQ_SEC_SGI_1 9 +#define MARVELL_IRQ_SEC_SGI_2 10 +#define MARVELL_IRQ_SEC_SGI_3 11 +#define MARVELL_IRQ_SEC_SGI_4 12 +#define MARVELL_IRQ_SEC_SGI_5 13 +#define MARVELL_IRQ_SEC_SGI_6 14 +#define MARVELL_IRQ_SEC_SGI_7 15 + +#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ + MARVELL_SHARED_RAM_BASE, \ + MARVELL_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ + MARVELL_DRAM_BASE, \ + MARVELL_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define MARVELL_BL_REGIONS 3 +#else +#define MARVELL_BL_REGIONS 2 +#endif + +#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ + MARVELL_BL_REGIONS) + +#define MARVELL_CONSOLE_BAUDRATE 115200 + +/**************************************************************************** + * Required platform porting definitions common to all MARVELL std. platforms + **************************************************************************** + */ +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF + + +#define PLATFORM_CORE_COUNT PLAT_MARVELL_CLUSTER_CORE_COUNT + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) + + +/***************************************************************************** + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ***************************************************************************** + */ +#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ + + PLAT_MARVELL_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVELL_MAX_BL1_RW_SIZE) +#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) + +/***************************************************************************** + * BL2 specific defines. + ***************************************************************************** + */ +/* + * Put BL2 just below BL31. + */ +#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) +#define BL2_LIMIT BL31_BASE + +/***************************************************************************** + * BL31 specific defines. + ***************************************************************************** + */ +/* + * Put BL31 at the top of the Trusted SRAM. + */ +#define BL31_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVEL_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE +#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE) + +/***************************************************************************** + * BL32 specific defines. + ***************************************************************************** + */ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ + +#endif /* MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a3k/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h new file mode 100644 index 0000000..cb31481 --- /dev/null +++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2016 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef PLAT_MARVELL_H +#define PLAT_MARVELL_H + +#include <stdint.h> + +#include <common/bl_common.h> +#include <lib/cassert.h> +#include <lib/el3_runtime/cpu_data.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +/* + * Extern declarations common to Marvell standard platforms + */ +extern const mmap_region_t plat_marvell_mmap[]; + +#define MARVELL_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions) + +/* + * Utility functions common to Marvell standard platforms + */ +void marvell_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, + uintptr_t coh_limit +#endif +); + +/* Console utility functions */ +void marvell_console_boot_init(void); +void marvell_console_boot_end(void); +void marvell_console_runtime_init(void); +void marvell_console_runtime_end(void); + +/* IO storage utility functions */ +void marvell_io_setup(void); + +/* Systimer utility function */ +void marvell_configure_sys_timer(void); + +/* Topology utility function */ +int marvell_check_mpidr(u_register_t mpidr); + +/* BL1 utility functions */ +void marvell_bl1_early_platform_setup(void); +void marvell_bl1_platform_setup(void); +void marvell_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void marvell_bl2_early_platform_setup(meminfo_t *mem_layout); +void marvell_bl2_platform_setup(void); +void marvell_bl2_plat_arch_setup(void); +uint32_t marvell_get_spsr_for_bl32_entry(void); +uint32_t marvell_get_spsr_for_bl33_entry(void); + +/* BL31 utility functions */ +void marvell_bl31_early_platform_setup(void *from_bl2, + uintptr_t soc_fw_config, + uintptr_t hw_config, + void *plat_params_from_bl2); +void marvell_bl31_platform_setup(void); +void marvell_bl31_plat_runtime_setup(void); +void marvell_bl31_plat_arch_setup(void); + +/* FIP TOC validity check */ +int marvell_io_is_toc_valid(void); + +/* + * PSCI functionality + */ +void marvell_psci_arch_init(int idx); +void plat_marvell_system_reset(void); + +/* + * Optional functions required in Marvell standard platforms + */ +void plat_marvell_io_setup(void); +int plat_marvell_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_marvell_calc_core_pos(u_register_t mpidr); + +void plat_marvell_interconnect_init(void); +void plat_marvell_interconnect_enter_coherency(void); + +const mmap_region_t *plat_marvell_get_mmap(void); + +uint32_t get_ref_clk(void); + +#endif /* PLAT_MARVELL_H */ diff --git a/include/plat/marvell/armada/a8k/common/armada_common.h b/include/plat/marvell/armada/a8k/common/armada_common.h new file mode 100644 index 0000000..709d009 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/armada_common.h @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef ARMADA_COMMON_H +#define ARMADA_COMMON_H + +#include <drivers/marvell/amb_adec.h> +#include <drivers/marvell/ccu.h> +#include <drivers/marvell/io_win.h> +#include <drivers/marvell/iob.h> + +/* + * This struct supports skip image request + * detection_method: the method used to detect the request "signal". + * info: + * GPIO: + * detection_method: HIGH (pressed button), LOW (unpressed button), + * num (button mpp number). + * i2c: + * i2c_addr: the address of the i2c chosen. + * i2d_reg: the i2c register chosen. + * test: + * choose the DIE you picked the button in (AP or CP). + * in case of CP(cp_index = 0 if CP0, cp_index = 1 if CP1) + */ +struct skip_image { + enum { + GPIO, + I2C, + USER_DEFINED + } detection_method; + + struct { + struct { + int num; + enum { + HIGH, + LOW + } button_state; + + } gpio; + + struct { + int i2c_addr; + int i2c_reg; + } i2c; + + struct { + enum { + CP, + AP + } cp_ap; + int cp_index; + } test; + } info; +}; + +/* + * This struct supports SoC power off method + * type: the method used to power off the SoC + * cfg: + * PMIC_GPIO: + * pin_count: current GPIO pin number used for toggling the signal for + * notifying external PMIC + * info: holds the GPIOs information, CP GPIO should be used and + * all GPIOs should be within same GPIO config. register + * step_count: current step number to toggle the GPIO for PMIC + * seq: GPIO toggling values in sequence, each bit represents a GPIO. + * For example, bit0 represents first GPIO used for toggling + * the GPIO the last step is used to trigger the power off + * signal + * delay_ms: transition interval for the GPIO setting to take effect + * in unit of ms + */ +/* Max GPIO number used to notify PMIC to power off the SoC */ +#define PMIC_GPIO_MAX_NUMBER 8 +/* Max GPIO toggling steps in sequence to power off the SoC */ +#define PMIC_GPIO_MAX_TOGGLE_STEP 8 + +enum gpio_output_state { + GPIO_LOW = 0, + GPIO_HIGH +}; + +typedef struct gpio_info { + int cp_index; + int gpio_index; +} gpio_info_t; + +struct power_off_method { + enum { + PMIC_GPIO, + } type; + + struct { + struct { + int pin_count; + struct gpio_info info[PMIC_GPIO_MAX_NUMBER]; + int step_count; + uint32_t seq[PMIC_GPIO_MAX_TOGGLE_STEP]; + int delay_ms; + } gpio; + } cfg; +}; + +int marvell_gpio_config(void); +uint32_t marvell_get_io_win_gcr_target(int ap_idx); +uint32_t marvell_get_ccu_gcr_target(int ap_idx); + + +/* + * The functions below are defined as Weak and may be overridden + * in specific Marvell standard platform + */ +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base); +int marvell_get_io_win_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); +int marvell_get_iob_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base); +int marvell_get_ccu_memory_map(int ap_idx, struct addr_map_win **win, + uint32_t *size); +int system_power_off(void); + +#endif /* ARMADA_COMMON_H */ diff --git a/include/plat/marvell/armada/a8k/common/board_marvell_def.h b/include/plat/marvell/armada/a8k/common/board_marvell_def.h new file mode 100644 index 0000000..7e90f5f --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/board_marvell_def.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef BOARD_MARVELL_DEF_H +#define BOARD_MARVELL_DEF_H + +/* + * Required platform porting definitions common to all ARM + * development platforms + */ + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +#else +# define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif IMAGE_BL31 +# define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* + * PLAT_MARVELL_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if IMAGE_BLE +# define PLAT_MARVELL_MMAP_ENTRIES 3 +#endif +#if IMAGE_BL1 +# if TRUSTED_BOARD_BOOT +# define PLAT_MARVELL_MMAP_ENTRIES 7 +# else +# define PLAT_MARVELL_MMAP_ENTRIES 6 +# endif /* TRUSTED_BOARD_BOOT */ +#endif +#if IMAGE_BL2 +# define PLAT_MARVELL_MMAP_ENTRIES 8 +#endif +#if IMAGE_BL31 +#define PLAT_MARVELL_MMAP_ENTRIES 5 +#endif + +/* + * Platform specific page table and MMU setup constants + */ +#if IMAGE_BL1 +#define MAX_XLAT_TABLES 4 +#elif IMAGE_BLE +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL2 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL32 +# define MAX_XLAT_TABLES 4 +#endif + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a8k/common/efuse_def.h b/include/plat/marvell/armada/a8k/common/efuse_def.h new file mode 100644 index 0000000..ff1d4a3 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/efuse_def.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2021 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef EFUSE_DEF_H +#define EFUSE_DEF_H + +#include <platform_def.h> + +#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8) +#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6 +#define EFUSE_SRV_CTRL_LD_SELECT_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS) + +#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) +/* Bits [31:0] - 32 data bits total */ +#define MVEBU_AP_LDX_31_0_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE) +/* Bits [62:32] - 31 data bits total 32nd bit is parity for bits [62:0]*/ +#define MVEBU_AP_LDX_62_32_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x4) +/* Bits [94:63] - 32 data bits total */ +#define MVEBU_AP_LDX_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8) +/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */ +#define MVEBU_AP_LDX_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC) +/* Bits [157:126] - 32 data bits total */ +#define MVEBU_AP_LDX_126_157_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x10) +/* Bits [188:158] - 31 data bits total, 32nd bit is parity for bits [188:126] */ +#define MVEBU_AP_LDX_188_158_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x14) +/* Bits [220:189] - 32 data bits total */ +#define MVEBU_AP_LDX_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18) + +#endif /* EFUSE_DEF_H */ diff --git a/include/plat/marvell/armada/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h new file mode 100644 index 0000000..1245b88 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/marvell_def.h @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MARVELL_DEF_H +#define MARVELL_DEF_H + +#include <platform_def.h> + +#include <arch.h> +#include <common/tbbr/tbbr_img_def.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/common_def.h> + +/****************************************************************************** + * Definitions common to all MARVELL standard platforms + *****************************************************************************/ + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + + +#define MARVELL_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 +#define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 +#define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in Marvell platforms encoded by + * State-ID field within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define MARVELL_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define MARVELL_LOCAL_STATE_RET 1 +/* + * Local power state for OFF/power-down. Valid for CPU + * and cluster power domains + */ +#define MARVELL_LOCAL_STATE_OFF 2 + +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE +#define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ + MARVELL_SHARED_RAM_SIZE) +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ + MARVELL_SHARED_RAM_SIZE) +/* Non-shared DRAM */ +#define MARVELL_DRAM_BASE ULL(0x0) +#define MARVELL_DRAM_SIZE ULL(0x80000000) +#define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ + MARVELL_DRAM_SIZE - 1) + +#define MARVELL_IRQ_PIC0 28 +#define MARVELL_IRQ_SEC_PHY_TIMER 29 + +#define MARVELL_IRQ_SEC_SGI_0 8 +#define MARVELL_IRQ_SEC_SGI_1 9 +#define MARVELL_IRQ_SEC_SGI_2 10 +#define MARVELL_IRQ_SEC_SGI_3 11 +#define MARVELL_IRQ_SEC_SGI_4 12 +#define MARVELL_IRQ_SEC_SGI_5 13 +#define MARVELL_IRQ_SEC_SGI_6 14 +#define MARVELL_IRQ_SEC_SGI_7 15 + +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \ + (PLAT_MARVELL_TRUSTED_RAM_BASE + \ + PLAT_MARVELL_TRUSTED_RAM_SIZE - \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE) +#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 +#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \ + MAP_REGION_FLAT( \ + MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging + * support is enabled). + */ +#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ + MARVELL_SHARED_RAM_BASE, \ + MARVELL_SHARED_RAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ + MARVELL_DRAM_BASE, \ + MARVELL_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define MARVELL_BL_REGIONS 3 +#else +#define MARVELL_BL_REGIONS 2 +#endif + +#define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ + MARVELL_BL_REGIONS) + +#define MARVELL_CONSOLE_BAUDRATE 115200 + +/****************************************************************************** + * Required platform porting definitions common to all MARVELL std. platforms + *****************************************************************************/ + +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF + + +#define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT +#define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) + + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ + + PLAT_MARVELL_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVELL_MAX_BL1_RW_SIZE) +#define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) + +/******************************************************************************* + * BLE specific defines. + ******************************************************************************/ +#define BLE_BASE PLAT_MARVELL_SRAM_BASE +#define BLE_LIMIT PLAT_MARVELL_SRAM_END + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +/* + * Put BL2 just below BL31. + */ +#define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) +#define BL2_LIMIT BL31_BASE + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM. + */ +#define BL31_BASE (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE - \ + PLAT_MARVEL_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE +#define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ + MARVELL_BL_RAM_SIZE) + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ + +#endif /* MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a8k/common/plat_marvell.h b/include/plat/marvell/armada/a8k/common/plat_marvell.h new file mode 100644 index 0000000..bec21a0 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/plat_marvell.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef PLAT_MARVELL_H +#define PLAT_MARVELL_H + +#include <stdint.h> + +#include <common/bl_common.h> +#include <lib/cassert.h> +#include <lib/el3_runtime/cpu_data.h> +#include <lib/utils.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +/* + * Extern declarations common to Marvell standard platforms + */ +extern const mmap_region_t plat_marvell_mmap[]; + +#define MARVELL_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_marvell_mmap) + MARVELL_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions) + +struct marvell_bl31_params { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +}; + +/* + * Utility functions common to Marvell standard platforms + */ +void marvell_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, + uintptr_t coh_limit +#endif +); + +/* Console utility functions */ +void marvell_console_boot_init(void); +void marvell_console_boot_end(void); +void marvell_console_runtime_init(void); +void marvell_console_runtime_end(void); + +/* IO storage utility functions */ +void marvell_io_setup(void); + +/* Systimer utility function */ +void marvell_configure_sys_timer(void); + +/* Topology utility function */ +int marvell_check_mpidr(u_register_t mpidr); + +/* BLE utility functions */ +int ble_plat_setup(int *skip); +void plat_marvell_dram_update_topology(void); +void ble_plat_pcie_ep_setup(void); +struct pci_hw_cfg *plat_get_pcie_hw_data(void); + +/* BL1 utility functions */ +void marvell_bl1_early_platform_setup(void); +void marvell_bl1_platform_setup(void); +void marvell_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void marvell_bl2_early_platform_setup(meminfo_t *mem_layout); +void marvell_bl2_platform_setup(void); +void marvell_bl2_plat_arch_setup(void); +uint32_t marvell_get_spsr_for_bl32_entry(void); +uint32_t marvell_get_spsr_for_bl33_entry(void); + +/* BL31 utility functions */ +void marvell_bl31_early_platform_setup(void *from_bl2, + uintptr_t soc_fw_config, + uintptr_t hw_config, + void *plat_params_from_bl2); +void marvell_bl31_platform_setup(void); +void marvell_bl31_plat_runtime_setup(void); +void marvell_bl31_plat_arch_setup(void); + +/* Power management config to power off the SoC */ +void *plat_marvell_get_pm_cfg(void); + +/* Check if MSS AP CM3 firmware contains PM support */ +_Bool is_pm_fw_running(void); + +/* Bootrom image recovery utility functions */ +void *plat_marvell_get_skip_image_data(void); + +/* FIP TOC validity check */ +int marvell_io_is_toc_valid(void); + +/* + * PSCI functionality + */ +void marvell_psci_arch_init(int ap_idx); +void plat_marvell_system_reset(void); + +/* + * Miscellaneous platform SMC routines + */ +#ifdef MVEBU_PMU_IRQ_WA +void mvebu_pmu_interrupt_enable(void); +void mvebu_pmu_interrupt_disable(void); +#endif + +/* + * Optional functions required in Marvell standard platforms + */ +void plat_marvell_io_setup(void); +int plat_marvell_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_marvell_calc_core_pos(u_register_t mpidr); + +const mmap_region_t *plat_marvell_get_mmap(void); +void marvell_ble_prepare_exit(void); +void marvell_exit_bootrom(uintptr_t base); + +int plat_marvell_early_cpu_powerdown(void); +int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info); + +#endif /* PLAT_MARVELL_H */ diff --git a/include/plat/marvell/armada/a8k/common/plat_pm_trace.h b/include/plat/marvell/armada/a8k/common/plat_pm_trace.h new file mode 100644 index 0000000..a954914 --- /dev/null +++ b/include/plat/marvell/armada/a8k/common/plat_pm_trace.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef PLAT_PM_TRACE_H +#define PLAT_PM_TRACE_H + +/* + * PM Trace is for Debug purpose only!!! + * It should not be enabled during System Run time + */ +#undef PM_TRACE_ENABLE + + +/* trace entry time */ +struct pm_trace_entry { + /* trace entry time stamp */ + unsigned int timestamp; + + /* trace info + * [16-31] - API Trace Id + * [00-15] - API Step Id + */ + unsigned int trace_info; +}; + +struct pm_trace_ctrl { + /* trace pointer - points to next free entry in trace cyclic queue */ + unsigned int trace_pointer; + + /* trace count - number of entries in the queue, clear upon read */ + unsigned int trace_count; +}; + +/* trace size definition */ +#define AP_MSS_ATF_CORE_INFO_SIZE (256) +#define AP_MSS_ATF_CORE_ENTRY_SIZE (8) +#define AP_MSS_ATF_TRACE_SIZE_MASK (0xFF) + +/* trace address definition */ +#define AP_MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110) + +#define AP_MSS_ATF_CORE_0_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520140) +#define AP_MSS_ATF_CORE_1_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520150) +#define AP_MSS_ATF_CORE_2_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520160) +#define AP_MSS_ATF_CORE_3_CTRL_BASE (MVEBU_REGS_BASE_MASK + 0x520170) +#define AP_MSS_ATF_CORE_CTRL_BASE (AP_MSS_ATF_CORE_0_CTRL_BASE) + +#define AP_MSS_ATF_CORE_0_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5201C0) +#define AP_MSS_ATF_CORE_0_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5201C4) +#define AP_MSS_ATF_CORE_1_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5209C0) +#define AP_MSS_ATF_CORE_1_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5209C4) +#define AP_MSS_ATF_CORE_2_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5211C0) +#define AP_MSS_ATF_CORE_2_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5211C4) +#define AP_MSS_ATF_CORE_3_INFO_BASE (MVEBU_REGS_BASE_MASK + 0x5219C0) +#define AP_MSS_ATF_CORE_3_INFO_TRACE (MVEBU_REGS_BASE_MASK + 0x5219C4) +#define AP_MSS_ATF_CORE_INFO_BASE (AP_MSS_ATF_CORE_0_INFO_BASE) + +/* trace info definition */ +#define TRACE_PWR_DOMAIN_OFF (0x10000) +#define TRACE_PWR_DOMAIN_SUSPEND (0x20000) +#define TRACE_PWR_DOMAIN_SUSPEND_FINISH (0x30000) +#define TRACE_PWR_DOMAIN_ON (0x40000) +#define TRACE_PWR_DOMAIN_ON_FINISH (0x50000) + +#define TRACE_PWR_DOMAIN_ON_MASK (0xFF) + +#ifdef PM_TRACE_ENABLE + +/* trace API definition */ +void pm_core_0_trace(unsigned int trace); +void pm_core_1_trace(unsigned int trace); +void pm_core_2_trace(unsigned int trace); +void pm_core_3_trace(unsigned int trace); + +typedef void (*core_trace_func)(unsigned int); + +extern core_trace_func funcTbl[PLATFORM_CORE_COUNT]; + +#define PM_TRACE(trace) funcTbl[plat_my_core_pos()](trace) + +#else + +#define PM_TRACE(trace) + +#endif + +/******************************************************************************* + * pm_trace_add + * + * DESCRIPTION: Add PM trace + ****************************************************************************** + */ +void pm_trace_add(unsigned int trace, unsigned int core); + +#endif /* PLAT_PM_TRACE_H */ diff --git a/include/plat/marvell/armada/common/aarch64/cci_macros.S b/include/plat/marvell/armada/common/aarch64/cci_macros.S new file mode 100644 index 0000000..b0a909b --- /dev/null +++ b/include/plat/marvell/armada/common/aarch64/cci_macros.S @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef CCI_MACROS_S +#define CCI_MACROS_S + +#include <drivers/arm/cci.h> +#include <platform_def.h> + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro print_cci_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + +#endif /* CCI_MACROS_S */ diff --git a/include/plat/marvell/armada/common/aarch64/marvell_macros.S b/include/plat/marvell/armada/common/aarch64/marvell_macros.S new file mode 100644 index 0000000..bfe2d41 --- /dev/null +++ b/include/plat/marvell/armada/common/aarch64/marvell_macros.S @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MARVELL_MACROS_S +#define MARVELL_MACROS_S + +#include <drivers/arm/cci.h> +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv2.h> +#include <drivers/arm/gicv3.h> +#include <platform_def.h> + +/* + * These Macros are required by ATF + */ + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +#ifdef USE_CCI +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" +#endif +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on ARM standard platforms. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro marvell_print_gic_regs + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + +#ifdef USE_CCI + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print +#endif + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro print_cci_regs +#ifdef USE_CCI + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print +#endif + .endm + + +#endif /* MARVELL_MACROS_S */ diff --git a/include/plat/marvell/armada/common/marvell_plat_priv.h b/include/plat/marvell/armada/common/marvell_plat_priv.h new file mode 100644 index 0000000..78b5331 --- /dev/null +++ b/include/plat/marvell/armada/common/marvell_plat_priv.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MARVELL_PLAT_PRIV_H +#define MARVELL_PLAT_PRIV_H + +#include <lib/utils.h> + +/***************************************************************************** + * Function and variable prototypes + ***************************************************************************** + */ +void plat_delay_timer_init(void); + +uint64_t mvebu_get_dram_size(uint64_t ap_base_addr); + +/* + * GIC operation, mandatory functions required in Marvell standard platforms + */ +void plat_marvell_gic_driver_init(void); +void plat_marvell_gic_init(void); +void plat_marvell_gic_cpuif_enable(void); +void plat_marvell_gic_cpuif_disable(void); +void plat_marvell_gic_pcpu_init(void); +void plat_marvell_gic_irq_save(void); +void plat_marvell_gic_irq_restore(void); +void plat_marvell_gic_irq_pcpu_save(void); +void plat_marvell_gic_irq_pcpu_restore(void); + +#endif /* MARVELL_PLAT_PRIV_H */ diff --git a/include/plat/marvell/armada/common/marvell_pm.h b/include/plat/marvell/armada/common/marvell_pm.h new file mode 100644 index 0000000..8f16607 --- /dev/null +++ b/include/plat/marvell/armada/common/marvell_pm.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MARVELL_PM_H +#define MARVELL_PM_H + +#define MVEBU_MAILBOX_MAGIC_NUM PLAT_MARVELL_MAILBOX_MAGIC_NUM +#define MVEBU_MAILBOX_SUSPEND_STATE 0xb007de7c + +/* Mailbox entry indexes */ +/* Magic number for validity check */ +#define MBOX_IDX_MAGIC 0 +/* Recovery from suspend entry point */ +#define MBOX_IDX_SEC_ADDR 1 +/* Suspend state magic number */ +#define MBOX_IDX_SUSPEND_MAGIC 2 +/* Recovery jump address for ROM bypass */ +#define MBOX_IDX_ROM_EXIT_ADDR 3 +/* BLE execution start counter value */ +#define MBOX_IDX_START_CNT 4 + +#endif /* MARVELL_PM_H */ diff --git a/include/plat/marvell/armada/common/mvebu.h b/include/plat/marvell/armada/common/mvebu.h new file mode 100644 index 0000000..35a0200 --- /dev/null +++ b/include/plat/marvell/armada/common/mvebu.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses + */ + +#ifndef MVEBU_H +#define MVEBU_H + +/* Use this functions only when printf is allowed */ +#define debug_enter() VERBOSE("----> Enter %s\n", __func__) +#define debug_exit() VERBOSE("<---- Exit %s\n", __func__) + +/* Macro for testing alignment. Positive if number is NOT aligned */ +#define IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) + +/* Macro for alignment up. For example, ALIGN_UP(0x0330, 0x20) = 0x0340 */ +#define ALIGN_UP(number, align) (((number) & ((align) - 1)) ? \ + (((number) + (align)) & ~((align)-1)) : (number)) + +/* Macro for testing whether a number is a power of 2. Positive if so */ +#define IS_POWER_OF_2(number) ((number) != 0 && \ + (((number) & ((number) - 1)) == 0)) + +/* + * Macro for ronding up to next power of 2 + * it is done by count leading 0 (clz assembly opcode) and see msb set bit. + * then you can shift it left and get number which power of 2 + * Note: this Macro is for 32 bit number + */ +#define ROUND_UP_TO_POW_OF_2(number) (1 << \ + (32 - __builtin_clz((number) - 1))) + +#define _1MB_ (1024ULL * 1024ULL) +#define _1GB_ (_1MB_ * 1024ULL) +#define _2GB_ (2 * _1GB_) + +#endif /* MVEBU_H */ diff --git a/include/plat/nuvoton/common/npcm845x_arm_def.h b/include/plat/nuvoton/common/npcm845x_arm_def.h new file mode 100644 index 0000000..5a44907 --- /dev/null +++ b/include/plat/nuvoton/common/npcm845x_arm_def.h @@ -0,0 +1,567 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (C) 2017-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NPCM845x_ARM_DEF_H +#define NPCM845x_ARM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +/* This flag will add zones to the MMU so that it will be possible to debug */ +#ifdef NPCM845X_DEBUG +#define ALLOW_DEBUG_MMU +#undef ALLOW_DEBUG_MMU +#endif /* NPCM845X_DEBUG */ + +#undef CONFIG_TARGET_ARBEL_PALLADIUM +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Root of trust key hash lengths + */ +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +/* No need for system because we have only one cluster */ +#define ARM_SYSTEM_COUNT U(0) + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +/* In NPCM845x - refers to cores */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 + +/* In NPCM845x - refers to cluster */ +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 + +/* No need for additional settings because the platform doesn't have system */ + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +#define NPCM845x_PLAT_PRIMARY_CPU U(0x0) +#define NPCM845x_CLUSTER_COUNT U(1) + +#ifdef SECONDARY_BRINGUP +#define NPCM845x_MAX_CPU_PER_CLUSTER U(2) +#define NPCM845x_PLATFORM_CORE_COUNT U(2) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2) +#else +#define NPCM845x_MAX_CPU_PER_CLUSTER U(4) +#define NPCM845x_PLATFORM_CORE_COUNT U(4) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4) +#endif /* SECONDARY_BRINGUP */ + +#define NPCM845x_SYSTEM_COUNT U(0) + +/* Memory mapping for NPCM845x */ +#define NPCM845x_REG_BASE 0xf0000000 +#define NPCM845x_REG_SIZE 0x0ff16000 + +/* + * DRAM + * 0x3fffffff +-------------+ + * | BL33 | (non-secure) + * 0x06200000 +-------------+ + * | BL32 SHARED | (non-secure) + * 0x06000000 +-------------+ + * | BL32 | (secure) + * 0x02100000 +-------------+ + * | BL31 | (secure) + * 0x02000000 +-------------+ + * | | (non-secure) + * 0x00000000 +-------------+ + * + * Trusted ROM + * 0xfff50000 +-------------+ + * | BL1 (ro) | + * 0xfff40000 +-------------+ + */ + +#define ARM_DRAM1_BASE ULL(0x00000000) +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +/* + * Although npcm845x is 4G, + * consider only 2G Trusted Firmware memory allocation + */ +#define ARM_DRAM1_SIZE ULL(0x37000000) +#else +#define ARM_DRAM1_SIZE ULL(0x10000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U) +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ + +/* Check for redundancy */ +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_NS_IMAGE_BASE 0x0 +#endif /* NPCM845X_DEBUG */ + +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1U) + +/* + * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `arm_el3_tzc_dram` + * will be placed here. + * + * NPCM845x - Currently the platform doesn't have EL3 implementation + * on secured DRAM. + */ +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ +#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ + ARM_EL3_TZC_DRAM1_SIZE - 1U) + +#define ARM_AP_TZC_DRAM1_BASE 0x02100000 +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1U) + +/* Define the Access permissions for Secure peripherals to NS_DRAM */ +#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE + +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +#define BL32_BASE ARM_AP_TZC_DRAM1_BASE +#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) + +#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \ + ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE) +#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) +#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ + ARM_OPTEE_PAGEABLE_LOAD_BASE, \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager + * when paging support is enabled). + */ +#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1U) + +/* The platform doesn't use DRAM2 but it has to have a value for calculation */ +#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ +#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */ +#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U) + +#define FIRST_EXT_INTERRUPT_NUM U(32) +#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM) + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ + PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef ALLOW_DEBUG_MMU +/* In order to be able to debug, + * the platform needs to add BL33 and BL32 to MMU as well. + */ +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BL32_BASE +#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* BL32_BASE */ + +#ifdef NPCM845X_DEBUG +#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \ + 0xFFFB0000, 0x20000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif /* NPCM845X_DEBUG */ +#endif /* BL32_BASE */ + +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if ARM_BL31_IN_DRAM +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* ARM_BL31_IN_DRAM */ + +/* Currently the platform doesn't have EL3 implementation on secured DRAM. */ +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if defined(SPD_spmd) +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_spmd */ + +/* + * Mapping for the BL1 RW region. This mapping is needed by BL2 + * in order to share the Mbed TLS heap. Since the heap is allocated + * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access + * to the BL1 RW region in order to be able to access the heap. + */ +#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ + BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +/* + * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region + * for each section, otherwise one region containing both sections + * is defined. + */ +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) +#else +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS) +#endif /* SEPARATE_CODE_AND_RODATA */ + +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) +#endif /* USE_COHERENT_MEM */ + +#if USE_ROMLIB +#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ + ROMLIB_RO_BASE, \ + ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \ + MT_CODE | MT_SECURE) + +#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ + ROMLIB_RW_BASE, \ + ROMLIB_RW_END - ROMLIB_RW_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* USE_ROMLIB */ + +/* + * Map mem_protect flash region with read and write permissions + */ +#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \ + PLAT_ARM_MEM_PROT_ADDR, \ + V2M_FLASH_BLOCK_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +/* + * Map the region for device tree configuration with read and write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ + ARM_BL_RAM_BASE, \ + (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 10 + +#define MAX_MMAP_REGIONS ( \ + PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* + * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) + */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches (64 on Arbel). + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) + +/* + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT ( \ + (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) +#define ARM_BL2_MEM_DESC_LIMIT ( \ + ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U)) + +/* + * Define limit of firmware configuration memory: + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory + */ +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need + * two sets of addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \ + (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ + (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ + (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) + +#define ROMLIB_RO_BASE BL1_RO_LIMIT +#define ROMLIB_RO_LIMIT ( \ + PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) + +#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) +#define ROMLIB_RW_END ( \ + ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) + +/****************************************************************************** + * BL2 specific defines. + *****************************************************************************/ +#if BL2_AT_EL3 +/* Put BL2 towards the middle of the Trusted SRAM */ +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) +#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#else +/* + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE +#endif /* BL2_AT_EL3 */ + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION +/* + * Put BL31 at the bottom of TZC secured DRAM + */ +#define BL31_BASE ARM_AP_TZC_DRAM1_BASE +#define BL31_LIMIT ( \ + ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE) + +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ +#elif (RESET_TO_BL31) +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +#if !ENABLE_PIE +#error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif /* !ENABLE_PIE */ +/* + * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely + * used for building BL31 and not used for loading BL31. + */ +#define NEW_SRAM_ALLOCATION + +#ifdef NEW_SRAM_ALLOCATION + #define BL31_BASE 0x20001000 +#else + #define BL31_BASE 0x20001000 +#endif /* NEW_SRAM_ALLOCATION */ + +#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */ +#else +/* Put BL31 below BL2 in the Trusted SRAM.*/ +#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL2_BASE + +/* + * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. + * This is because in the BL2_AT_EL3 configuration, BL2 is always resident. + */ +#if BL2_AT_EL3 +#define BL31_LIMIT BL2_BASE +#else +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#endif /* BL2_AT_EL3 */ +#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */ + +/* + * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is + * no SPD and no SPM-MM, as they are the only ones that can be used as BL32. + */ +#if defined(SPD_none) && !SPM_MM +#undef BL32_BASE +#endif /* SPD_none && !SPM_MM */ + +/****************************************************************************** + * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. + *****************************************************************************/ +#define BL2U_BASE BL2_BASE +#define BL2U_LIMIT BL2_LIMIT + +#define NS_BL2U_BASE ARM_NS_DRAM1_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + +/* Priority levels for ARM platforms */ +#define PLAT_RAS_PRI 0x10 +#define PLAT_SDEI_CRITICAL_PRI 0x60 +#define PLAT_SDEI_NORMAL_PRI 0x70 + +/* ARM platforms use 3 upper bits of secure interrupt priority */ +#define ARM_PRI_BITS 3 + +/* SGI used for SDEI signalling */ +#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 + +#if SDEI_IN_FCONF +/* ARM SDEI dynamic private event max count */ +#define ARM_SDEI_DP_EVENT_MAX_CNT 3 + +/* ARM SDEI dynamic shared event max count */ +#define ARM_SDEI_DS_EVENT_MAX_CNT 3 +#else +/* ARM SDEI dynamic private event numbers */ +#define ARM_SDEI_DP_EVENT_0 1000 +#define ARM_SDEI_DP_EVENT_1 1001 +#define ARM_SDEI_DP_EVENT_2 1002 + +/* ARM SDEI dynamic shared event numbers */ +#define ARM_SDEI_DS_EVENT_0 2000 +#define ARM_SDEI_DS_EVENT_1 2001 +#define ARM_SDEI_DS_EVENT_2 2002 + +#define ARM_SDEI_PRIVATE_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) + +#define ARM_SDEI_SHARED_EVENTS \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) +#endif /* SDEI_IN_FCONF */ + +#endif /* ARM_DEF_H */ diff --git a/include/plat/nuvoton/common/plat_macros.S b/include/plat/nuvoton/common/plat_macros.S new file mode 100644 index 0000000..08f9feb --- /dev/null +++ b/include/plat/nuvoton/common/plat_macros.S @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <arm_macros.S> +#include <cci_macros.S> +#include <platform_def.h> + +/* + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + */ +.macro plat_print_gic_regs +mov_imm x17, BASE_GICC_BASE +mov_imm x16, BASE_GICD_BASE +arm_print_gic_regs +.endm + +/* + * the below macros print out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1 + */ +.macro plat_print_interconnect_regs + /* TODO */ +.endm + +/* + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + */ +.macro plat_crash_print_regs + /* TODO */ +.endm + +#endif /* PLAT_MACROS_S */ diff --git a/include/plat/nuvoton/common/plat_npcm845x.h b/include/plat/nuvoton/common/plat_npcm845x.h new file mode 100644 index 0000000..d90952a --- /dev/null +++ b/include/plat/nuvoton/common/plat_npcm845x.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_NPCM845X_H +#define PLAT_NPCM845X_H + +#include <drivers/arm/gicv2.h> +#include <lib/psci/psci.h> + +unsigned int plat_calc_core_pos(uint64_t mpidr); +void npcm845x_mailbox_init(uintptr_t base_addr); +void plat_gic_driver_init(void); +void plat_gic_init(void); +void plat_gic_cpuif_enable(void); +void plat_gic_cpuif_disable(void); +void plat_gic_pcpu_init(void); + +void __dead2 npcm845x_system_off(void); +void __dead2 npcm845x_system_reset(void); +void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state); +bool npcm845x_is_wakeup_src_irqsteer(void); +void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state); +void npcm845x_cpu_standby(plat_local_state_t cpu_state); +int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint); +int npcm845x_pwr_domain_on(u_register_t mpidr); +int npcm845x_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); + +#if !ARM_BL31_IN_DRAM +void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state); +#endif + +void __dead2 npcm845x_pwr_domain_pwr_down_wfi( + const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_off(const psci_power_state_t *target_state); +void __init npcm845x_bl31_plat_arch_setup(void); + +#endif /* PLAT_NPCM845X_H */ diff --git a/include/plat/nuvoton/npcm845x/platform_def.h b/include/plat/nuvoton/npcm845x/platform_def.h new file mode 100644 index 0000000..09da36b --- /dev/null +++ b/include/plat/nuvoton/npcm845x/platform_def.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <npcm845x_arm_def.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define VALUE_TO_STRING(x) #x +#define VALUE(x) VALUE_TO_STRING(x) +#define VAR_NAME_VALUE(var) #var "=" VALUE(var) + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0x400 + +#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT +#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT +#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER +#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU +#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF +#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL + +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +#ifdef BL32_BASE + +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#else +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ +#endif /* BL32_BASE */ + +#define PWR_DOMAIN_AT_MAX_LVL U(1) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 16 +#define PLAT_ARM_MMAP_ENTRIES 17 + +#ifdef NPCM845X_DEBUG +#define MAX_MMAP_REGIONS 8 +#define NPCM845X_TZ1_BASE 0xFFFB0000 +#endif /* NPCM845X_DEBUG */ + +#define FIQ_SMP_CALL_SGI 10 + +/* (0x00040000) 128 KB, the rest 128K if it is non secured */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000) + +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ + +/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */ +#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE) + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) + +/* + * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000 + * because only half is secured in this specific implementation + */ +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) + +#if RESET_TO_BL31 +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#else +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE + * is calculated using the current BL31 PROGBITS debug size plus the sizes + * of BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#endif /* RESET_TO_BL31 */ +/* + * Load address of BL33 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000)) + +#ifdef NPCM845X_DEBUG +#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */ +#endif /* NPCM845X_DEBUG */ + +#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */ +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +/* GIC parameters */ + +/* Base compatible GIC memory map */ +#define NT_GIC_BASE (0xDFFF8000) +#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) +#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000) +#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000) + +#define DEVICE1_BASE BASE_GICD_BASE +#define DEVICE1_SIZE 0x7000 + +#ifdef NPCM845X_DEBUG +/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */ +#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4) +#endif /* NPCM845X_DEBUG */ + +#define PLAT_REG_BASE NPCM845x_REG_BASE +#define PLAT_REG_SIZE NPCM845x_REG_SIZE + +/* MMU entry for internal (register) space access */ +#define MAP_DEVICE0 \ + MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS) + +#define MAP_DEVICE1 \ + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) + +/* Required for compilation: */ + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */ +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) +#endif /* USE_ROMLIB */ + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION) +#else +/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */ +#define PLAT_ARM_MAX_BL2_SIZE 0 +#endif /* TRUSTED_BOARD_BOOT */ + +#undef NPCM_PRINT_ONCE +#ifdef NPCM_PRINT_ONCE +#define PRINT_ONLY_ONCE +#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE)) +#pragma message(VAR_NAME_VALUE(BL32_BASE)) +#pragma message(VAR_NAME_VALUE(BL32_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE) +#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO)) +#endif /* NPCM_PRINT_ONCE */ + +#define MAX_IO_DEVICES 4 +#define MAX_IO_HANDLES 4 + +#define PLAT_ARM_FIP_BASE 0x0 +#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE + +#define PLAT_ARM_BOOT_UART_BASE 0xF0000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_RUN_UART_BASE 0xF0000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_CRASH_UART_BASE 0xF0000000 +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200 + +/* + * Mailbox to control the secondary cores.All secondary cores are held in a wait + * loop in cold boot. To release them perform the following steps (plus any + * additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE; + * + * sev(); + */ +#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE + +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE +#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_NPCM_TM_HOLD_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE) +#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_NPCM_TM_HOLD_SIZE \ + (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT) +#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \ + (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT) + +#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \ + PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE) + +#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1) +#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2) + +#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA) +#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC) + +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000 +#endif /* NPCM845X_DEBUG */ + +#endif /* PLATFORM_DEF_H */ |