Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

8 files changed, 945 insertions, 0 deletions

diff --git a/plat/mediatek/mt8188/include/plat_helpers.h b/plat/mediatek/mt8188/include/plat_helpers.h
new file mode 100644
index 0000000..eb78623
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_HELPERS_H
+#define PLAT_HELPERS_H
+
+unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+
+#endif /* PLAT_HELPERS_H */
diff --git a/plat/mediatek/mt8188/include/plat_macros.S b/plat/mediatek/mt8188/include/plat_macros.S
new file mode 100644
index 0000000..a6e05a9
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_macros.S
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n"	\
+		" Offset:\t\t\tvalue\n"
+newline:
+	.asciz "\n"
+spacer:
+	.asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+	/* ---------------------------------------------
+	 * The below macro prints out relevant GIC
+	 * registers whenever an unhandled exception
+	 * is taken in BL31.
+	 * Clobbers: x0 - x10, x26, x27, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_crash_print_regs
+	/* TODO: leave implementation to GIC owner */
+	.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/mediatek/mt8188/include/plat_private.h b/plat/mediatek/mt8188/include/plat_private.h
new file mode 100644
index 0000000..4d4ac85
--- /dev/null
+++ b/plat/mediatek/mt8188/include/plat_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+			    uintptr_t total_size,
+			    uintptr_t ro_start,
+			    uintptr_t ro_limit);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
new file mode 100644
index 0000000..0a7ae6d
--- /dev/null
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch_def.h>
+
+#define PLAT_PRIMARY_CPU	(0x0)
+
+#define MT_GIC_BASE		(0x0C000000)
+#define MCUCFG_BASE		(0x0C530000)
+#define MCUCFG_REG_SIZE		(0x10000)
+#define IO_PHYS			(0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE	(MT_GIC_BASE)
+#define MTK_DEV_RNG0_SIZE	(0x600000)
+#define MTK_DEV_RNG1_BASE	(IO_PHYS)
+#define MTK_DEV_RNG1_SIZE	(0x10000000)
+
+#define TOPCKGEN_BASE		(IO_PHYS)
+
+/*******************************************************************************
+ * APUSYS related constants
+ ******************************************************************************/
+#define BCRM_FMEM_PDN_BASE	(IO_PHYS + 0x00276000)
+#define APU_MD32_SYSCTRL	(IO_PHYS + 0x09001000)
+#define APU_MD32_WDT		(IO_PHYS + 0x09002000)
+#define APU_RCX_CONFIG		(IO_PHYS + 0x09020000)
+#define APU_CTRL_DAPC_RCX_BASE	(IO_PHYS + 0x09034000)
+#define APU_NOC_DAPC_RCX_BASE	(IO_PHYS + 0x09038000)
+#define APU_REVISER		(IO_PHYS + 0x0903c000)
+#define APU_RCX_VCORE_CONFIG	(IO_PHYS + 0x090e0000)
+#define APU_MBOX0		(IO_PHYS + 0x090e1000)
+#define APU_MBOX1		(IO_PHYS + 0x090e2000)
+#define APU_RPCTOP		(IO_PHYS + 0x090f0000)
+#define APU_PCUTOP		(IO_PHYS + 0x090f1000)
+#define APU_AO_CTRL		(IO_PHYS + 0x090f2000)
+#define APU_PLL			(IO_PHYS + 0x090f3000)
+#define APU_ACC			(IO_PHYS + 0x090f4000)
+#define APU_SEC_CON		(IO_PHYS + 0x090f5000)
+#define APU_ARETOP_ARE0		(IO_PHYS + 0x090f6000)
+#define APU_ARETOP_ARE1		(IO_PHYS + 0x090f7000)
+#define APU_ARETOP_ARE2		(IO_PHYS + 0x090f8000)
+#define APU_CTRL_DAPC_AO_BASE	(IO_PHYS + 0x090fc000)
+#define APU_ACX0_RPC_LITE	(IO_PHYS + 0x09140000)
+#define BCRM_FMEM_PDN_SIZE	(0x1000)
+
+/*******************************************************************************
+ * AUDIO related constants
+ ******************************************************************************/
+#define AUDIO_BASE		(IO_PHYS + 0x00b10000)
+
+/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE		(IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define RGU_BASE		(IO_PHYS + 0x00007000)
+#define DRM_BASE		(IO_PHYS + 0x0000D000)
+#define IOCFG_RM_BASE		(IO_PHYS + 0x01C00000)
+#define IOCFG_LT_BASE		(IO_PHYS + 0x01E10000)
+#define IOCFG_LM_BASE		(IO_PHYS + 0x01E20000)
+#define IOCFG_RT_BASE		(IO_PHYS + 0x01EA0000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE	(IO_PHYS + 0x01002000)
+#define UART_BAUDRATE	(115200)
+
+/*******************************************************************************
+ * PMIC related constants
+ ******************************************************************************/
+#define PMIC_WRAP_BASE		(IO_PHYS + 0x00024000)
+
+/*******************************************************************************
+ * Infra IOMMU related constants
+ ******************************************************************************/
+#define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
+#define INFRACFG_AO_MEM_BASE	(IO_PHYS + 0x00002000)
+#define PERICFG_AO_BASE		(IO_PHYS + 0x01003000)
+#define PERICFG_AO_REG_SIZE	(0x1000)
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE		(MT_GIC_BASE)
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
+
+/*******************************************************************************
+ * CIRQ related constants
+ ******************************************************************************/
+#define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
+#define MD_WDT_IRQ_BIT_ID	(141)
+#define CIRQ_IRQ_NUM		(730)
+#define CIRQ_REG_NUM		(23)
+#define CIRQ_SPI_START		(96)
+
+/*******************************************************************************
+ * MM IOMMU & SMI related constants
+ ******************************************************************************/
+#define SMI_LARB_0_BASE		(IO_PHYS + 0x0c022000)
+#define SMI_LARB_1_BASE		(IO_PHYS + 0x0c023000)
+#define SMI_LARB_2_BASE		(IO_PHYS + 0x0c102000)
+#define SMI_LARB_3_BASE		(IO_PHYS + 0x0c103000)
+#define SMI_LARB_4_BASE		(IO_PHYS + 0x04013000)
+#define SMI_LARB_5_BASE		(IO_PHYS + 0x04f02000)
+#define SMI_LARB_6_BASE		(IO_PHYS + 0x04f03000)
+#define SMI_LARB_7_BASE		(IO_PHYS + 0x04e04000)
+#define SMI_LARB_9_BASE		(IO_PHYS + 0x05001000)
+#define SMI_LARB_10_BASE	(IO_PHYS + 0x05120000)
+#define SMI_LARB_11A_BASE	(IO_PHYS + 0x05230000)
+#define SMI_LARB_11B_BASE	(IO_PHYS + 0x05530000)
+#define SMI_LARB_11C_BASE	(IO_PHYS + 0x05630000)
+#define SMI_LARB_12_BASE	(IO_PHYS + 0x05340000)
+#define SMI_LARB_13_BASE	(IO_PHYS + 0x06001000)
+#define SMI_LARB_14_BASE	(IO_PHYS + 0x06002000)
+#define SMI_LARB_15_BASE	(IO_PHYS + 0x05140000)
+#define SMI_LARB_16A_BASE	(IO_PHYS + 0x06008000)
+#define SMI_LARB_16B_BASE	(IO_PHYS + 0x0600a000)
+#define SMI_LARB_17A_BASE	(IO_PHYS + 0x06009000)
+#define SMI_LARB_17B_BASE	(IO_PHYS + 0x0600b000)
+#define SMI_LARB_19_BASE	(IO_PHYS + 0x0a010000)
+#define SMI_LARB_21_BASE	(IO_PHYS + 0x0802e000)
+#define SMI_LARB_23_BASE	(IO_PHYS + 0x0800d000)
+#define SMI_LARB_27_BASE	(IO_PHYS + 0x07201000)
+#define SMI_LARB_28_BASE	(IO_PHYS + 0x00000000)
+#define SMI_LARB_REG_RNG_SIZE	(0x1000)
+
+/*******************************************************************************
+ * SPM related constants
+ ******************************************************************************/
+#define SPM_BASE		(IO_PHYS + 0x00006000)
+
+/*******************************************************************************
+ * APMIXEDSYS related constants
+ ******************************************************************************/
+#define APMIXEDSYS		(IO_PHYS + 0x0000C000)
+
+/*******************************************************************************
+ * VPPSYS related constants
+ ******************************************************************************/
+#define VPPSYS0_BASE		(IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE		(IO_PHYS + 0x04f00000)
+
+/*******************************************************************************
+ * VDOSYS related constants
+ ******************************************************************************/
+#define VDOSYS0_BASE		(IO_PHYS + 0x0C01D000)
+#define VDOSYS1_BASE		(IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * SSPM_MBOX_3 related constants
+ ******************************************************************************/
+#define SSPM_MBOX_3_BASE	(IO_PHYS + 0x00480000)
+
+/*******************************************************************************
+ * DP related constants
+ ******************************************************************************/
+#define EDP_SEC_BASE		(IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE		(IO_PHYS + 0x0C604000)
+#define EDP_SEC_SIZE		(0x1000)
+#define DP_SEC_SIZE		(0x1000)
+
+/*******************************************************************************
+ * EMI MPU related constants
+ *******************************************************************************/
+#define EMI_MPU_BASE		(IO_PHYS + 0x00226000)
+#define SUB_EMI_MPU_BASE	(IO_PHYS + 0x00225000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_HZ	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ	(13)
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE		(0x800)
+#define FIRMWARE_WELCOME_STR		"Booting Trusted Firmware\n"
+#define SOC_CHIP_ID			U(0x8188)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00040000)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE			(TZRAM_BASE + 0x1000)
+#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
+
+/*******************************************************************************
+ * CPU_EB TCM handling related constants
+ ******************************************************************************/
+#define CPU_EB_TCM_BASE		(0x0C550000)
+#define CPU_EB_TCM_SIZE		(0x10000)
+#define CPU_EB_MBOX3_OFFSET	(0xFCE0)
+
+/*******************************************************************************
+ * CPU PM definitions
+ *******************************************************************************/
+#define PLAT_CPU_PM_B_BUCK_ISO_ID	(6)
+#define PLAT_CPU_PM_ILDO_ID		(6)
+#define CPU_IDLE_SRAM_BASE		(0x11B000)
+#define CPU_IDLE_SRAM_SIZE		(0x1000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8188/include/spm_reg.h b/plat/mediatek/mt8188/include/spm_reg.h
new file mode 100644
index 0000000..e20f1aa
--- /dev/null
+++ b/plat/mediatek/mt8188/include/spm_reg.h
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2022, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPM_REG_H
+#define SPM_REG_H
+
+#include <platform_def.h>
+
+/* Register_SPM_CFG */
+#define MD32PCM_CFG_BASE                (SPM_BASE + 0xA00)
+#define POWERON_CONFIG_EN               (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0               (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1               (SPM_BASE + 0x008)
+#define SPM_CLK_CON                     (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE                  (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON              (SPM_BASE + 0x014)
+#define PCM_CON0                        (SPM_BASE + 0x018)
+#define PCM_CON1                        (SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2               (SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3               (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI                (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN                   (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL                   (SPM_BASE + 0x030)
+#define PCM_WDT_VAL                     (SPM_BASE + 0x034)
+#define SPM_SW_RST_CON                  (SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET              (SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR              (SPM_BASE + 0x048)
+#define SPM_ARBITER_EN                  (SPM_BASE + 0x050)
+#define SCPSYS_CLK_CON                  (SPM_BASE + 0x054)
+#define SPM_SRAM_RSV_CON                (SPM_BASE + 0x058)
+#define SPM_SWINT                       (SPM_BASE + 0x05C)
+#define SPM_SWINT_SET                   (SPM_BASE + 0x060)
+#define SPM_SWINT_CLR                   (SPM_BASE + 0x064)
+#define SPM_SCP_MAILBOX                 (SPM_BASE + 0x068)
+#define SCP_SPM_MAILBOX                 (SPM_BASE + 0x06C)
+#define SPM_SCP_IRQ                     (SPM_BASE + 0x070)
+#define SPM_CPU_WAKEUP_EVENT            (SPM_BASE + 0x074)
+#define SPM_IRQ_MASK                    (SPM_BASE + 0x078)
+#define SPM_SRC_REQ                     (SPM_BASE + 0x080)
+#define SPM_SRC_MASK                    (SPM_BASE + 0x084)
+#define SPM_SRC2_MASK                   (SPM_BASE + 0x088)
+#define SPM_SRC3_MASK                   (SPM_BASE + 0x090)
+#define SPM_SRC4_MASK                   (SPM_BASE + 0x094)
+#define SPM_WAKEUP_EVENT_MASK2          (SPM_BASE + 0x098)
+#define SPM_WAKEUP_EVENT_MASK           (SPM_BASE + 0x09C)
+#define SPM_WAKEUP_EVENT_SENS           (SPM_BASE + 0x0A0)
+#define SPM_WAKEUP_EVENT_CLEAR          (SPM_BASE + 0x0A4)
+#define SPM_WAKEUP_EVENT_EXT_MASK       (SPM_BASE + 0x0A8)
+#define SCP_CLK_CON                     (SPM_BASE + 0x0AC)
+#define PCM_DEBUG_CON                   (SPM_BASE + 0x0B0)
+#define DDREN_DBC_CON                   (SPM_BASE + 0x0B4)
+#define SPM_RESOURCE_ACK_CON0           (SPM_BASE + 0x0B8)
+#define SPM_RESOURCE_ACK_CON1           (SPM_BASE + 0x0BC)
+#define SPM_RESOURCE_ACK_CON2           (SPM_BASE + 0x0C0)
+#define SPM_RESOURCE_ACK_CON3           (SPM_BASE + 0x0C4)
+#define SPM_RESOURCE_ACK_CON4           (SPM_BASE + 0x0C8)
+#define SPM_SRAM_CON                    (SPM_BASE + 0x0CC)
+#define PCM_REG0_DATA                   (SPM_BASE + 0x100)
+#define PCM_REG2_DATA                   (SPM_BASE + 0x104)
+#define PCM_REG6_DATA                   (SPM_BASE + 0x108)
+#define PCM_REG7_DATA                   (SPM_BASE + 0x10C)
+#define PCM_REG13_DATA                  (SPM_BASE + 0x110)
+#define SRC_REQ_STA_0                   (SPM_BASE + 0x114)
+#define SRC_REQ_STA_1                   (SPM_BASE + 0x118)
+#define SRC_REQ_STA_2                   (SPM_BASE + 0x120)
+#define SRC_REQ_STA_3                   (SPM_BASE + 0x124)
+#define SRC_REQ_STA_4                   (SPM_BASE + 0x128)
+#define PCM_TIMER_OUT                   (SPM_BASE + 0x130)
+#define PCM_WDT_OUT                     (SPM_BASE + 0x134)
+#define SPM_IRQ_STA                     (SPM_BASE + 0x138)
+#define MD32PCM_WAKEUP_STA              (SPM_BASE + 0x13C)
+#define MD32PCM_EVENT_STA               (SPM_BASE + 0x140)
+#define SPM_WAKEUP_STA                  (SPM_BASE + 0x144)
+#define SPM_WAKEUP_EXT_STA              (SPM_BASE + 0x148)
+#define SPM_WAKEUP_MISC                 (SPM_BASE + 0x14C)
+#define MM_DVFS_HALT                    (SPM_BASE + 0x150)
+#define SUBSYS_IDLE_STA                 (SPM_BASE + 0x164)
+#define PCM_STA                         (SPM_BASE + 0x168)
+#define PWR_STATUS                      (SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND                  (SPM_BASE + 0x170)
+#define CPU_PWR_STATUS                  (SPM_BASE + 0x174)
+#define CPU_PWR_STATUS_2ND              (SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA       (SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA       (SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA       (SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA       (SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA       (SPM_BASE + 0x18C)
+#define MD32PCM_STA                     (SPM_BASE + 0x190)
+#define MD32PCM_PC                      (SPM_BASE + 0x194)
+#define OTHER_PWR_STATUS                (SPM_BASE + 0x198)
+#define DVFSRC_EVENT_STA                (SPM_BASE + 0x19C)
+#define BUS_PROTECT_RDY                 (SPM_BASE + 0x1A0)
+#define BUS_PROTECT1_RDY                (SPM_BASE + 0x1A4)
+#define BUS_PROTECT2_RDY                (SPM_BASE + 0x1A8)
+#define BUS_PROTECT3_RDY                (SPM_BASE + 0x1AC)
+#define BUS_PROTECT4_RDY                (SPM_BASE + 0x1B0)
+#define BUS_PROTECT5_RDY                (SPM_BASE + 0x1B4)
+#define BUS_PROTECT6_RDY                (SPM_BASE + 0x1B8)
+#define BUS_PROTECT7_RDY                (SPM_BASE + 0x1BC)
+#define BUS_PROTECT8_RDY                (SPM_BASE + 0x1C0)
+#define BUS_PROTECT9_RDY                (SPM_BASE + 0x1C4)
+#define SPM_TWAM_LAST_STA0              (SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1              (SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2              (SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3              (SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0              (SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1              (SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2              (SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3              (SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT              (SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA                (SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA                    (SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA                (SPM_BASE + 0x1FC)
+#define CPUEB_PWR_CON                   (SPM_BASE + 0x200)
+#define SPM_MCUSYS_PWR_CON              (SPM_BASE + 0x204)
+#define SPM_CPUTOP_PWR_CON              (SPM_BASE + 0x208)
+#define SPM_CPU0_PWR_CON                (SPM_BASE + 0x20C)
+#define SPM_CPU1_PWR_CON                (SPM_BASE + 0x210)
+#define SPM_CPU2_PWR_CON                (SPM_BASE + 0x214)
+#define SPM_CPU3_PWR_CON                (SPM_BASE + 0x218)
+#define SPM_CPU4_PWR_CON                (SPM_BASE + 0x21C)
+#define SPM_CPU5_PWR_CON                (SPM_BASE + 0x220)
+#define SPM_CPU6_PWR_CON                (SPM_BASE + 0x224)
+#define SPM_CPU7_PWR_CON                (SPM_BASE + 0x228)
+#define ARMPLL_CLK_CON                  (SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA                 (SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA                  (SPM_BASE + 0x234)
+#define CPU_SPARE_CON                   (SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET               (SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR               (SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL                  (SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ              (SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET          (SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR          (SPM_BASE + 0x250)
+#define CPU_IRQ_MASK                    (SPM_BASE + 0x260)
+#define CPU_IRQ_MASK_SET                (SPM_BASE + 0x264)
+#define CPU_IRQ_MASK_CLR                (SPM_BASE + 0x268)
+#define CPU_WFI_EN                      (SPM_BASE + 0x280)
+#define CPU_WFI_EN_SET                  (SPM_BASE + 0x284)
+#define CPU_WFI_EN_CLR                  (SPM_BASE + 0x288)
+#define SYSRAM_CON                      (SPM_BASE + 0x290)
+#define SYSROM_CON                      (SPM_BASE + 0x294)
+#define ROOT_CPUTOP_ADDR                (SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR                  (SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0                (SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1                (SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2                (SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3                (SPM_BASE + 0x2DC)
+#define SW2SPM_INT                      (SPM_BASE + 0x2E0)
+#define SW2SPM_INT_SET                  (SPM_BASE + 0x2E4)
+#define SW2SPM_INT_CLR                  (SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0                (SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1                (SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2                (SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3                (SPM_BASE + 0x2F8)
+#define SW2SPM_CFG                      (SPM_BASE + 0x2FC)
+#define MFG0_PWR_CON                    (SPM_BASE + 0x300)
+#define MFG1_PWR_CON                    (SPM_BASE + 0x304)
+#define MFG2_PWR_CON                    (SPM_BASE + 0x308)
+#define MFG3_PWR_CON                    (SPM_BASE + 0x30C)
+#define MFG4_PWR_CON                    (SPM_BASE + 0x310)
+#define MFG5_PWR_CON                    (SPM_BASE + 0x314)
+#define IFR_PWR_CON                     (SPM_BASE + 0x318)
+#define IFR_SUB_PWR_CON                 (SPM_BASE + 0x31C)
+#define PERI_PWR_CON                    (SPM_BASE + 0x320)
+#define PEXTP_MAC_TOP_P0_PWR_CON        (SPM_BASE + 0x324)
+#define PEXTP_PHY_TOP_PWR_CON           (SPM_BASE + 0x328)
+#define APHY_N_PWR_CON                  (SPM_BASE + 0x32C)
+#define APHY_S_PWR_CON                  (SPM_BASE + 0x330)
+#define ETHER_PWR_CON                   (SPM_BASE + 0x338)
+#define DPY0_PWR_CON                    (SPM_BASE + 0x33C)
+#define DPY1_PWR_CON                    (SPM_BASE + 0x340)
+#define DPM0_PWR_CON                    (SPM_BASE + 0x344)
+#define DPM1_PWR_CON                    (SPM_BASE + 0x348)
+#define AUDIO_PWR_CON                   (SPM_BASE + 0x34C)
+#define AUDIO_ASRC_PWR_CON              (SPM_BASE + 0x350)
+#define ADSP_PWR_CON                    (SPM_BASE + 0x354)
+#define ADSP_INFRA_PWR_CON              (SPM_BASE + 0x358)
+#define ADSP_AO_PWR_CON                 (SPM_BASE + 0x35C)
+#define VPPSYS0_PWR_CON                 (SPM_BASE + 0x360)
+#define VPPSYS1_PWR_CON                 (SPM_BASE + 0x364)
+#define VDOSYS0_PWR_CON                 (SPM_BASE + 0x368)
+#define VDOSYS1_PWR_CON                 (SPM_BASE + 0x36C)
+#define WPESYS_PWR_CON                  (SPM_BASE + 0x370)
+#define DP_TX_PWR_CON                   (SPM_BASE + 0x374)
+#define EDP_TX_PWR_CON                  (SPM_BASE + 0x378)
+#define HDMI_TX_PWR_CON                 (SPM_BASE + 0x37C)
+#define VDE0_PWR_CON                    (SPM_BASE + 0x380)
+#define VDE1_PWR_CON                    (SPM_BASE + 0x384)
+#define VDE2_PWR_CON                    (SPM_BASE + 0x388)
+#define VEN_PWR_CON                     (SPM_BASE + 0x38C)
+#define VEN_CORE1_PWR_CON               (SPM_BASE + 0x390)
+#define CAM_MAIN_PWR_CON                (SPM_BASE + 0x394)
+#define CAM_SUBA_PWR_CON                (SPM_BASE + 0x398)
+#define CAM_SUBB_PWR_CON                (SPM_BASE + 0x39C)
+#define CAM_VCORE_PWR_CON               (SPM_BASE + 0x3A0)
+#define IMG_VCORE_PWR_CON               (SPM_BASE + 0x3A4)
+#define IMG_MAIN_PWR_CON                (SPM_BASE + 0x3A8)
+#define IMG_DIP_PWR_CON                 (SPM_BASE + 0x3AC)
+#define IMG_IPE_PWR_CON                 (SPM_BASE + 0x3B0)
+#define NNA0_PWR_CON                    (SPM_BASE + 0x3B4)
+#define NNA1_PWR_CON                    (SPM_BASE + 0x3B8)
+#define IPNNA_PWR_CON                   (SPM_BASE + 0x3C0)
+#define CSI_RX_TOP_PWR_CON              (SPM_BASE + 0x3C4)
+#define SSPM_SRAM_CON                   (SPM_BASE + 0x3CC)
+#define SCP_SRAM_CON                    (SPM_BASE + 0x3D0)
+#define DEVAPC_IFR_SRAM_CON             (SPM_BASE + 0x3D8)
+#define DEVAPC_SUBIFR_SRAM_CON          (SPM_BASE + 0x3DC)
+#define DEVAPC_ACP_SRAM_CON             (SPM_BASE + 0x3E0)
+#define USB_SRAM_CON                    (SPM_BASE + 0x3E4)
+#define DUMMY_SRAM_CON                  (SPM_BASE + 0x3E8)
+#define EXT_BUCK_ISO                    (SPM_BASE + 0x3EC)
+#define MSDC_SRAM_CON                   (SPM_BASE + 0x3F0)
+#define DEBUGTOP_SRAM_CON               (SPM_BASE + 0x3F4)
+#define DPMAIF_SRAM_CON                 (SPM_BASE + 0x3F8)
+#define GCPU_SRAM_CON                   (SPM_BASE + 0x3FC)
+#define SPM_MEM_CK_SEL                  (SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B          (SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B         (SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B         (SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B         (SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B         (SPM_BASE + 0x414)
+#define SPM_BUS_PROTECT5_MASK_B         (SPM_BASE + 0x418)
+#define SPM_BUS_PROTECT6_MASK_B         (SPM_BASE + 0x41C)
+#define SPM_BUS_PROTECT7_MASK_B         (SPM_BASE + 0x420)
+#define SPM_BUS_PROTECT8_MASK_B         (SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT9_MASK_B         (SPM_BASE + 0x428)
+#define SPM_EMI_BW_MODE                 (SPM_BASE + 0x42C)
+#define SPM2MM_CON                      (SPM_BASE + 0x434)
+#define SPM2CPUEB_CON                   (SPM_BASE + 0x438)
+#define AP_MDSRC_REQ                    (SPM_BASE + 0x43C)
+#define SPM2EMI_ENTER_ULPM              (SPM_BASE + 0x440)
+#define SPM_PLL_CON                     (SPM_BASE + 0x444)
+#define RC_SPM_CTRL                     (SPM_BASE + 0x448)
+#define SPM_DRAM_MCU_SW_CON_0           (SPM_BASE + 0x44C)
+#define SPM_DRAM_MCU_SW_CON_1           (SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_2           (SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_3           (SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_4           (SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_STA_0              (SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_STA_1              (SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_2              (SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_SW_SEL_0           (SPM_BASE + 0x46C)
+#define RELAY_DVFS_LEVEL                (SPM_BASE + 0x470)
+#define DRAMC_DPY_CLK_SW_CON_0          (SPM_BASE + 0x474)
+#define DRAMC_DPY_CLK_SW_CON_1          (SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_2          (SPM_BASE + 0x47C)
+#define DRAMC_DPY_CLK_SW_CON_3          (SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_SEL_0          (SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_SEL_1          (SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_SEL_2          (SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_3          (SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SPM_CON           (SPM_BASE + 0x494)
+#define SPM_DVFS_LEVEL                  (SPM_BASE + 0x498)
+#define SPM_CIRQ_CON                    (SPM_BASE + 0x49C)
+#define SPM_DVFS_MISC                   (SPM_BASE + 0x4A0)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0    (SPM_BASE + 0x4A4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1    (SPM_BASE + 0x4A8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2    (SPM_BASE + 0x4AC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0    (SPM_BASE + 0x4B0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1    (SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2    (SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0    (SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1    (SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2    (SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0    (SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1    (SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2    (SPM_BASE + 0x4D0)
+#define PWR_STATUS_MASK_REQ_0           (SPM_BASE + 0x4D4)
+#define PWR_STATUS_MASK_REQ_1           (SPM_BASE + 0x4D8)
+#define PWR_STATUS_MASK_REQ_2           (SPM_BASE + 0x4DC)
+#define SPM_CG_CHECK_CON                (SPM_BASE + 0x4E0)
+#define SPM_SRC_RDY_STA                 (SPM_BASE + 0x4E4)
+#define SPM_DVS_DFS_LEVEL               (SPM_BASE + 0x4E8)
+#define SPM_FORCE_DVFS                  (SPM_BASE + 0x4EC)
+#define DRAMC_MCU_SRAM_CON              (SPM_BASE + 0x4F0)
+#define DRAMC_MCU2_SRAM_CON             (SPM_BASE + 0x4F4)
+#define DPY_SHU_SRAM_CON                (SPM_BASE + 0x4F8)
+#define DPY_SHU2_SRAM_CON               (SPM_BASE + 0x4FC)
+#define SPM_DPM_P2P_STA                 (SPM_BASE + 0x514)
+#define SPM_DPM_P2P_CON                 (SPM_BASE + 0x518)
+#define SPM_SW_FLAG_0                   (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0                  (SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1                   (SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1                  (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0                    (SPM_BASE + 0x610)
+#define SPM_SW_RSV_1                    (SPM_BASE + 0x614)
+#define SPM_SW_RSV_2                    (SPM_BASE + 0x618)
+#define SPM_SW_RSV_3                    (SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4                    (SPM_BASE + 0x620)
+#define SPM_SW_RSV_5                    (SPM_BASE + 0x624)
+#define SPM_SW_RSV_6                    (SPM_BASE + 0x628)
+#define SPM_SW_RSV_7                    (SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8                    (SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT               (SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR                (SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC                (SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER                (SPM_BASE + 0x640)
+#define ULPOSC_CON                      (SPM_BASE + 0x644)
+#define SPM_RSV_CON_0                   (SPM_BASE + 0x650)
+#define SPM_RSV_CON_1                   (SPM_BASE + 0x654)
+#define SPM_RSV_STA_0                   (SPM_BASE + 0x658)
+#define SPM_RSV_STA_1                   (SPM_BASE + 0x65C)
+#define SPM_SPARE_CON                   (SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET               (SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR               (SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ          (SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ          (SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ          (SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ          (SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL                 (SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON                (SPM_BASE + 0x680)
+#define SPARE_ACK_MASK                  (SPM_BASE + 0x684)
+#define SPM_DV_CON_0                    (SPM_BASE + 0x68C)
+#define SPM_DV_CON_1                    (SPM_BASE + 0x690)
+#define SPM_DV_STA                      (SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN             (SPM_BASE + 0x698)
+#define SPM_SEMA_M0                     (SPM_BASE + 0x69C)
+#define SPM_SEMA_M1                     (SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2                     (SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3                     (SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4                     (SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5                     (SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6                     (SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7                     (SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX                (SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX                (SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ                    (SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ                    (SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0              (SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1              (SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2              (SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3              (SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0              (SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1              (SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2              (SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3              (SPM_BASE + 0x6E8)
+#define SPM_AP_SEMA                     (SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA                    (SPM_BASE + 0x6FC)
+#define SPM_DVFS_CON                    (SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA                (SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON               (SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0                   (SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1                   (SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2                   (SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3                   (SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4                   (SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5                   (SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6                   (SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7                   (SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8                   (SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9                   (SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10                  (SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11                  (SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12                  (SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13                  (SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14                  (SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15                  (SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16                  (SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17                  (SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18                  (SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19                  (SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20                  (SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21                  (SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22                  (SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23                  (SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L               (SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H               (SPM_BASE + 0x774)
+#define SYS_TIMER_START_L               (SPM_BASE + 0x778)
+#define SYS_TIMER_START_H               (SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00            (SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00            (SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01            (SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01            (SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02            (SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02            (SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03            (SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03            (SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04            (SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04            (SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05            (SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05            (SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06            (SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06            (SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07            (SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07            (SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08            (SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08            (SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09            (SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09            (SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10            (SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10            (SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11            (SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11            (SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12            (SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12            (SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13            (SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13            (SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14            (SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14            (SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15            (SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15            (SPM_BASE + 0x7FC)
+#define PCM_WDT_LATCH_0                 (SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1                 (SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2                 (SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3                 (SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4                 (SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5                 (SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6                 (SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7                 (SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8                 (SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9                 (SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10                (SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11                (SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12                (SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13                (SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14                (SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15                (SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16                (SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17                (SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18                (SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0           (SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1           (SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2           (SPM_BASE + 0x854)
+#define DRAMC_GATING_ERR_LATCH_CH0_0    (SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1    (SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2    (SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3    (SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4    (SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5    (SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0  (SPM_BASE + 0x8F4)
+#define SPM_ACK_CHK_CON_0               (SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0                (SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0               (SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0             (SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0               (SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0             (SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1               (SPM_BASE + 0x920)
+#define SPM_ACK_CHK_PC_1                (SPM_BASE + 0x924)
+#define SPM_ACK_CHK_SEL_1               (SPM_BASE + 0x928)
+#define SPM_ACK_CHK_TIMER_1             (SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_STA_1               (SPM_BASE + 0x930)
+#define SPM_ACK_CHK_SWINT_1             (SPM_BASE + 0x934)
+#define SPM_ACK_CHK_CON_2               (SPM_BASE + 0x940)
+#define SPM_ACK_CHK_PC_2                (SPM_BASE + 0x944)
+#define SPM_ACK_CHK_SEL_2               (SPM_BASE + 0x948)
+#define SPM_ACK_CHK_TIMER_2             (SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_STA_2               (SPM_BASE + 0x950)
+#define SPM_ACK_CHK_SWINT_2             (SPM_BASE + 0x954)
+#define SPM_ACK_CHK_CON_3               (SPM_BASE + 0x960)
+#define SPM_ACK_CHK_PC_3                (SPM_BASE + 0x964)
+#define SPM_ACK_CHK_SEL_3               (SPM_BASE + 0x968)
+#define SPM_ACK_CHK_TIMER_3             (SPM_BASE + 0x96C)
+#define SPM_ACK_CHK_STA_3               (SPM_BASE + 0x970)
+#define SPM_ACK_CHK_SWINT_3             (SPM_BASE + 0x974)
+#define SPM_COUNTER_0                   (SPM_BASE + 0x978)
+#define SPM_COUNTER_1                   (SPM_BASE + 0x97C)
+#define SPM_COUNTER_2                   (SPM_BASE + 0x980)
+#define SYS_TIMER_CON                   (SPM_BASE + 0x98C)
+#define SPM_TWAM_CON                    (SPM_BASE + 0x990)
+#define SPM_TWAM_WINDOW_LEN             (SPM_BASE + 0x994)
+#define SPM_TWAM_IDLE_SEL               (SPM_BASE + 0x998)
+#define SPM_TWAM_EVENT_CLEAR            (SPM_BASE + 0x99C)
+#define PMSR_LAST_DAT                   (SPM_BASE + 0xF00)
+#define PMSR_LAST_CNT                   (SPM_BASE + 0xF04)
+#define PMSR_LAST_ACK                   (SPM_BASE + 0xF08)
+#define SPM_PMSR_SEL_CON0               (SPM_BASE + 0xF10)
+#define SPM_PMSR_SEL_CON1               (SPM_BASE + 0xF14)
+#define SPM_PMSR_SEL_CON2               (SPM_BASE + 0xF18)
+#define SPM_PMSR_SEL_CON3               (SPM_BASE + 0xF1C)
+#define SPM_PMSR_SEL_CON4               (SPM_BASE + 0xF20)
+#define SPM_PMSR_SEL_CON5               (SPM_BASE + 0xF24)
+#define SPM_PMSR_SEL_CON6               (SPM_BASE + 0xF28)
+#define SPM_PMSR_SEL_CON7               (SPM_BASE + 0xF2C)
+#define SPM_PMSR_SEL_CON8               (SPM_BASE + 0xF30)
+#define SPM_PMSR_SEL_CON9               (SPM_BASE + 0xF34)
+#define SPM_PMSR_SEL_CON10              (SPM_BASE + 0xF3C)
+#define SPM_PMSR_SEL_CON11              (SPM_BASE + 0xF40)
+#define SPM_PMSR_TIEMR_STA0             (SPM_BASE + 0xFB8)
+#define SPM_PMSR_TIEMR_STA1             (SPM_BASE + 0xFBC)
+#define SPM_PMSR_TIEMR_STA2             (SPM_BASE + 0xFC0)
+#define SPM_PMSR_GENERAL_CON0           (SPM_BASE + 0xFC4)
+#define SPM_PMSR_GENERAL_CON1           (SPM_BASE + 0xFC8)
+#define SPM_PMSR_GENERAL_CON2           (SPM_BASE + 0xFCC)
+#define SPM_PMSR_GENERAL_CON3           (SPM_BASE + 0xFD0)
+#define SPM_PMSR_GENERAL_CON4           (SPM_BASE + 0xFD4)
+#define SPM_PMSR_GENERAL_CON5           (SPM_BASE + 0xFD8)
+#define SPM_PMSR_SW_RESET               (SPM_BASE + 0xFDC)
+#define SPM_PMSR_MON_CON0               (SPM_BASE + 0xFE0)
+#define SPM_PMSR_MON_CON1               (SPM_BASE + 0xFE4)
+#define SPM_PMSR_MON_CON2               (SPM_BASE + 0xFE8)
+#define SPM_PMSR_LEN_CON0               (SPM_BASE + 0xFEC)
+#define SPM_PMSR_LEN_CON1               (SPM_BASE + 0xFF0)
+#define SPM_PMSR_LEN_CON2               (SPM_BASE + 0xFF4)
+
+#endif /* SPM_REG_H */
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
new file mode 100644
index 0000000..2e3392f
--- /dev/null
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -0,0 +1,50 @@
+#
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Separate text code and read only data
+SEPARATE_CODE_AND_RODATA := 1
+# ARMv8.2 and above need enable HW assist coherence
+HW_ASSISTED_COHERENCY := 1
+# No need coherency memory because of HW assistency
+USE_COHERENT_MEM := 0
+# GIC600
+GICV3_SUPPORT_GIC600 := 1
+#
+# MTK options
+#
+PLAT_EXTRA_RODATA_INCLUDES := 1
+USE_PMIC_WRAP_INIT_V2 := 1
+USE_RTC_MT6359P := 1
+
+# Configs for A78 and A55
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+ERRATA_A55_1221012 := 1
+ERRATA_A78_1688305 := 1
+ERRATA_A78_1941498 := 1
+ERRATA_A78_1951500 := 1
+ERRATA_A78_1821534 := 1
+ERRATA_A78_2132060 := 1
+ERRATA_A78_2242635 := 1
+ERRATA_A78_2376745 := 1
+ERRATA_A78_2395406 := 1
+
+CONFIG_ARCH_ARM_V8_2 := y
+CONFIG_MTK_MCUSYS := y
+MCUSYS_VERSION := v1
+CONFIG_MTK_PM_SUPPORT := y
+CONFIG_MTK_PM_ARCH := 8_2
+CONFIG_MTK_CPU_PM_SUPPORT := y
+CONFIG_MTK_CPU_PM_ARCH := 3_2
+CONFIG_MTK_SMP_EN := y
+CONFIG_MTK_CPU_SUSPEND_EN := y
+CONFIG_MTK_SPM_VERSION := mt8188
+CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND := y
+CPU_PM_TINYSYS_SUPPORT := y
+MTK_PUBEVENT_ENABLE := y
+
+MACH_MT8188 := 1
+$(eval $(call add_define,MACH_MT8188))
diff --git a/plat/mediatek/mt8188/plat_mmap.c b/plat/mediatek/mt8188/plat_mmap.c
new file mode 100644
index 0000000..a611d22
--- /dev/null
+++ b/plat/mediatek/mt8188/plat_mmap.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+static const mmap_region_t plat_mmap[] = {
+	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(CPU_IDLE_SRAM_BASE, CPU_IDLE_SRAM_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
+	{ 0 }
+};
+DECLARE_MTK_MMAP_REGIONS(plat_mmap);
diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk
new file mode 100644
index 0000000..5096e15
--- /dev/null
+++ b/plat/mediatek/mt8188/platform.mk
@@ -0,0 +1,68 @@
+#
+# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+MTK_SOC := ${PLAT}
+
+include plat/mediatek/build_helpers/mtk_build_helpers.mk
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common \
+		 -I${MTK_PLAT}/include \
+		 -I${MTK_PLAT}/include/${ARCH_VERSION} \
+		 -I${MTK_PLAT} \
+		 -I${MTK_PLAT_SOC}/include \
+		 -Idrivers/arm/gic \
+
+MODULES-y += $(MTK_PLAT)/common
+MODULES-y += $(MTK_PLAT)/common/lpm
+MODULES-y += $(MTK_PLAT)/lib/mtk_init
+MODULES-y += $(MTK_PLAT)/lib/pm
+MODULES-y += $(MTK_PLAT)/lib/system_reset
+MODULES-y += $(MTK_PLAT)/drivers/apusys
+MODULES-y += $(MTK_PLAT)/drivers/audio
+MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/cpu_pm
+MODULES-y += $(MTK_PLAT)/drivers/dcm
+MODULES-y += $(MTK_PLAT)/drivers/dfd
+MODULES-y += $(MTK_PLAT)/drivers/dp
+MODULES-y += $(MTK_PLAT)/drivers/emi_mpu
+MODULES-y += $(MTK_PLAT)/drivers/gic600
+MODULES-y += $(MTK_PLAT)/drivers/gpio
+MODULES-y += $(MTK_PLAT)/drivers/iommu
+MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
+MODULES-y += $(MTK_PLAT)/drivers/ptp3
+MODULES-y += $(MTK_PLAT)/drivers/rtc
+MODULES-y += $(MTK_PLAT)/drivers/spm
+MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/usb
+MODULES-y += $(MTK_PLAT)/helpers
+MODULES-y += $(MTK_PLAT)/topology
+
+PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
+			  drivers/ti/uart/aarch64/16550_console.S \
+			  lib/bl_aux_params/bl_aux_params.c
+
+BL31_SOURCES += drivers/delay_timer/delay_timer.c \
+		drivers/delay_timer/generic_delay_timer.c \
+		lib/cpus/aarch64/cortex_a55.S \
+		lib/cpus/aarch64/cortex_a78.S \
+		${GICV3_SOURCES} \
+		${XLAT_TABLES_LIB_SRCS} \
+		plat/common/plat_gicv3.c \
+		plat/common/plat_psci_common.c \
+		plat/common/aarch64/crash_console_helpers.S \
+		${MTK_PLAT}/common/mtk_plat_common.c \
+		${MTK_PLAT}/common/params_setup.c \
+		$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
+
+include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
+
+include lib/coreboot/coreboot.mk