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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-21 17:43:51 +0000 |
commit | be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b (patch) | |
tree | 779c248fb61c83f65d1f0dc867f2053d76b4e03a /plat/nvidia/tegra/include/tegra_platform.h | |
parent | Initial commit. (diff) | |
download | arm-trusted-firmware-be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b.tar.xz arm-trusted-firmware-be58c81aff4cd4c0ccf43dbd7998da4a6a08c03b.zip |
Adding upstream version 2.10.0+dfsg.upstream/2.10.0+dfsgupstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'plat/nvidia/tegra/include/tegra_platform.h')
-rw-r--r-- | plat/nvidia/tegra/include/tegra_platform.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h new file mode 100644 index 0000000..ab51dfe --- /dev/null +++ b/plat/nvidia/tegra/include/tegra_platform.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TEGRA_PLATFORM_H +#define TEGRA_PLATFORM_H + +#include <cdefs.h> +#include <lib/utils_def.h> +#include <stdbool.h> + +/******************************************************************************* + * Tegra major, minor version helper macros + ******************************************************************************/ +#define MAJOR_VERSION_SHIFT U(0x4) +#define MAJOR_VERSION_MASK U(0xF) +#define MINOR_VERSION_SHIFT U(0x10) +#define MINOR_VERSION_MASK U(0xF) +#define CHIP_ID_SHIFT U(8) +#define CHIP_ID_MASK U(0xFF) +#define PRE_SI_PLATFORM_SHIFT U(0x14) +#define PRE_SI_PLATFORM_MASK U(0xF) + +/******************************************************************************* + * Tegra chip ID values + ******************************************************************************/ +#define TEGRA_CHIPID_TEGRA13 U(0x13) +#define TEGRA_CHIPID_TEGRA21 U(0x21) +#define TEGRA_CHIPID_TEGRA18 U(0x18) +#define TEGRA_CHIPID_TEGRA19 U(0x19) + +/******************************************************************************* + * JEDEC Standard Manufacturer's Identification Code and Bank ID + ******************************************************************************/ +#define JEDEC_NVIDIA_MFID U(0x6B) +#define JEDEC_NVIDIA_BKID U(3) + +#ifndef __ASSEMBLER__ + +/* + * Tegra chip ID major/minor identifiers + */ +uint32_t tegra_get_chipid_major(void); +uint32_t tegra_get_chipid_minor(void); + +/* + * Tegra chip ID identifiers + */ +bool tegra_chipid_is_t186(void); +bool tegra_chipid_is_t210(void); +bool tegra_chipid_is_t210_b01(void); +bool tegra_chipid_is_t194(void); + +/* + * Tegra platform identifiers + */ +bool tegra_platform_is_silicon(void); +bool tegra_platform_is_qt(void); +bool tegra_platform_is_emulation(void); +bool tegra_platform_is_linsim(void); +bool tegra_platform_is_fpga(void); +bool tegra_platform_is_unit_fpga(void); +bool tegra_platform_is_virt_dev_kit(void); + +#endif /* __ASSEMBLER__ */ + +#endif /* TEGRA_PLATFORM_H */ |