diff options
Diffstat (limited to 'drivers/cadence')
| -rw-r--r-- | drivers/cadence/combo_phy/cdns_combo_phy.c | 83 | ||||
| -rw-r--r-- | drivers/cadence/emmc/cdns_sdmmc.c | 824 | ||||
| -rw-r--r-- | drivers/cadence/nand/cdns_nand.c | 435 | ||||
| -rw-r--r-- | drivers/cadence/uart/aarch64/cdns_console.S | 227 |
4 files changed, 1569 insertions, 0 deletions
diff --git a/drivers/cadence/combo_phy/cdns_combo_phy.c b/drivers/cadence/combo_phy/cdns_combo_phy.c new file mode 100644 index 0000000..f00d0c1 --- /dev/null +++ b/drivers/cadence/combo_phy/cdns_combo_phy.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_combo_phy.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value) +{ + uint32_t data = 0U; + uint32_t value = 0U; + + /* Get PHY register address, write HRS04*/ + value = mmio_read_32(phy_reg_addr); + value &= ~PHY_REG_ADDR_MASK; + value |= phy_reg_addr_value; + mmio_write_32(phy_reg_addr, value); + data = mmio_read_32(phy_reg_addr); + if ((data & PHY_REG_ADDR_MASK) != phy_reg_addr_value) { + ERROR("PHY_REG_ADDR is not set properly\n"); + return -ENXIO; + } + + /* Get PHY register data, write HRS05 */ + value &= ~PHY_REG_DATA_MASK; + value |= phy_reg_data_value; + mmio_write_32(phy_reg_data, value); + data = mmio_read_32(phy_reg_data); + if (data != phy_reg_data_value) { + ERROR("PHY_REG_DATA is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_sd_card_detect(void) +{ + uint32_t value = 0; + + /* Card detection */ + do { + value = mmio_read_32(SDMMC_CDN(SRS09)); + /* Wait for card insertion. SRS09.CI = 1 */ + } while ((value & (1 << SDMMC_CDN_CI)) == 0); + + if ((value & (1 << SDMMC_CDN_CI)) == 0) { + ERROR("Card does not detect\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_emmc_card_reset(void) +{ + uint32_t _status = 0; + + /* Reset embedded card */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + mdelay(68680); /* ~68680us */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(340); /* ~340us */ + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + + return 0; +} diff --git a/drivers/cadence/emmc/cdns_sdmmc.c b/drivers/cadence/emmc/cdns_sdmmc.c new file mode 100644 index 0000000..d2cd4d6 --- /dev/null +++ b/drivers/cadence/emmc/cdns_sdmmc.c @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <stddef.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <drivers/mmc.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +/* Card busy and present */ +#define CARD_BUSY 1 +#define CARD_NOT_BUSY 0 + +/* 500 ms delay to read the RINST register */ +#define DELAY_MS_SRS_READ 500 +#define DELAY_RES 10 + +/* SRS12 error mask */ +#define SRS12_ERR_MASK 0xFFFF8000 + +/* Check DV dfi_init val=0 */ +#define IO_MASK_END_DATA 0x0 + +/* Check DV dfi_init val=2; DDR Mode */ +#define IO_MASK_END_DATA_DDR 0x2 +#define IO_MASK_START_DATA 0x0 +#define DATA_SELECT_OE_END_DATA 0x1 + +#define TIMEOUT 100000 + +/* General define */ +#define SDHC_REG_MASK UINT_MAX +#define SD_HOST_BLOCK_SIZE 0x200 +#define DTCVVAL_DEFAULT_VAL 0xE +#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024 +#define CDNSMMC_ADDRESS_MASK U(0x0f) +#define CONFIG_CDNS_DESC_COUNT 8 + +void cdns_init(void); +int cdns_send_cmd(struct mmc_cmd *cmd); +int cdns_set_ios(unsigned int clk, unsigned int width); +int cdns_prepare(int lba, uintptr_t buf, size_t size); +int cdns_read(int lba, uintptr_t buf, size_t size); +int cdns_write(int lba, uintptr_t buf, size_t size); + +const struct mmc_ops cdns_sdmmc_ops = { + .init = cdns_init, + .send_cmd = cdns_send_cmd, + .set_ios = cdns_set_ios, + .prepare = cdns_prepare, + .read = cdns_read, + .write = cdns_write, +}; + +struct cdns_sdmmc_params cdns_params; +struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg; +struct cdns_sdmmc_sdhc sdmmc_sdhc_reg; +#ifdef CONFIG_DMA_ADDR_T_64BIT +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT]; +#else +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(32); +#endif + +bool data_cmd; + +int cdns_wait_ics(uint16_t timeout, uint32_t cdn_srs_res) +{ + /* Clock for sdmclk and sdclk */ + uint32_t count = 0; + uint32_t data = 0; + + /* Wait status command response ready */ + do { + data = mmio_read_32(cdn_srs_res); + count++; + if (count >= timeout) { + return -ETIMEDOUT; + } + } while ((data & (1 << SDMMC_CDN_ICS)) == 0); + + return 0; +} + +int cdns_busy(void) +{ + unsigned int data; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS09); + return (data & STATUS_DATA_BUSY) ? CARD_BUSY : CARD_NOT_BUSY; +} + +int cdns_vol_reset(void) +{ + /* Reset embedded card */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(500); + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + return 0; +} + +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + /* Values are taken by the reference of cadence IP documents */ + combo_phy_reg->cp_clk_wr_delay = 0; + combo_phy_reg->cp_clk_wrdqs_delay = 0; + combo_phy_reg->cp_data_select_oe_end = 0; + combo_phy_reg->cp_dll_bypass_mode = 1; + combo_phy_reg->cp_dll_locked_mode = 0; + combo_phy_reg->cp_dll_start_point = 0; + combo_phy_reg->cp_gate_cfg_always_on = 1; + combo_phy_reg->cp_io_mask_always_on = 0; + combo_phy_reg->cp_io_mask_end = 0; + combo_phy_reg->cp_io_mask_start = 0; + combo_phy_reg->cp_rd_del_sel = 52; + combo_phy_reg->cp_read_dqs_cmd_delay = 0; + combo_phy_reg->cp_read_dqs_delay = 0; + combo_phy_reg->cp_sw_half_cycle_shift = 0; + combo_phy_reg->cp_sync_method = 1; + combo_phy_reg->cp_underrun_suppress = 1; + combo_phy_reg->cp_use_ext_lpbk_dqs = 1; + combo_phy_reg->cp_use_lpbk_dqs = 1; + combo_phy_reg->cp_use_phony_dqs = 1; + combo_phy_reg->cp_use_phony_dqs_cmd = 1; + + sdhc_reg->sdhc_extended_rd_mode = 1; + sdhc_reg->sdhc_extended_wr_mode = 1; + sdhc_reg->sdhc_hcsdclkadj = 0; + sdhc_reg->sdhc_idelay_val = 0; + sdhc_reg->sdhc_rdcmd_en = 1; + sdhc_reg->sdhc_rddata_en = 1; + sdhc_reg->sdhc_rw_compensate = 9; + sdhc_reg->sdhc_sdcfsh = 0; + sdhc_reg->sdhc_sdcfsl = 1; + sdhc_reg->sdhc_wrcmd0_dly = 1; + sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0; + sdhc_reg->sdhc_wrcmd1_dly = 0; + sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata0_dly = 1; + sdhc_reg->sdhc_wrdata0_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata1_dly = 0; + sdhc_reg->sdhc_wrdata1_sdclk_dly = 0; +} + +static int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program PHY_DQS_TIMING_REG */ + value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) | + (CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) | + (CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) | + (CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQS_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_GATE_LPBK_CTRL_REG */ + value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) | + (CP_SW_HALF_CYCLE_SHIFT(combo_phy_reg->cp_sw_half_cycle_shift)) | + (CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) | + (CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) | + (CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_MASTER_CTRL_REG */ + value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) + | (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_SLAVE_CTRL_REG */ + value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) + | (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) + | (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) + | (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_CTRL_REG */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS04, COMBO_PHY_REG + + PHY_CTRL_REG); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS05); + + /* phony_dqs_timing=0 */ + value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS05, value); + + /* switch off DLL_RESET */ + do { + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value |= SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + /* polling PHY_INIT_COMPLETE */ + } while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE); + + /* program PHY_DQ_TIMING_REG */ + combo_phy_reg->cp_io_mask_end = 0U; + value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) + | (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) + | (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) + | (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end)); + + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQ_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + return 0; +} + +int cdns_read(int lba, uintptr_t buf, size_t size) +{ + inv_dcache_range(buf, size); + + return 0; +} + +void cdns_init(void) +{ + /* Dummy function pointer for cdns_init. */ +} + +int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size) +{ + data_cmd = true; + struct cdns_idmac_desc *desc; + uint32_t desc_cnt, i; + uint64_t desc_base; + + assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) && + (cdns_params.desc_size > 0) && + ((MMC_REG_BASE & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_base & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_size & MMC_BLOCK_MASK) == 0)); + + flush_dcache_range(dma_buff, size); + + desc_cnt = (size + (CDMMC_DMA_MAX_BUFFER_SIZE) - 1) / (CDMMC_DMA_MAX_BUFFER_SIZE); + assert(desc_cnt * sizeof(struct cdns_idmac_desc) < cdns_params.desc_size); + + if (desc_cnt > CONFIG_CDNS_DESC_COUNT) { + ERROR("Requested data transfer length %ld is greater than configured length %d", + size, (CONFIG_CDNS_DESC_COUNT * CDMMC_DMA_MAX_BUFFER_SIZE)); + return -EINVAL; + } + + desc = (struct cdns_idmac_desc *)cdns_params.desc_base; + desc_base = (uint64_t)desc; + i = 0; + + while ((i + 1) < desc_cnt) { + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + desc->reserved = 0; + desc->len = MAX_64KB_PAGE; + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_hi = (dma_buff >> 32) & 0xffffffff; +#endif + size -= CDMMC_DMA_MAX_BUFFER_SIZE; + desc++; + i++; + } + + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA | + ADMA_DESC_ATTR_END; + desc->reserved = 0; + desc->len = size; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); + desc->addr_hi = (dma_buff >> 32) & UINT_MAX; +#else + desc->addr_lo = (dma_buff & UINT_MAX); +#endif + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS22, (uint32_t)desc_base); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS23, (uint32_t)(desc_base >> 32)); + flush_dcache_range(cdns_params.desc_base, + desc_cnt * CDMMC_DMA_MAX_BUFFER_SIZE); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS01, + ((512 << BLOCK_SIZE) | ((size/512) << BLK_COUNT_CT) | SDMA_BUF)); + return 0; +} + +static void cdns_host_set_clk(int clk) +{ + uint32_t ret = 0; + uint32_t sdclkfsval = 0; + uint32_t dtcvval = DTCVVAL_DEFAULT_VAL; + + sdclkfsval = (cdns_params.clk_rate / 2000) / clk; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + } + + /* Enable DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & + ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) + & SDHC_EXTENDED_WR_MODE_MASK) | (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); +} + +int cdns_set_ios(unsigned int clk, unsigned int width) +{ + + switch (width) { + case MMC_BUS_WIDTH_1: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), LEDC_OFF); + break; + case MMC_BUS_WIDTH_4: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), DTW_4BIT); + break; + case MMC_BUS_WIDTH_8: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), EDTW_8BIT); + break; + default: + assert(0); + break; + } + cdns_host_set_clk(clk); + + return 0; +} + +int cdns_sdmmc_write_sd_host_reg(uint32_t addr, uint32_t data) +{ + uint32_t value = 0; + + value = mmio_read_32(addr); + value &= ~SDHC_REG_MASK; + value |= data; + mmio_write_32(addr, value); + value = mmio_read_32(addr); + if (value != data) { + ERROR("SD host address is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_write(int lba, uintptr_t buf, size_t size) +{ + return 0; +} + +static int cdns_init_hrs_io(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program HRS09, register 42 */ + value = (SDHC_RDDATA_EN(sdhc_reg->sdhc_rddata_en)) + | (SDHC_RDCMD_EN(sdhc_reg->sdhc_rdcmd_en)) + | (SDHC_EXTENDED_WR_MODE(sdhc_reg->sdhc_extended_wr_mode)) + | (SDHC_EXTENDED_RD_MODE(sdhc_reg->sdhc_extended_rd_mode)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + if (ret != 0) { + ERROR("Program HRS09 failed"); + return ret; + } + + /* program HRS10, register 43 */ + value = (SDHC_HCSDCLKADJ(sdhc_reg->sdhc_hcsdclkadj)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS10, value); + if (ret != 0) { + ERROR("Program HRS10 failed"); + return ret; + } + + /* program HRS16, register 48 */ + value = (SDHC_WRDATA1_SDCLK_DLY(sdhc_reg->sdhc_wrdata1_sdclk_dly)) + | (SDHC_WRDATA0_SDCLK_DLY(sdhc_reg->sdhc_wrdata0_sdclk_dly)) + | (SDHC_WRCMD1_SDCLK_DLY(sdhc_reg->sdhc_wrcmd1_sdclk_dly)) + | (SDHC_WRCMD0_SDCLK_DLY(sdhc_reg->sdhc_wrcmd0_sdclk_dly)) + | (SDHC_WRDATA1_DLY(sdhc_reg->sdhc_wrdata1_dly)) + | (SDHC_WRDATA0_DLY(sdhc_reg->sdhc_wrdata0_dly)) + | (SDHC_WRCMD1_DLY(sdhc_reg->sdhc_wrcmd1_dly)) + | (SDHC_WRCMD0_DLY(sdhc_reg->sdhc_wrcmd0_dly)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS16, value); + if (ret != 0) { + ERROR("Program HRS16 failed"); + return ret; + } + + /* program HRS07, register 40 */ + value = (SDHC_RW_COMPENSATE(sdhc_reg->sdhc_rw_compensate)) + | (SDHC_IDELAY_VAL(sdhc_reg->sdhc_idelay_val)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS07, value); + if (ret != 0) { + ERROR("Program HRS07 failed"); + return ret; + } + + return ret; +} + +static int cdns_hc_set_clk(struct cdns_sdmmc_params *cdn_sdmmc_dev_mode_params) +{ + uint32_t ret = 0; + uint32_t dtcvval, sdclkfsval; + + dtcvval = DTC_VAL; + sdclkfsval = 0; + + if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_DS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR12) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR_BC)) { + sdclkfsval = 4; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_HS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR25) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_DDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR)) { + sdclkfsval = 2; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_DDR) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400es)) { + sdclkfsval = 1; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR104) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS200)) { + sdclkfsval = 0; + } + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + return ret; + } + + /* Enable DLL reset */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) & ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), + (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & SDHC_EXTENDED_WR_MODE_MASK) | + (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); + return 0; +} + +int cdns_reset(void) +{ + uint32_t data = 0; + uint32_t count = 0; + uint32_t value = 0; + + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + value &= ~(0xFFFF); + value |= 0x0; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, value); + udelay(500); + + /* Software reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS00, 1); + /* Wait status command response ready */ + do { + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS00); + count++; + if (count >= 5000) { + return -ETIMEDOUT; + } + /* Wait for HRS00.SWR */ + } while ((data & 1) == 1); + + /* Step 1, switch on DLL_RESET */ + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value &= ~SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + + return 0; +} + +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg) +{ + int ret = 0; + + ret = cdns_reset(); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_init_hrs_io(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program init for HRS reg is failed"); + return ret; + } + + ret = cdns_sd_card_detect(); + if (ret != 0) { + ERROR("SD card does not detect"); + return ret; + } + + ret = cdns_vol_reset(); + if (ret != 0) { + ERROR("eMMC card reset failed"); + return ret; + } + + ret = cdns_hc_set_clk(&cdns_params); + if (ret != 0) { + ERROR("hc set clk failed"); + return ret; + } + + return 0; +} + +void cdns_srs10_value_toggle(uint8_t write_val, uint8_t prev_val) +{ + uint32_t data_op = 0U; + + data_op = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, (data_op & (prev_val << 0))); + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, data_op | (write_val << 0)); +} + +void cdns_srs11_srs15_config(uint32_t srs11_val, uint32_t srs15_val) +{ + uint32_t data = 0U; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (data | srs11_val)); + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS15); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS15, (data | srs15_val)); +} + +int cdns_send_cmd(struct mmc_cmd *cmd) +{ + uint32_t op = 0, ret = 0; + uint8_t write_value = 0, prev_val = 0; + uint32_t value; + int32_t timeout; + uint32_t cmd_indx; + uint32_t status = 0, srs15_val = 0, srs11_val = 0; + uint32_t status_check = 0; + + assert(cmd); + cmd_indx = (cmd->cmd_idx) << COM_IDX; + + if (data_cmd) { + switch (cmd->cmd_idx) { + case SD_SWITCH: + op = DATA_PRESENT; + write_value = ADMA2_32 | DT_WIDTH; + prev_val = ADMA2_32 | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + srs15_val = BIT_AD_64 | HV4E | V18SE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_WRITE_SINGLE_BLOCK: + case SD_READ_SINGLE_BLOCK: + op = DATA_PRESENT; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_WRITE_MULTIPLE_BLOCK: + case SD_READ_MULTIPLE_BLOCK: + op = DATA_PRESENT | AUTO_CMD_EN | MULTI_BLK_READ; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_APP_SEND_SCR: + op = DATA_PRESENT; + write_value = ADMA2_32 | LEDC; + prev_val = LEDC; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = BIT_AD_64 | HV4E | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = DATA_PRESENT | CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } else { + switch (cmd->cmd_idx) { + case SD_GO_IDLE_STATE: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_ALL_SEND_CID: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E | V18SE; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_STOP_TRANSMISSION: + op = CMD_STOP_ABORT_CMD; + break; + + case SD_SEND_STATUS: + break; + + case 1: + cmd->cmd_arg = 0; + break; + + case SD_SELECT_CARD: + op = MULTI_BLK_READ; + break; + + case SD_APP_CMD: + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } + + switch (cmd->resp_type) { + case MMC_RESPONSE_NONE: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN; + break; + + case MMC_RESPONSE_R2: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_136 | CMD_CHECK_RESP_CRC; + break; + + case MMC_RESPONSE_R3: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_48; + break; + + case MMC_RESPONSE_R1: + if ((cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK) || (cmd->cmd_idx + == SD_WRITE_MULTIPLE_BLOCK)) { + op |= DMA_ENABLED | BLK_CNT_EN | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } else { + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } + break; + + default: + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | MULTI_BLK_READ | + RES_TYPE_SEL_48 | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + break; + } + + timeout = TIMEOUT; + do { + udelay(100); + ret = cdns_busy(); + if (--timeout <= 0) { + udelay(50); + panic(); + } + } while (ret); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS12, UINT_MAX); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS02, cmd->cmd_arg); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS14, 0x00000000); + if (cmd_indx == 1) + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, SDHC_CDNS_SRS03_VALUE); + else + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, op | cmd_indx); + + timeout = TIMEOUT; + do { + udelay(500); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS12); + } while (((value & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0)); + + timeout = TIMEOUT; + + if (data_cmd) { + data_cmd = false; + do { + udelay(250); + } while (((value & TRAN_COMP) == 0) && (timeout-- > 0)); + } + + status_check = value & SRS12_ERR_MASK; + if (status_check != 0U) { + ERROR("SD host controller send command failed, SRS12 = %x", status); + return -1; + } + + if ((op & RES_TYPE_SEL_48) || (op & RES_TYPE_SEL_136)) { + cmd->resp_data[0] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS04); + if (op & RES_TYPE_SEL_136) { + cmd->resp_data[1] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS05); + cmd->resp_data[2] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS06); + cmd->resp_data[3] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS07); + } + } + + return 0; +} diff --git a/drivers/cadence/nand/cdns_nand.c b/drivers/cadence/nand/cdns_nand.c new file mode 100644 index 0000000..5a66262 --- /dev/null +++ b/drivers/cadence/nand/cdns_nand.c @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_nand.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include <platform_def.h> + +/* NAND flash device information struct */ +static cnf_dev_info_t dev_info; + +/* Scratch buffers for read and write operations */ +static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + +/* Wait for controller to be in idle state */ +static inline void cdns_nand_wait_idle(void) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_CTRL_BUSY(reg) != 0U); +} + +/* Wait for given thread to be in ready state */ +static inline void cdns_nand_wait_thread_ready(uint8_t thread_id) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(TRD_STATUS)); + reg &= (1U << (uint32_t)thread_id); + } while (reg != 0U); +} + +/* Check if the last operation/command in selected thread is completed */ +static int cdns_nand_last_opr_status(uint8_t thread_id) +{ + uint8_t nthreads = 0U; + uint32_t reg = 0U; + + /* Get number of threads */ + reg = mmio_read_32(CNF_CTRLPARAM(FEATURE)); + nthreads = CNF_GET_NTHREADS(reg); + + if (thread_id > nthreads) { + ERROR("%s: Invalid thread ID\n", __func__); + return -EINVAL; + } + + /* Select thread */ + mmio_write_32(CNF_CMDREG(CMD_STAT_PTR), (uint32_t)thread_id); + + uint32_t err_mask = CNF_ECMD | CNF_EECC | CNF_EDEV | CNF_EDQS | CNF_EFAIL | + CNF_EBUS | CNF_EDI | CNF_EPAR | CNF_ECTX | CNF_EPRO; + + do { + udelay(CNF_DEF_DELAY_US * 2); + reg = mmio_read_32(CNF_CMDREG(CMD_STAT)); + } while ((reg & CNF_CMPLT) == 0U); + + /* last operation is completed, make sure no other error bits are set */ + if ((reg & err_mask) == 1U) { + ERROR("%s, CMD_STATUS:0x%x\n", __func__, reg); + return -EIO; + } + + return 0; +} + +/* Set feature command */ +int cdns_nand_set_feature(uint8_t feat_addr, uint8_t feat_val, uint8_t thread_id) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(thread_id); + + /* Set feature address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), (uint32_t)feat_addr); + /* Set feature volume */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (uint32_t)feat_val); + + /* Set feature command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_SET_FEATURE << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Reset command to the selected device */ +int cdns_nand_reset(uint8_t thread_id) +{ + /* Operation is executed in selected thread */ + cdns_nand_wait_thread_ready(thread_id); + + /* Select memory */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Issue reset command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_RESET_ASYNC << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Set operation work mode */ +static void cdns_nand_set_opr_mode(uint8_t opr_mode) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Reset DLL PHY */ + uint32_t reg = mmio_read_32(CNF_MINICTRL(DLL_PHY_CTRL)); + + reg &= ~(1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); + + if (opr_mode == CNF_OPR_WORK_MODE_SDR) { + /* Combo PHY Control Timing Block register settings */ + mmio_write_32(CP_CTB(CTRL_REG), CP_CTRL_REG_SDR); + mmio_write_32(CP_CTB(TSEL_REG), CP_TSEL_REG_SDR); + + /* Combo PHY DLL register settings */ + mmio_write_32(CP_DLL(DQ_TIMING_REG), CP_DQ_TIMING_REG_SDR); + mmio_write_32(CP_DLL(DQS_TIMING_REG), CP_DQS_TIMING_REG_SDR); + mmio_write_32(CP_DLL(GATE_LPBK_CTRL_REG), CP_GATE_LPBK_CTRL_REG_SDR); + mmio_write_32(CP_DLL(MASTER_CTRL_REG), CP_DLL_MASTER_CTRL_REG_SDR); + + /* Async mode timing settings */ + mmio_write_32(CNF_MINICTRL(ASYNC_TOGGLE_TIMINGS), + (2 << CNF_ASYNC_TIMINGS_TRH) | + (4 << CNF_ASYNC_TIMINGS_TRP) | + (2 << CNF_ASYNC_TIMINGS_TWH) | + (4 << CNF_ASYNC_TIMINGS_TWP)); + + /* Set extended read and write mode */ + reg |= (1 << CNF_DLL_PHY_EXT_RD_MODE); + reg |= (1 << CNF_DLL_PHY_EXT_WR_MODE); + + /* Set operation work mode in common settings */ + uint32_t data = mmio_read_32(CNF_MINICTRL(CMN_SETTINGS)); + + data |= (CNF_OPR_WORK_MODE_SDR << CNF_CMN_SETTINGS_OPR); + mmio_write_32(CNF_MINICTRL(CMN_SETTINGS), data); + + } else if (opr_mode == CNF_OPR_WORK_MODE_NVDDR) { + ; /* ToDo: add DDR mode settings also once available on SIMICS */ + } else { + ; + } + + reg |= (1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); +} + +/* Data transfer configuration */ +static void cdns_nand_transfer_config(void) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Configure data transfer parameters */ + mmio_write_32(CNF_CTRLCFG(TRANS_CFG0), 1); + + /* ECC is disabled */ + mmio_write_32(CNF_CTRLCFG(ECC_CFG0), 0); + + /* DMA burst select */ + mmio_write_32(CNF_CTRLCFG(DMA_SETTINGS), + (CNF_DMA_BURST_SIZE_MAX << CNF_DMA_SETTINGS_BURST) | + (1 << CNF_DMA_SETTINGS_OTE)); + + /* Enable pre-fetching for 1K */ + mmio_write_32(CNF_CTRLCFG(FIFO_TLEVEL), + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_POS) | + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_DMA_SIZE)); + + /* Select access type */ + mmio_write_32(CNF_CTRLCFG(MULTIPLANE_CFG), 0); + mmio_write_32(CNF_CTRLCFG(CACHE_CFG), 0); +} + +/* Update the nand flash device info */ +static int cdns_nand_update_dev_info(void) +{ + uint32_t reg = 0U; + + /* Read the device type and number of LUNs */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_PARAMS0)); + dev_info.type = CNF_GET_DEV_TYPE(reg); + if (dev_info.type == CNF_DT_UNKNOWN) { + ERROR("%s: device type unknown\n", __func__); + return -ENXIO; + } + dev_info.nluns = CNF_GET_NLUNS(reg); + + /* Pages per block */ + reg = mmio_read_32(CNF_CTRLCFG(DEV_LAYOUT)); + dev_info.npages_per_block = CNF_GET_NPAGES_PER_BLOCK(reg); + + /* Sector size and last sector size */ + reg = mmio_read_32(CNF_CTRLCFG(TRANS_CFG1)); + dev_info.sector_size = CNF_GET_SCTR_SIZE(reg); + dev_info.last_sector_size = CNF_GET_LAST_SCTR_SIZE(reg); + + /* Page size and spare size */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_AREA)); + dev_info.page_size = CNF_GET_PAGE_SIZE(reg); + dev_info.spare_size = CNF_GET_SPARE_SIZE(reg); + + /* Device blocks per LUN */ + dev_info.nblocks_per_lun = mmio_read_32(CNF_CTRLPARAM(DEV_BLOCKS_PLUN)); + + /* Calculate block size and total device size */ + dev_info.block_size = (dev_info.npages_per_block * dev_info.page_size); + dev_info.total_size = (dev_info.block_size * dev_info.nblocks_per_lun * + dev_info.nluns); + + VERBOSE("CNF params: page %d, spare %d, block %d, total %lld\n", + dev_info.page_size, dev_info.spare_size, + dev_info.block_size, dev_info.total_size); + + return 0; +} + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void) +{ + uint32_t reg = 0U; + int ret = 0; + + do { + /* Read controller status register for init complete */ + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_INIT_COMP(reg) == 0); + + ret = cdns_nand_update_dev_info(); + if (ret != 0) { + return ret; + } + + INFO("CNF: device discovery process completed and device type %d\n", + dev_info.type); + + /* Enable data integrity, enable CRC and parity */ + reg = mmio_read_32(CNF_DI(CONTROL)); + reg |= (1 << CNF_DI_PAR_EN); + reg |= (1 << CNF_DI_CRC_EN); + mmio_write_32(CNF_DI(CONTROL), reg); + + /* Status polling mode, device control and status register */ + cdns_nand_wait_idle(); + reg = mmio_read_32(CNF_CTRLCFG(DEV_STAT)); + reg = reg & ~1; + mmio_write_32(CNF_CTRLCFG(DEV_STAT), reg); + + /* Set operation work mode */ + cdns_nand_set_opr_mode(CNF_OPR_WORK_MODE_SDR); + + /* Set data transfer configuration parameters */ + cdns_nand_transfer_config(); + + return 0; +} + +/* erase: Block erase command */ +int cdns_nand_erase(uint32_t offset, uint32_t size) +{ + /* Determine the starting block offset i.e row address */ + uint32_t row_address = dev_info.npages_per_block * offset; + + /* Wait for thread to be in ready state */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /*Set row address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Operation bank number */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Block erase command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_ERASE << CNF_CMDREG0_CMD); + reg |= (((size-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for erase operation to complete */ + return cdns_nand_last_opr_status(CNF_DEF_TRD); +} + +/* io mtd functions */ +int cdns_nand_init_mtd(unsigned long long *size, unsigned int *erase_size) +{ + *size = dev_info.total_size; + *erase_size = dev_info.block_size; + + return 0; +} + +/* NAND Flash page read */ +static int cdns_nand_read_page(uint32_t block, uint32_t page, uintptr_t buffer) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /* Select device */ + mmio_write_32(CNF_CMDREG(CMD_REG4), + (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Set host memory address for DMA transfers */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (buffer & 0xFFFF)); + mmio_write_32(CNF_CMDREG(CMD_REG3), ((buffer >> 32) & 0xFFFF)); + + /* Set row address */ + uint32_t row_address = 0U; + + row_address |= ((page & 0x3F) | (block << 6)); + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Page read command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_DMA_MASTER_SEL << CNF_CMDREG0_DMA); + reg |= (CNF_CT_PAGE_READ << CNF_CMDREG0_CMD); + reg |= (((CNF_READ_SINGLE_PAGE-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for read operation to complete */ + if (cdns_nand_last_opr_status(CNF_DEF_TRD)) { + ERROR("%s: Page read failed\n", __func__); + return -EIO; + } + + return 0; +} + +int cdns_nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *out_length) +{ + uint32_t block = offset / dev_info.block_size; + uint32_t end_block = (offset + length - 1U) / dev_info.block_size; + uint32_t page_start = (offset % dev_info.block_size) / dev_info.page_size; + uint32_t start_offset = offset % dev_info.page_size; + uint32_t nb_pages = dev_info.block_size / dev_info.page_size; + uint32_t bytes_read = 0U; + uint32_t page = 0U; + int result = 0; + + VERBOSE("CNF: block %u-%u, page_start %u, len %zu, offset %u\n", + block, end_block, page_start, length, offset); + + if ((offset >= dev_info.total_size) || + (offset + length-1 >= dev_info.total_size) || + (length == 0U)) { + ERROR("CNF: Invalid read parameters\n"); + return -EINVAL; + } + + *out_length = 0UL; + + while (block <= end_block) { + for (page = page_start; page < nb_pages; page++) { + if ((start_offset != 0U) || (length < dev_info.page_size)) { + /* Partial page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = MIN((size_t)(dev_info.page_size - start_offset), + length); + + memcpy((uint8_t *)buffer, scratch_buff + start_offset, + bytes_read); + start_offset = 0U; + } else { + /* Full page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = dev_info.page_size; + memcpy((uint8_t *)buffer, scratch_buff, bytes_read); + } + + length -= bytes_read; + buffer += bytes_read; + *out_length += bytes_read; + + /* All the bytes have read */ + if (length == 0U) { + break; + } + + udelay(CNF_READ_INT_DELAY_US); + } /* for */ + + page_start = 0U; + block++; + } /* while */ + + return 0; +} diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S new file mode 100644 index 0000000..d2dd0a8 --- /dev/null +++ b/drivers/cadence/uart/aarch64/cdns_console.S @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <arch.h> +#include <asm_macros.S> +#include <assert_macros.S> +#include <console_macros.S> +#include <drivers/cadence/cdns_uart.h> + + /* + * "core" functions are low-level implementations that don't require + * writable memory and are thus safe to call in BL1 crash context. + */ + .globl console_cdns_core_init + .globl console_cdns_core_putc + .globl console_cdns_core_getc + .globl console_cdns_core_flush + + .globl console_cdns_putc + .globl console_cdns_getc + .globl console_cdns_flush + + /* ----------------------------------------------- + * int console_cdns_core_init(uintptr_t base_addr) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * We assume that the bootloader already set up + * the HW (baud, ...) and only enable the trans- + * mitter and receiver here. + * In: x0 - console base address + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_cdns_core_init + /* Check the input base address */ + cbz x0, core_init_fail + + /* RX/TX enabled & reset */ + mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST) + str w3, [x0, #R_UART_CR] + + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_cdns_core_init + + .globl console_cdns_register + + /* ----------------------------------------------- + * int console_cdns_register(uintptr_t baseaddr, + * uint32_t clock, uint32_t baud, + * console_t *console); + * Function to initialize and register a new CDNS + * console. Storage passed in for the console struct + * *must* be persistent (i.e. not from the stack). + * In: x0 - UART register base address + * w1 - UART clock in Hz + * w2 - Baud rate + * x3 - pointer to empty console_t struct + * Out: return 1 on success, 0 on error + * Clobber list : x0, x1, x2, x6, x7, x14 + * ----------------------------------------------- + */ +func console_cdns_register + mov x7, x30 + mov x6, x3 + cbz x6, register_fail + str x0, [x6, #CONSOLE_T_BASE] + + bl console_cdns_core_init + cbz x0, register_fail + + mov x0, x6 + mov x30, x7 + finish_console_register cdns putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 + +register_fail: + ret x7 +endfunc console_cdns_register + + /* -------------------------------------------------------- + * int console_cdns_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_cdns_core_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f +1: + /* Check if the transmit FIFO is empty */ + ldr w2, [x1, #R_UART_SR] + tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b + mov w2, #0xD + str w2, [x1, #R_UART_TX] +2: + /* Check if the transmit FIFO is empty */ + ldr w2, [x1, #R_UART_SR] + tbz w2, #UART_SR_INTR_TEMPTY_BIT, 2b + str w0, [x1, #R_UART_TX] + ret +endfunc console_cdns_core_putc + + /* -------------------------------------------------------- + * int console_cdns_putc(int c, console_t *cdns) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - pointer to console_t structure + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_cdns_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x1, [x1, #CONSOLE_T_BASE] + b console_cdns_core_putc +endfunc console_cdns_putc + + /* --------------------------------------------- + * int console_cdns_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - console base address + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_cdns_core_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + + /* Check if the receive FIFO is empty */ + ldr w1, [x0, #R_UART_SR] + tbnz w1, #UART_SR_INTR_REMPTY_BIT, no_char + ldr w1, [x0, #R_UART_RX] + mov w0, w1 + ret +no_char: + mov w0, #ERROR_NO_PENDING_CHAR + ret +endfunc console_cdns_core_getc + + /* --------------------------------------------- + * int console_cdns_getc(console_t *console) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - pointer to console_t structure + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_cdns_getc +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_BASE] + b console_cdns_core_getc +endfunc console_cdns_getc + + /* --------------------------------------------- + * void console_cdns_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : void + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_cdns_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + /* Loop until the transmit FIFO is empty */ +check_txfifo_empty: + ldr w2, [x0, #R_UART_SR] + tbz w2, #UART_SR_INTR_TEMPTY_BIT, check_txfifo_empty + /* Wait until the Transmit is Inactive */ +check_tx_inactive_state: + ldr w2, [x0, #R_UART_SR] + tbnz w2, #UART_SR_INTR_TACTIVE_BIT, check_tx_inactive_state + ret +endfunc console_cdns_core_flush + + /* --------------------------------------------- + * void console_cdns_flush(console_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : void. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_cdns_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_BASE] + b console_cdns_core_flush +endfunc console_cdns_flush |