5 files changed, 364 insertions, 0 deletions
diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h
new file mode 100644
index 0000000..1d58ef9
--- /dev/null
+++ b/include/bl31/bl31.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BL31_H
+#define BL31_H
+
+#include <stdint.h>
+
+/*******************************************************************************
+ * Function prototypes
+ ******************************************************************************/
+void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+		u_register_t arg3);
+void bl31_next_el_arch_setup(uint32_t security_state);
+void bl31_set_next_image_type(uint32_t security_state);
+uint32_t bl31_get_next_image_type(void);
+void bl31_prepare_next_image_entry(void);
+void bl31_register_bl32_init(int32_t (*func)(void));
+void bl31_register_rmm_init(int32_t (*func)(void));
+void bl31_warm_entrypoint(void);
+void bl31_main(void);
+void bl31_lib_init(void);
+
+#endif /* BL31_H */
diff --git a/include/bl31/ea_handle.h b/include/bl31/ea_handle.h
new file mode 100644
index 0000000..7cd7b6a
--- /dev/null
+++ b/include/bl31/ea_handle.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EA_HANDLE_H
+#define EA_HANDLE_H
+
+/* Constants indicating the reason for an External Abort */
+
+/* External Abort received at SError vector */
+#define ERROR_EA_ASYNC		0
+
+/* Synchronous External Abort received at Synchronous exception vector */
+#define ERROR_EA_SYNC		1
+
+/* External Abort synchronized by ESB instruction */
+#define ERROR_EA_ESB		2
+
+/* RAS event signalled as peripheral interrupt */
+#define ERROR_INTERRUPT		3
+
+#define ASYNC_EA_REPLAY_COUNTER	U(100)
+
+#endif /* EA_HANDLE_H */
diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h
new file mode 100644
index 0000000..63943a9
--- /dev/null
+++ b/include/bl31/ehf.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef EHF_H
+#define EHF_H
+
+#ifndef __ASSEMBLER__
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+/* Valid priorities set bit 0 of the priority handler. */
+#define EHF_PRI_VALID_	BIT(0)
+
+/* Marker for no handler registered for a valid priority */
+#define EHF_NO_HANDLER_	(0U | EHF_PRI_VALID_)
+
+/* Extract the specified number of top bits from 7 lower bits of priority */
+#define EHF_PRI_TO_IDX(pri, plat_bits) \
+	((((unsigned) (pri)) & 0x7fu) >> (7u - (plat_bits)))
+
+/* Install exception priority descriptor at a suitable index */
+#define EHF_PRI_DESC(plat_bits, priority) \
+	[EHF_PRI_TO_IDX(priority, plat_bits)] = { \
+		.ehf_handler = EHF_NO_HANDLER_, \
+	}
+
+/* Macro for platforms to register its exception priorities */
+#define EHF_REGISTER_PRIORITIES(priorities, num, bits) \
+	const ehf_priorities_t exception_data = { \
+		.num_priorities = (num), \
+		.ehf_priorities = (priorities), \
+		.pri_bits = (bits), \
+	}
+
+/*
+ * Priority stack, managed as a bitmap.
+ *
+ * Currently only supports 32 priority levels, allowing platforms to use up to 5
+ * top bits of priority. But the type can be changed to uint64_t should need
+ * arise to support 64 priority levels, allowing platforms to use up to 6 top
+ * bits of priority.
+ */
+typedef uint32_t ehf_pri_bits_t;
+
+/*
+ * Per-PE exception data. The data for each PE is kept as a per-CPU data field.
+ * See cpu_data.h.
+ */
+typedef struct {
+	ehf_pri_bits_t active_pri_bits;
+
+	/* Priority mask value before any priority levels were active */
+	uint8_t init_pri_mask;
+
+	/* Non-secure priority mask value stashed during Secure execution */
+	uint8_t ns_pri_mask;
+} __aligned(sizeof(uint64_t)) pe_exc_data_t;
+
+typedef int (*ehf_handler_t)(uint32_t intr_raw, uint32_t flags, void *handle,
+		void *cookie);
+
+typedef struct ehf_pri_desc {
+	/*
+	 * 4-byte-aligned exception handler. Bit 0 indicates the corresponding
+	 * priority level is valid. This is effectively of ehf_handler_t type,
+	 * but left as uintptr_t in order to make pointer arithmetic convenient.
+	 */
+	uintptr_t ehf_handler;
+} ehf_pri_desc_t;
+
+typedef struct ehf_priority_type {
+	ehf_pri_desc_t *ehf_priorities;
+	unsigned int num_priorities;
+	unsigned int pri_bits;
+} ehf_priorities_t;
+
+void ehf_init(void);
+void ehf_activate_priority(unsigned int priority);
+void ehf_deactivate_priority(unsigned int priority);
+void ehf_register_priority_handler(unsigned int pri, ehf_handler_t handler);
+void ehf_allow_ns_preemption(uint64_t preempt_ret_code);
+unsigned int ehf_is_ns_preemption_allowed(void);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* EHF_H */
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
new file mode 100644
index 0000000..21af112
--- /dev/null
+++ b/include/bl31/interrupt_mgmt.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef INTERRUPT_MGMT_H
+#define INTERRUPT_MGMT_H
+
+#include <arch.h>
+#include <lib/utils_def.h>
+
+/*******************************************************************************
+ * Constants for the types of interrupts recognised by the IM framework
+ ******************************************************************************/
+#define INTR_TYPE_S_EL1			U(0)
+#define INTR_TYPE_EL3			U(1)
+#define INTR_TYPE_NS			U(2)
+#define MAX_INTR_TYPES			U(3)
+#define INTR_TYPE_INVAL			MAX_INTR_TYPES
+
+/* Interrupt routing modes */
+#define INTR_ROUTING_MODE_PE		0
+#define INTR_ROUTING_MODE_ANY		1
+
+/*
+ * Constant passed to the interrupt handler in the 'id' field when the
+ * framework does not read the gic registers to determine the interrupt id.
+ */
+#define INTR_ID_UNAVAILABLE		U(0xFFFFFFFF)
+
+
+/*******************************************************************************
+ * Mask for _both_ the routing model bits in the 'flags' parameter and
+ * constants to define the valid routing models for each supported interrupt
+ * type
+ ******************************************************************************/
+#define INTR_RM_FLAGS_SHIFT		U(0x0)
+#define INTR_RM_FLAGS_MASK		U(0x3)
+/* Routed to EL3 from NS. Taken to S-EL1 from Secure */
+#define INTR_SEL1_VALID_RM0		U(0x2)
+/* Routed to EL3 from NS and Secure */
+#define INTR_SEL1_VALID_RM1		U(0x3)
+/* Routed to EL1/EL2 from NS and to S-EL1 from Secure */
+#define INTR_NS_VALID_RM0		U(0x0)
+/* Routed to EL1/EL2 from NS and to EL3 from Secure */
+#define INTR_NS_VALID_RM1		U(0x1)
+/* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */
+#define INTR_EL3_VALID_RM0		U(0x2)
+/* Routed to EL3 from NS and Secure */
+#define INTR_EL3_VALID_RM1		U(0x3)
+/* This is the default routing model */
+#define INTR_DEFAULT_RM			U(0x0)
+
+/*******************************************************************************
+ * Constants for the _individual_ routing model bits in the 'flags' field for
+ * each interrupt type and mask to validate the 'flags' parameter while
+ * registering an interrupt handler
+ ******************************************************************************/
+#define INTR_TYPE_FLAGS_MASK		U(0xFFFFFFFC)
+
+#define INTR_RM_FROM_SEC_SHIFT		SECURE		/* BIT[0] */
+#define INTR_RM_FROM_NS_SHIFT		NON_SECURE	/* BIT[1] */
+#define INTR_RM_FROM_FLAG_MASK		U(1)
+#define get_interrupt_rm_flag(flag, ss) \
+	((((flag) >> INTR_RM_FLAGS_SHIFT) >> (ss)) & INTR_RM_FROM_FLAG_MASK)
+#define set_interrupt_rm_flag(flag, ss)	((flag) |= U(1) << (ss))
+#define clr_interrupt_rm_flag(flag, ss)	((flag) &= ~(U(1) << (ss)))
+
+/*******************************************************************************
+ * Macros to set the 'flags' parameter passed to an interrupt type handler. Only
+ * the flag to indicate the security state when the exception was generated is
+ * supported.
+ ******************************************************************************/
+#define INTR_SRC_SS_FLAG_SHIFT		U(0)		/* BIT[0] */
+#define INTR_SRC_SS_FLAG_MASK		U(1)
+#define set_interrupt_src_ss(flag, val)	((flag) |= (val) << INTR_SRC_SS_FLAG_SHIFT)
+#define clr_interrupt_src_ss(flag)	((flag) &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT))
+#define get_interrupt_src_ss(flag)	(((flag) >> INTR_SRC_SS_FLAG_SHIFT) & \
+					 INTR_SRC_SS_FLAG_MASK)
+
+#ifndef __ASSEMBLER__
+
+#include <errno.h>
+#include <stdint.h>
+
+/*******************************************************************************
+ * Helpers to validate the routing model bits in the 'flags' for a type
+ * of interrupt. If the model does not match one of the valid masks
+ * -EINVAL is returned.
+ ******************************************************************************/
+static inline int32_t validate_sel1_interrupt_rm(uint32_t x)
+{
+	if ((x == INTR_SEL1_VALID_RM0) || (x == INTR_SEL1_VALID_RM1))
+		return 0;
+
+	return -EINVAL;
+}
+
+static inline int32_t validate_ns_interrupt_rm(uint32_t x)
+{
+	if ((x == INTR_NS_VALID_RM0) || (x == INTR_NS_VALID_RM1))
+		return 0;
+
+	return -EINVAL;
+}
+
+static inline int32_t validate_el3_interrupt_rm(uint32_t x)
+{
+#if EL3_EXCEPTION_HANDLING && !(defined(SPD_spmd) && (SPMD_SPM_AT_SEL2 == 1))
+	/*
+	 * With EL3 exception handling, EL3 interrupts are always routed to EL3
+	 * from both Secure and Non-secure, when the SPMC does not live in S-EL2.
+	 * Therefore INTR_EL3_VALID_RM1 is the only valid routing model.
+	 */
+	if (x == INTR_EL3_VALID_RM1)
+		return 0;
+#else
+	/*
+	 * When EL3_EXCEPTION_HANDLING is not defined both routing modes are
+	 * valid. This is the most common case. The exception to this rule is
+	 * when EL3_EXCEPTION_HANDLING is defined but also when the SPMC lives
+	 * at S-EL2. In this case, Group0 Interrupts are trapped to the SPMC
+	 * when running in S-EL0 and S-EL1. The SPMC may handle the interrupt
+	 * itself, delegate it to an SP or forward to EL3 for handling.
+	 */
+	if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1))
+		return 0;
+#endif
+
+	return -EINVAL;
+}
+
+/*******************************************************************************
+ * Prototype for defining a handler for an interrupt type
+ ******************************************************************************/
+typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
+					     uint32_t flags,
+					     void *handle,
+					     void *cookie);
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+u_register_t get_scr_el3_from_routing_model(uint32_t security_state);
+int32_t set_routing_model(uint32_t type, uint32_t flags);
+int32_t register_interrupt_type_handler(uint32_t type,
+					interrupt_type_handler_t handler,
+					uint32_t flags);
+interrupt_type_handler_t get_interrupt_type_handler(uint32_t type);
+int disable_intr_rm_local(uint32_t type, uint32_t security_state);
+int enable_intr_rm_local(uint32_t type, uint32_t security_state);
+
+#endif /*__ASSEMBLER__*/
+#endif /* INTERRUPT_MGMT_H */
diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
new file mode 100644
index 0000000..1ac4f98
--- /dev/null
+++ b/include/bl31/sync_handle.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TRAP_HANDLE_H
+#define TRAP_HANDLE_H
+
+#include <stdbool.h>
+#include <context.h>
+
+#define ISS_SYSREG_OPCODE_MASK		0x3ffc1eUL
+#define ISS_SYSREG_REG_MASK		0x0003e0UL
+#define ISS_SYSREG_REG_SHIFT		5U
+#define ISS_SYSREG_DIRECTION_MASK	0x000001UL
+
+#define ISS_SYSREG_OPCODE_RNDR		0x30c808U
+#define ISS_SYSREG_OPCODE_IMPDEF	0x303c00U
+#define ISS_SYSREG_OPCODE_RNDRRS	0x32c808U
+
+#define TRAP_RET_UNHANDLED		-1
+#define TRAP_RET_REPEAT			0
+#define TRAP_RET_CONTINUE		1
+
+#ifndef __ASSEMBLER__
+static inline unsigned int get_sysreg_iss_rt(uint64_t esr)
+{
+	return (esr & ISS_SYSREG_REG_MASK) >> ISS_SYSREG_REG_SHIFT;
+}
+
+static inline bool is_sysreg_iss_write(uint64_t esr)
+{
+	return !(esr & ISS_SYSREG_DIRECTION_MASK);
+}
+
+/**
+ * handle_sysreg_trap() - Handle AArch64 system register traps from lower ELs
+ * @esr_el3: The content of ESR_EL3, containing the trap syndrome information
+ * @ctx: Pointer to the lower EL context, containing saved registers
+ *
+ * Called by the exception handler when a synchronous trap identifies as a
+ * system register trap (EC=0x18). ESR contains the encoding of the op[x] and
+ * CRm/CRn fields, to identify the system register, and the target/source
+ * GPR plus the direction (MRS/MSR). The lower EL's context can be altered
+ * by the function, to inject back the result of the emulation.
+ *
+ * Return: indication how to proceed with the trap:
+ *   TRAP_RET_UNHANDLED(-1): trap is unhandled, trigger panic
+ *   TRAP_RET_REPEAT(0): trap was handled, return to the trapping instruction
+ *			 (repeating it)
+ *   TRAP_RET_CONTINUE(1): trap was handled, return to the next instruction
+ *		           (continuing after it)
+ */
+int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
+
+/* Prototypes for system register emulation handlers provided by platforms. */
+int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx);
+int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);
+
+#endif /* __ASSEMBLER__ */
+
+#endif