diff options
Diffstat (limited to 'plat/intel/soc/agilex5/include')
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_clock_manager.h | 150 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_memory_controller.h | 175 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_mmc.h | 7 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_pinmux.h | 202 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_power_manager.h | 83 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/agilex5_system_manager.h | 200 | ||||
| -rw-r--r-- | plat/intel/soc/agilex5/include/socfpga_plat_def.h | 119 |
7 files changed, 936 insertions, 0 deletions
diff --git a/plat/intel/soc/agilex5/include/agilex5_clock_manager.h b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h new file mode 100644 index 0000000..566a80d --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CLOCKMANAGER_H +#define CLOCKMANAGER_H + +#include "socfpga_handoff.h" + +/* Clock Manager Registers */ +#define CLKMGR_OFFSET 0x10d10000 + +#define CLKMGR_CTRL 0x0 +#define CLKMGR_STAT 0x4 +#define CLKMGR_TESTIOCTROL 0x8 +#define CLKMGR_INTRGEN 0xc +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Main PLL Group */ +#define CLKMGR_MAINPLL 0x10d10024 +#define CLKMGR_MAINPLL_EN 0x0 +#define CLKMGR_MAINPLL_ENS 0x4 +#define CLKMGR_MAINPLL_BYPASS 0xc +#define CLKMGR_MAINPLL_BYPASSS 0x10 +#define CLKMGR_MAINPLL_BYPASSR 0x14 +#define CLKMGR_MAINPLL_NOCCLK 0x1c +#define CLKMGR_MAINPLL_NOCDIV 0x20 +#define CLKMGR_MAINPLL_PLLGLOB 0x24 +#define CLKMGR_MAINPLL_FDBCK 0x28 +#define CLKMGR_MAINPLL_MEM 0x2c +#define CLKMGR_MAINPLL_MEMSTAT 0x30 +#define CLKMGR_MAINPLL_VCOCALIB 0x34 +#define CLKMGR_MAINPLL_PLLC0 0x38 +#define CLKMGR_MAINPLL_PLLC1 0x3c +#define CLKMGR_MAINPLL_PLLC2 0x40 +#define CLKMGR_MAINPLL_PLLC3 0x44 +#define CLKMGR_MAINPLL_PLLM 0x48 +#define CLKMGR_MAINPLL_FHOP 0x4c +#define CLKMGR_MAINPLL_SSC 0x50 +#define CLKMGR_MAINPLL_LOSTLOCK 0x54 + +/* Peripheral PLL Group */ +#define CLKMGR_PERPLL 0x10d1007c +#define CLKMGR_PERPLL_EN 0x0 +#define CLKMGR_PERPLL_ENS 0x4 +#define CLKMGR_PERPLL_BYPASS 0xc +#define CLKMGR_PERPLL_EMACCTL 0x18 +#define CLKMGR_PERPLL_GPIODIV 0x1c +#define CLKMGR_PERPLL_PLLGLOB 0x20 +#define CLKMGR_PERPLL_FDBCK 0x24 +#define CLKMGR_PERPLL_MEM 0x28 +#define CLKMGR_PERPLL_MEMSTAT 0x2c +#define CLKMGR_PERPLL_PLLC0 0x30 +#define CLKMGR_PERPLL_PLLC1 0x34 +#define CLKMGR_PERPLL_VCOCALIB 0x38 +#define CLKMGR_PERPLL_PLLC2 0x3c +#define CLKMGR_PERPLL_PLLC3 0x40 +#define CLKMGR_PERPLL_PLLM 0x44 +#define CLKMGR_PERPLL_LOSTLOCK 0x50 + +/* Altera Group */ +#define CLKMGR_ALTERA 0x10d100d0 +#define CLKMGR_ALTERA_JTAG 0x0 +#define CLKMGR_ALTERA_EMACACTR 0x4 +#define CLKMGR_ALTERA_EMACBCTR 0x8 +#define CLKMGR_ALTERA_EMACPTPCTR 0xc +#define CLKMGR_ALTERA_GPIODBCTR 0x10 +#define CLKMGR_ALTERA_S2FUSER0CTR 0x18 +#define CLKMGR_ALTERA_S2FUSER1CTR 0x1c +#define CLKMGR_ALTERA_PSIREFCTR 0x20 +#define CLKMGR_ALTERA_EXTCNTRST 0x24 +#define CLKMGR_ALTERA_USB31CTR 0x28 +#define CLKMGR_ALTERA_DSUCTR 0x2c +#define CLKMGR_ALTERA_CORE01CTR 0x30 +#define CLKMGR_ALTERA_CORE23CTR 0x34 +#define CLKMGR_ALTERA_CORE2CTR 0x38 +#define CLKMGR_ALTERA_CORE3CTR 0x3c + +/* Membus */ +#define CLKMGR_MEM_REQ BIT(24) +#define CLKMGR_MEM_WR BIT(25) +#define CLKMGR_MEM_ERR BIT(26) +#define CLKMGR_MEM_WDAT_OFFSET 16 +#define CLKMGR_MEM_ADDR 0x4027 +#define CLKMGR_MEM_WDAT 0x80 + +/* Clock Manager Macros */ +#define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 +#define CLKMGR_STAT_BUSY_E_BUSY 0x1 +#define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) +#define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) +#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) +#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 +#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 +#define CLKMGR_INTOSC_HZ 460000000 + +/* Main PLL Macros */ +#define CLKMGR_MAINPLL_EN_RESET 0x0000005e +#define CLKMGR_MAINPLL_ENS_RESET 0x0000005e + +/* Peripheral PLL Macros */ +#define CLKMGR_PERPLL_EN_RESET 0x040007FF +#define CLKMGR_PERPLL_ENS_RESET 0x040007FF + +#define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) +#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) + +/* Altera Macros */ +#define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff + +/* Shared Macros */ +#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) +#define CLKMGR_PSRC_MAIN 0 +#define CLKMGR_PSRC_PER 1 + +#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 +#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 +#define CLKMGR_PLLGLOB_PSRC_F2S 0x2 + +#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) +#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 +#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 + +#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) +#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) + +#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) +#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) + +#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 + +typedef struct { + uint32_t clk_freq_of_eosc1; + uint32_t clk_freq_of_f2h_free; + uint32_t clk_freq_of_cb_intosc_ls; +} CLOCK_SOURCE_CONFIG; + +void config_clkmgr_handoff(handoff *hoff_ptr); +uint32_t get_wdt_clk(void); +uint32_t get_uart_clk(void); +uint32_t get_mmc_clk(void); + +#endif diff --git a/plat/intel/soc/agilex5/include/agilex5_memory_controller.h b/plat/intel/soc/agilex5/include/agilex5_memory_controller.h new file mode 100644 index 0000000..1708488 --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_memory_controller.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AGX_MEMORYCONTROLLER_H +#define AGX_MEMORYCONTROLLER_H + +#include "socfpga_plat_def.h" + +#define AGX_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8 +#define AGX_MPFE_IOHMC_CTRLCFG0 0xf8010028 +#define AGX_MPFE_IOHMC_CTRLCFG1 0xf801002c +#define AGX_MPFE_IOHMC_CTRLCFG2 0xf8010030 +#define AGX_MPFE_IOHMC_CTRLCFG3 0xf8010034 +#define AGX_MPFE_IOHMC_DRAMADDRW 0xf80100a8 +#define AGX_MPFE_IOHMC_DRAMTIMING0 0xf8010050 +#define AGX_MPFE_IOHMC_CALTIMING0 0xf801007c +#define AGX_MPFE_IOHMC_CALTIMING1 0xf8010080 +#define AGX_MPFE_IOHMC_CALTIMING2 0xf8010084 +#define AGX_MPFE_IOHMC_CALTIMING3 0xf8010088 +#define AGX_MPFE_IOHMC_CALTIMING4 0xf801008c +#define AGX_MPFE_IOHMC_CALTIMING9 0xf80100a0 +#define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) +#define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) (((value) & 0x00000060) >> 5) + +#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 +#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 + + +#define AGX_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c + +#define AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110 + +#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) +#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) +#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) +#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) +#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) + +#define AGX_MPFE_DDR(x) (0xf8000000 + x) +#define AGX_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c +#define AGX_MPFE_DDR_MAIN_SCHED 0xf8000400 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f +#define AGX_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c +#define AGX_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1)) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3)) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5)) + +#define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) +#define AGX_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210 +#define AGX_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008 +#define HMC_ADP_DDRIOCTRL 0x8 +#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) +#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9) +#define ADP_DRAMADDRWIDTH 0xe0 + +#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) +#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) + +/* timing 2 */ +#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) +#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) +#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) +#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) + +/* timing 3 */ +#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12) +#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) + +/* timing 4 */ +#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6) + +#define DDRTIMING_BWRATIO_OFST 31 +#define DDRTIMING_WRTORD_OFST 26 +#define DDRTIMING_RDTOWR_OFST 21 +#define DDRTIMING_BURSTLEN_OFST 18 +#define DDRTIMING_WRTOMISS_OFST 12 +#define DDRTIMING_RDTOMISS_OFST 6 +#define DDRTIMING_ACTTOACT_OFST 0 + +#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x3) >> 0) + +#define DDRMODE_AUTOPRECHARGE_OFST 1 +#define DDRMODE_BWRATIOEXTENDED_OFST 0 + + +#define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0) +#define AGX_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0f) >> 0) + +#define AGX_CCU_CPU0_MPRT_DDR 0xf7004400 +#define AGX_CCU_CPU0_MPRT_MEM0 0xf70045c0 +#define AGX_CCU_CPU0_MPRT_MEM1A 0xf70045e0 +#define AGX_CCU_CPU0_MPRT_MEM1B 0xf7004600 +#define AGX_CCU_CPU0_MPRT_MEM1C 0xf7004620 +#define AGX_CCU_CPU0_MPRT_MEM1D 0xf7004640 +#define AGX_CCU_CPU0_MPRT_MEM1E 0xf7004660 +#define AGX_CCU_IOM_MPRT_MEM0 0xf7018560 +#define AGX_CCU_IOM_MPRT_MEM1A 0xf7018580 +#define AGX_CCU_IOM_MPRT_MEM1B 0xf70185a0 +#define AGX_CCU_IOM_MPRT_MEM1C 0xf70185c0 +#define AGX_CCU_IOM_MPRT_MEM1D 0xf70185e0 +#define AGX_CCU_IOM_MPRT_MEM1E 0xf7018600 + +#define AGX_NOC_FW_DDR_SCR 0xf8020200 +#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802021c +#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020218 +#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802029c +#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020298 + +#define AGX_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020200 +#define AGX_SOC_NOC_FW_DDR_SCR_ENABLESET 0xf8020204 +#define AGX_CCU_NOC_DI_SET_MSK 0x10 + +#define AGX_SYSMGR_CORE_HMC_CLK 0xffd120b4 +#define AGX_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001 + +#define AGX_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0xffff) >> 0) +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0 +#define AGX_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f +#define AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7 + +#define AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000 +#define AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100 +#define AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001 + +#define AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001 +#define AGX_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 +#define AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100 +#define AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x1) >> 0) + + +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00003) >> 0) +#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x03c00) >> 10) +#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0c000) >> 14) +#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0001f) >> 0) +#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x70000) >> 16) +#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x003e0) >> 5) + +#define AGX_SDRAM_0_LB_ADDR 0x0 +#define AGX_DDR_SIZE 0x40000000 + +/* Macros */ +#define SOCFPGA_MEMCTRL_ECCCTRL1 0x008 +#define SOCFPGA_MEMCTRL_ERRINTEN 0x010 +#define SOCFPGA_MEMCTRL_ERRINTENS 0x014 +#define SOCFPGA_MEMCTRL_ERRINTENR 0x018 +#define SOCFPGA_MEMCTRL_INTMODE 0x01C +#define SOCFPGA_MEMCTRL_INTSTAT 0x020 +#define SOCFPGA_MEMCTRL_DIAGINTTEST 0x024 +#define SOCFPGA_MEMCTRL_DERRADDRA 0x02C + +#define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ + + (SOCFPGA_MEMCTRL_##_reg)) + +#endif diff --git a/plat/intel/soc/agilex5/include/agilex5_mmc.h b/plat/intel/soc/agilex5/include/agilex5_mmc.h new file mode 100644 index 0000000..c8a5fba --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_mmc.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +void agx5_mmc_init(void); diff --git a/plat/intel/soc/agilex5/include/agilex5_pinmux.h b/plat/intel/soc/agilex5/include/agilex5_pinmux.h new file mode 100644 index 0000000..8a8e8c7 --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_pinmux.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AGX5_PINMUX_H +#define AGX5_PINMUX_H + +/* PINMUX REGISTER ADDRESS */ +#define AGX5_PINMUX_PIN0SEL 0x10d13000 +#define AGX5_PINMUX_IO0CTRL 0x10d13130 +#define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300 +#define AGX5_PINMUX_IO0_DELAY 0x10d13400 +#define AGX5_PERIPHERAL 0x10d14044 + +#include "socfpga_handoff.h" + +/* PINMUX DEFINE */ +#define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec +#define PINMUX_HANDOFF_CONFIG_VAL 0x7e000 + +/* Macros */ +#define SOCFPGA_PINMUX_SEL_NAND (0x03) +#define SOCFPGA_PINMUX_PIN0SEL (0x00) +#define SOCFPGA_PINMUX_PIN1SEL (0x04) +#define SOCFPGA_PINMUX_PIN2SEL (0x08) +#define SOCFPGA_PINMUX_PIN3SEL (0x0C) +#define SOCFPGA_PINMUX_PIN4SEL (0x10) +#define SOCFPGA_PINMUX_PIN5SEL (0x14) +#define SOCFPGA_PINMUX_PIN6SEL (0x18) +#define SOCFPGA_PINMUX_PIN7SEL (0x1C) +#define SOCFPGA_PINMUX_PIN8SEL (0x20) +#define SOCFPGA_PINMUX_PIN9SEL (0x24) +#define SOCFPGA_PINMUX_PIN10SEL (0x28) +#define SOCFPGA_PINMUX_PIN11SEL (0x2C) +#define SOCFPGA_PINMUX_PIN12SEL (0x30) +#define SOCFPGA_PINMUX_PIN13SEL (0x34) +#define SOCFPGA_PINMUX_PIN14SEL (0x38) +#define SOCFPGA_PINMUX_PIN15SEL (0x3C) +#define SOCFPGA_PINMUX_PIN16SEL (0x40) +#define SOCFPGA_PINMUX_PIN17SEL (0x44) +#define SOCFPGA_PINMUX_PIN18SEL (0x48) +#define SOCFPGA_PINMUX_PIN19SEL (0x4C) +#define SOCFPGA_PINMUX_PIN20SEL (0x50) +#define SOCFPGA_PINMUX_PIN21SEL (0x54) +#define SOCFPGA_PINMUX_PIN22SEL (0x58) +#define SOCFPGA_PINMUX_PIN23SEL (0x5C) +#define SOCFPGA_PINMUX_PIN24SEL (0x60) +#define SOCFPGA_PINMUX_PIN25SEL (0x64) +#define SOCFPGA_PINMUX_PIN26SEL (0x68) +#define SOCFPGA_PINMUX_PIN27SEL (0x6C) +#define SOCFPGA_PINMUX_PIN28SEL (0x70) +#define SOCFPGA_PINMUX_PIN29SEL (0x74) +#define SOCFPGA_PINMUX_PIN30SEL (0x78) +#define SOCFPGA_PINMUX_PIN31SEL (0x7C) +#define SOCFPGA_PINMUX_PIN32SEL (0x80) +#define SOCFPGA_PINMUX_PIN33SEL (0x84) +#define SOCFPGA_PINMUX_PIN34SEL (0x88) +#define SOCFPGA_PINMUX_PIN35SEL (0x8C) +#define SOCFPGA_PINMUX_PIN36SEL (0x90) +#define SOCFPGA_PINMUX_PIN37SEL (0x94) +#define SOCFPGA_PINMUX_PIN38SEL (0x98) +#define SOCFPGA_PINMUX_PIN39SEL (0x9C) +#define SOCFPGA_PINMUX_PIN40SEL (0x100) +#define SOCFPGA_PINMUX_PIN41SEL (0x104) +#define SOCFPGA_PINMUX_PIN42SEL (0x108) +#define SOCFPGA_PINMUX_PIN43SEL (0x10C) +#define SOCFPGA_PINMUX_PIN44SEL (0x110) +#define SOCFPGA_PINMUX_PIN45SEL (0x114) +#define SOCFPGA_PINMUX_PIN46SEL (0x118) +#define SOCFPGA_PINMUX_PIN47SEL (0x11C) + +#define SOCFPGA_PINMUX_IO0CTRL (0x00) +#define SOCFPGA_PINMUX_IO1CTRL (0x04) +#define SOCFPGA_PINMUX_IO2CTRL (0x08) +#define SOCFPGA_PINMUX_IO3CTRL (0x0C) +#define SOCFPGA_PINMUX_IO4CTRL (0x10) +#define SOCFPGA_PINMUX_IO5CTRL (0x14) +#define SOCFPGA_PINMUX_IO6CTRL (0x18) +#define SOCFPGA_PINMUX_IO7CTRL (0x1C) +#define SOCFPGA_PINMUX_IO8CTRL (0x20) +#define SOCFPGA_PINMUX_IO9CTRL (0x24) +#define SOCFPGA_PINMUX_IO10CTRL (0x28) +#define SOCFPGA_PINMUX_IO11CTRL (0x2C) +#define SOCFPGA_PINMUX_IO12CTRL (0x30) +#define SOCFPGA_PINMUX_IO13CTRL (0x34) +#define SOCFPGA_PINMUX_IO14CTRL (0x38) +#define SOCFPGA_PINMUX_IO15CTRL (0x3C) +#define SOCFPGA_PINMUX_IO16CTRL (0x40) +#define SOCFPGA_PINMUX_IO17CTRL (0x44) +#define SOCFPGA_PINMUX_IO18CTRL (0x48) +#define SOCFPGA_PINMUX_IO19CTRL (0x4C) +#define SOCFPGA_PINMUX_IO20CTRL (0x50) +#define SOCFPGA_PINMUX_IO21CTRL (0x54) +#define SOCFPGA_PINMUX_IO22CTRL (0x58) +#define SOCFPGA_PINMUX_IO23CTRL (0x5C) +#define SOCFPGA_PINMUX_IO24CTRL (0x60) +#define SOCFPGA_PINMUX_IO25CTRL (0x64) +#define SOCFPGA_PINMUX_IO26CTRL (0x68) +#define SOCFPGA_PINMUX_IO27CTRL (0x6C) +#define SOCFPGA_PINMUX_IO28CTRL (0xD0) +#define SOCFPGA_PINMUX_IO29CTRL (0xD4) +#define SOCFPGA_PINMUX_IO30CTRL (0xD8) +#define SOCFPGA_PINMUX_IO31CTRL (0xDC) +#define SOCFPGA_PINMUX_IO32CTRL (0xE0) +#define SOCFPGA_PINMUX_IO33CTRL (0xE4) +#define SOCFPGA_PINMUX_IO34CTRL (0xE8) +#define SOCFPGA_PINMUX_IO35CTRL (0xEC) +#define SOCFPGA_PINMUX_IO36CTRL (0xF0) +#define SOCFPGA_PINMUX_IO37CTRL (0xF4) +#define SOCFPGA_PINMUX_IO38CTRL (0xF8) +#define SOCFPGA_PINMUX_IO39CTRL (0xFC) +#define SOCFPGA_PINMUX_IO40CTRL (0x100) +#define SOCFPGA_PINMUX_IO41CTRL (0x104) +#define SOCFPGA_PINMUX_IO42CTRL (0x108) +#define SOCFPGA_PINMUX_IO43CTRL (0x10C) +#define SOCFPGA_PINMUX_IO44CTRL (0x110) +#define SOCFPGA_PINMUX_IO45CTRL (0x114) +#define SOCFPGA_PINMUX_IO46CTRL (0x118) +#define SOCFPGA_PINMUX_IO47CTRL (0x11C) + +#define SOCFPGA_PINMUX_EMAC0_USEFPGA (0x00) +#define SOCFPGA_PINMUX_EMAC1_USEFPGA (0x04) +#define SOCFPGA_PINMUX_EMAC2_USEFPGA (0x08) +#define SOCFPGA_PINMUX_I2C0_USEFPGA (0x0C) +#define SOCFPGA_PINMUX_I2C1_USEFPGA (0x10) +#define SOCFPGA_PINMUX_I2C_EMAC0_USEFPGA (0x14) +#define SOCFPGA_PINMUX_I2C_EMAC1_USEFPGA (0x18) +#define SOCFPGA_PINMUX_I2C_EMAC2_USEFPGA (0x1C) +#define SOCFPGA_PINMUX_NAND_USEFPGA (0x20) +#define SOCFPGA_PINMUX_SPIM0_USEFPGA (0x28) +#define SOCFPGA_PINMUX_SPIM1_USEFPGA (0x2C) +#define SOCFPGA_PINMUX_SPIS0_USEFPGA (0x30) +#define SOCFPGA_PINMUX_SPIS1_USEFPGA (0x34) +#define SOCFPGA_PINMUX_UART0_USEFPGA (0x38) +#define SOCFPGA_PINMUX_UART1_USEFPGA (0x3C) +#define SOCFPGA_PINMUX_MDIO0_USEFPGA (0x40) +#define SOCFPGA_PINMUX_MDIO1_USEFPGA (0x44) +#define SOCFPGA_PINMUX_MDIO2_USEFPGA (0x48) +#define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50) +#define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54) + +#define SOCFPGA_PINMUX_IO0DELAY (0x00) +#define SOCFPGA_PINMUX_IO1DELAY (0x04) +#define SOCFPGA_PINMUX_IO2DELAY (0x08) +#define SOCFPGA_PINMUX_IO3DELAY (0x0C) +#define SOCFPGA_PINMUX_IO4DELAY (0x10) +#define SOCFPGA_PINMUX_IO5DELAY (0x14) +#define SOCFPGA_PINMUX_IO6DELAY (0x18) +#define SOCFPGA_PINMUX_IO7DELAY (0x1C) +#define SOCFPGA_PINMUX_IO8DELAY (0x20) +#define SOCFPGA_PINMUX_IO9DELAY (0x24) +#define SOCFPGA_PINMUX_IO10DELAY (0x28) +#define SOCFPGA_PINMUX_IO11DELAY (0x2C) +#define SOCFPGA_PINMUX_IO12DELAY (0x30) +#define SOCFPGA_PINMUX_IO13DELAY (0x34) +#define SOCFPGA_PINMUX_IO14DELAY (0x38) +#define SOCFPGA_PINMUX_IO15DELAY (0x3C) +#define SOCFPGA_PINMUX_IO16DELAY (0x40) +#define SOCFPGA_PINMUX_IO17DELAY (0x44) +#define SOCFPGA_PINMUX_IO18DELAY (0x48) +#define SOCFPGA_PINMUX_IO19DELAY (0x4C) +#define SOCFPGA_PINMUX_IO20DELAY (0x50) +#define SOCFPGA_PINMUX_IO21DELAY (0x54) +#define SOCFPGA_PINMUX_IO22DELAY (0x58) +#define SOCFPGA_PINMUX_IO23DELAY (0x5C) +#define SOCFPGA_PINMUX_IO24DELAY (0x60) +#define SOCFPGA_PINMUX_IO25DELAY (0x64) +#define SOCFPGA_PINMUX_IO26DELAY (0x68) +#define SOCFPGA_PINMUX_IO27DELAY (0x6C) +#define SOCFPGA_PINMUX_IO28DELAY (0x70) +#define SOCFPGA_PINMUX_IO29DELAY (0x74) +#define SOCFPGA_PINMUX_IO30DELAY (0x78) +#define SOCFPGA_PINMUX_IO31DELAY (0x7C) +#define SOCFPGA_PINMUX_IO32DELAY (0x80) +#define SOCFPGA_PINMUX_IO33DELAY (0x84) +#define SOCFPGA_PINMUX_IO34DELAY (0x88) +#define SOCFPGA_PINMUX_IO35DELAY (0x8C) +#define SOCFPGA_PINMUX_IO36DELAY (0x90) +#define SOCFPGA_PINMUX_IO37DELAY (0x94) +#define SOCFPGA_PINMUX_IO38DELAY (0x98) +#define SOCFPGA_PINMUX_IO39DELAY (0x9C) +#define SOCFPGA_PINMUX_IO40DELAY (0xA0) +#define SOCFPGA_PINMUX_IO41DELAY (0xA4) +#define SOCFPGA_PINMUX_IO42DELAY (0xA8) +#define SOCFPGA_PINMUX_IO43DELAY (0xAC) +#define SOCFPGA_PINMUX_IO44DELAY (0xB0) +#define SOCFPGA_PINMUX_IO45DELAY (0xB4) +#define SOCFPGA_PINMUX_IO46DELAY (0xB8) +#define SOCFPGA_PINMUX_IO47DELAY (0xBC) + +#define SOCFPGA_PINMUX_I3C0_USEFPGA (0xC0) +#define SOCFPGA_PINMUX_I3C1_USEFPGA (0xC4) + +#define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \ + + (SOCFPGA_PINMUX_##_reg)) + +void config_pinmux(handoff *handoff); +void config_peripheral(handoff *handoff); +#endif diff --git a/plat/intel/soc/agilex5/include/agilex5_power_manager.h b/plat/intel/soc/agilex5/include/agilex5_power_manager.h new file mode 100644 index 0000000..1bba74b --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_power_manager.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef POWERMANAGER_H +#define POWERMANAGER_H + +#include "socfpga_handoff.h" + +#define AGX5_PWRMGR_BASE 0x10d14000 + +/* DSU */ +#define AGX5_PWRMGR_DSU_FWENCTL 0x0 +#define AGX5_PWRMGR_DSU_PGENCTL 0x4 +#define AGX5_PWRMGR_DSU_PGSTAT 0x8 +#define AGX5_PWRMGR_DSU_PWRCTLR 0xc +#define AGX5_PWRMGR_DSU_PWRSTAT0 0x10 +#define AGX5_PWRMGR_DSU_PWRSTAT1 0x14 + +/* DSU Macros*/ +#define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1) +#define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1) +#define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8) +#define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31) +#define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff) +#define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8) +#define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16) +#define AGX5_PWRMGR_DSU_MULTI_PCH_DONE(x) (((x) & 0x1) << 31) + +/* CPU */ +#define AGX5_PWRMGR_CPU_PWRCTLR0 0x18 +#define AGX5_PWRMGR_CPU_PWRCTLR1 0x20 +#define AGX5_PWRMGR_CPU_PWRCTLR2 0x28 +#define AGX5_PWRMGR_CPU_PWRCTLR3 0x30 +#define AGX5_PWRMGR_CPU_PWRSTAT0 0x1c +#define AGX5_PWRMGR_CPU_PWRSTAT1 0x24 +#define AGX5_PWRMGR_CPU_PWRSTAT2 0x2c +#define AGX5_PWRMGR_CPU_PWRSTAT3 0x34 + +/* APS */ +#define AGX5_PWRMGR_APS_FWENCTL 0x38 +#define AGX5_PWRMGR_APS_PGENCTL 0x3C +#define AGX5_PWRMGR_APS_PGSTAT 0x40 + +/* PSS */ +#define AGX5_PWRMGR_PSS_FWENCTL 0x44 +#define AGX5_PWRMGR_PSS_PGENCTL 0x48 +#define AGX5_PWRMGR_PSS_PGSTAT 0x4c + +/* PSS Macros*/ +#define AGX5_PWRMGR_PSS_FWEN(x) ((x) & 0xff) +#define AGX5_PWRMGR_PSS_PGEN(x) ((x) & 0xff) +#define AGX5_PWRMGR_PSS_PGEN_OUT(x) ((x) & 0xff) + +/* MPU */ +#define AGX5_PWRMGR_MPU_PCHCTLR 0x50 +#define AGX5_PWRMGR_MPU_PCHSTAT 0x54 +#define AGX5_PWRMGR_MPU_BOOTCONFIG 0x58 +#define AGX5_PWRMGR_CPU_POWER_STATE_MASK 0x1E + +/* MPU Macros*/ +#define AGX5_PWRMGR_MPU_TRIGGER_PCH_DSU(x) ((x) & 0x1) +#define AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(x) (((x) & 0xf) << 1) +#define AGX5_PWRMGR_MPU_STATUS_PCH_CPU(x) (((x) & 0xf) << 1) + +/* Shared Macros */ +#define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ + (AGX5_PWRMGR_##_reg)) + +/* POWER MANAGER ERROR CODE */ +#define AGX5_PWRMGR_HANDOFF_PERIPHERAL -1 +#define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0 +#define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0) + +int pss_sram_power_off(handoff *hoff_ptr); +int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff); + +#endif diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h new file mode 100644 index 0000000..9a58cdb --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef AGX5_SOCFPGA_SYSTEMMANAGER_H +#define AGX5_SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ +#define SOCFPGA_SYSMGR_SILICONID_1 0x00 +#define SOCFPGA_SYSMGR_SILICONID_2 0x04 +#define SOCFPGA_SYSMGR_WDDBG 0x08 +#define SOCFPGA_SYSMGR_MPU_STATUS 0x10 +#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C +#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 +#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 +#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C +#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 +#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ +#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ +#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ +#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 +#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 +#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C +#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 +#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 +#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 +#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C +#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 +#define SOCFPGA_SYSMGR_OSC_TRIM 0x84 +#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 +#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C +#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 +#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C +#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 +/* NOC configuration value */ +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 +#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 +#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC +#define SOCFPGA_SYSMGR_GPO 0xE4 +#define SOCFPGA_SYSMGR_GPI 0xE8 +#define SOCFPGA_SYSMGR_MPU 0xF0 +#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 +#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 +#define SOCFPGA_SYSMGR_DFI_INTF 0xFC +#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 +#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 +#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 +#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C +#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 +#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 +#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 +#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C +#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 +#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 +#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 +#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C +#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 +#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 +#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 +#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 +#define SOCFPGA_SYSMGR_MPFE_status 0x22C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C + +#define DMA0_STREAM_CTRL_REG 0x10D1217C +#define DMA1_STREAM_CTRL_REG 0x10D12180 +#define SDM_STREAM_CTRL_REG 0x10D12184 +#define USB2_STREAM_CTRL_REG 0x10D12188 +#define USB3_STREAM_CTRL_REG 0x10D1218C +#define SDMMC_STREAM_CTRL_REG 0x10D12190 +#define NAND_STREAM_CTRL_REG 0x10D12194 +#define ETR_STREAM_CTRL_REG 0x10D12198 +#define TSN0_STREAM_CTRL_REG 0x10D1219C +#define TSN1_STREAM_CTRL_REG 0x10D121A0 +#define TSN2_STREAM_CTRL_REG 0x10D121A4 + +/* Stream ID configuration value for Agilex5 */ +#define TSN0 0x00010001 +#define TSN1 0x00020002 +#define TSN2 0x00030003 +#define NAND 0x00040004 +#define SDMMC 0x00050005 +#define USB0 0x00060006 +#define USB1 0x00070007 +#define DMA0 0x00080008 +#define DMA1 0x00090009 +#define SDM 0x000A000A +#define CORE_SIGHT_DEBUG 0x000B000B + +/* Field Masking */ +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) + +#define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0) +#define IDLE_DATA_LWSOC2FPGA BIT(4) +#define IDLE_DATA_SOC2FPGA BIT(0) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \ + | IDLE_DATA_SOC2FPGA) +#define SYSMGR_ECC_OCRAM_MASK BIT(1) +#define SYSMGR_ECC_DDR0_MASK BIT(16) +#define SYSMGR_ECC_DDR1_MASK BIT(17) + +#define WSTREAMIDEN_REG_CTRL BIT(0) +#define RSTREAMIDEN_REG_CTRL BIT(1) +#define WMMUSECSID_REG_VAL BIT(4) +#define RMMUSECSID_REG_VAL BIT(5) + +/* Macros */ +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) + +#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \ + | RSTREAMIDEN_REG_CTRL +#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \ + | RSTREAMIDEN_REG_CTRL \ + | WMMUSECSID_REG_VAL \ + | RMMUSECSID_REG_VAL + +#endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h new file mode 100644 index 0000000..8a49d61 --- /dev/null +++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include "agilex5_memory_controller.h" +#include "agilex5_system_manager.h" +#include <platform_def.h> + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ +#define XLAT_TABLES_V2 U(1) +#define PLAT_PRIMARY_CPU_A55 0x000 +#define PLAT_PRIMARY_CPU_A76 0x200 +#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT +#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT +#define PLAT_L2_RESET_REQ 0xB007C0DE + +/* System Counter */ /* TODO: Update back to 400MHz */ +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (80000000) +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (80) + +/* FPGA config helpers */ +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 + +/* QSPI Setting */ +#define CAD_QSPIDATA_OFST 0x10900000 +#define CAD_QSPI_OFFSET 0x108d2000 + +/* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 +#define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 + +#define SOCFPGA_MMC_REG_BASE 0x10808000 +#define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 +#define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 +#define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 +#define SOCFPGA_PINMUX_REG_BASE 0x10d13000 +#define SOCFPGA_NAND_REG_BASE 0x10B80000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 + +/* Define maximum page size for NAND flash devices */ +#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x80000000) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0x00000000) +#define OCRAM_SIZE (0x00080000) + +#define MEM64_BASE (0x0080000000) +#define MEM64_SIZE (0x0080000000) + +//128MB PSS +#define PSS_BASE (0x10000000) +#define PSS_SIZE (0x08000000) + +//64MB MPFE +#define MPFE_BASE (0x18000000) +#define MPFE_SIZE (0x04000000) + +//16MB CCU +#define CCU_BASE (0x1C000000) +#define CCU_SIZE (0x01000000) + +//1MB GIC +#define GIC_BASE (0x1D000000) +#define GIC_SIZE (0x00100000) + +#define BL2_BASE (0x00000000) +#define BL2_LIMIT (0x0001b000) + +#define BL31_BASE (0x80000000) +#define BL31_LIMIT (0x82000000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0x10C02000) +#define PLAT_UART1_BASE (0x10C02100) + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define PLAT_GIC_BASE (0x1D000000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) +#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) + +#define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE + +/******************************************************************************* + * SDMMC related pointer function + ******************************************************************************/ +#define SDMMC_READ_BLOCKS sdmmc_read_blocks +#define SDMMC_WRITE_BLOCKS sdmmc_write_blocks + +/******************************************************************************* + * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset + * is done and HPS should trigger warm reset via RMR_EL3. + ******************************************************************************/ +#define L2_RESET_DONE_REG 0x10D12218 + +#endif /* PLAT_SOCFPGA_DEF_H */ |