diff options
Diffstat (limited to 'plat/intel/soc/stratix10/include')
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_clock_manager.h | 101 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_memory_controller.h | 160 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_mmc.h | 12 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_pinmux.h | 20 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_system_manager.h | 194 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/socfpga_plat_def.h | 105 |
6 files changed, 592 insertions, 0 deletions
diff --git a/plat/intel/soc/stratix10/include/s10_clock_manager.h b/plat/intel/soc/stratix10/include/s10_clock_manager.h new file mode 100644 index 0000000..5f76375 --- /dev/null +++ b/plat/intel/soc/stratix10/include/s10_clock_manager.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CLOCKMANAGER_H__ +#define __CLOCKMANAGER_H__ + +#include "s10_system_manager.h" +#include "socfpga_handoff.h" + +#define ALT_CLKMGR 0xffd10000 + +#define ALT_CLKMGR_CTRL 0x0 +#define ALT_CLKMGR_STAT 0x4 +#define ALT_CLKMGR_INTRCLR 0x14 +#define ALT_CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 +#define ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 + +#define ALT_CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 +#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1 +#define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) +#define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) +#define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9) + +#define ALT_CLKMGR_MAINPLL 0xffd10030 +#define ALT_CLKMGR_MAINPLL_EN 0x0 +#define ALT_CLKMGR_MAINPLL_BYPASS 0xc +#define ALT_CLKMGR_MAINPLL_MPUCLK 0x18 +#define ALT_CLKMGR_MAINPLL_NOCCLK 0x1c +#define ALT_CLKMGR_MAINPLL_CNTR2CLK 0x20 +#define ALT_CLKMGR_MAINPLL_CNTR3CLK 0x24 +#define ALT_CLKMGR_MAINPLL_CNTR4CLK 0x28 +#define ALT_CLKMGR_MAINPLL_CNTR5CLK 0x2c +#define ALT_CLKMGR_MAINPLL_CNTR6CLK 0x30 +#define ALT_CLKMGR_MAINPLL_CNTR7CLK 0x34 +#define ALT_CLKMGR_MAINPLL_CNTR8CLK 0x38 +#define ALT_CLKMGR_MAINPLL_CNTR9CLK 0x3c +#define ALT_CLKMGR_MAINPLL_NOCDIV 0x40 +#define ALT_CLKMGR_MAINPLL_PLLGLOB 0x44 +#define ALT_CLKMGR_MAINPLL_FDBCK 0x48 +#define ALT_CLKMGR_MAINPLL_PLLC0 0x54 +#define ALT_CLKMGR_MAINPLL_PLLC1 0x58 +#define ALT_CLKMGR_MAINPLL_VCOCALIB 0x5c +#define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff +#define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) +#define ALT_CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001 +#define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) +#define ALT_CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002 +#define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) +#define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) + +#define ALT_CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) +#define ALT_CLKMGR_SRC_MAIN 0 +#define ALT_CLKMGR_SRC_PER 1 + +#define ALT_CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 +#define ALT_CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 +#define ALT_CLKMGR_PLLGLOB_PSRC_F2S 0x2 + +#define ALT_CLKMGR_PERPLL 0xffd100a4 +#define ALT_CLKMGR_PERPLL_EN 0x0 +#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) +#define ALT_CLKMGR_PERPLL_BYPASS 0xc +#define ALT_CLKMGR_PERPLL_CNTR2CLK 0x18 +#define ALT_CLKMGR_PERPLL_CNTR3CLK 0x1c +#define ALT_CLKMGR_PERPLL_CNTR4CLK 0x20 +#define ALT_CLKMGR_PERPLL_CNTR5CLK 0x24 +#define ALT_CLKMGR_PERPLL_CNTR6CLK 0x28 +#define ALT_CLKMGR_PERPLL_CNTR7CLK 0x2c +#define ALT_CLKMGR_PERPLL_CNTR8CLK 0x30 +#define ALT_CLKMGR_PERPLL_CNTR9CLK 0x34 +#define ALT_CLKMGR_PERPLL_GPIODIV 0x3c +#define ALT_CLKMGR_PERPLL_EMACCTL 0x38 +#define ALT_CLKMGR_PERPLL_PLLGLOB 0x40 +#define ALT_CLKMGR_PERPLL_FDBCK 0x44 +#define ALT_CLKMGR_PERPLL_PLLC0 0x50 +#define ALT_CLKMGR_PERPLL_PLLC1 0x54 +#define ALT_CLKMGR_PERPLL_EN_RESET 0x00000fff +#define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) +#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) +#define ALT_CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001 +#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) +#define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV_SET(x) (((x) << 8) & 0x00003f00) +#define ALT_CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002 +#define ALT_CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) +#define ALT_CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) +#define ALT_CLKMGR_PERPLL_VCOCALIB 0x58 + +#define ALT_CLKMGR_INTOSC_HZ 460000000 + +void config_clkmgr_handoff(handoff *hoff_ptr); +uint32_t get_wdt_clk(void); +uint32_t get_uart_clk(void); +uint32_t get_mmc_clk(void); +uint32_t get_l3_clk(uint32_t ref_clk); +uint32_t get_ref_clk(uint32_t pllglob); +uint32_t get_cpu_clk(void); + +#endif diff --git a/plat/intel/soc/stratix10/include/s10_memory_controller.h b/plat/intel/soc/stratix10/include/s10_memory_controller.h new file mode 100644 index 0000000..155b279 --- /dev/null +++ b/plat/intel/soc/stratix10/include/s10_memory_controller.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __S10_MEMORYCONTROLLER_H__ +#define __S10_MEMORYCONTROLLER_H__ + +#define S10_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8 +#define S10_MPFE_IOHMC_CTRLCFG0 0xf8010028 +#define S10_MPFE_IOHMC_CTRLCFG1 0xf801002c +#define S10_MPFE_IOHMC_DRAMADDRW 0xf80100a8 +#define S10_MPFE_IOHMC_DRAMTIMING0 0xf8010050 +#define S10_MPFE_IOHMC_CALTIMING0 0xf801007c +#define S10_MPFE_IOHMC_CALTIMING1 0xf8010080 +#define S10_MPFE_IOHMC_CALTIMING2 0xf8010084 +#define S10_MPFE_IOHMC_CALTIMING3 0xf8010088 +#define S10_MPFE_IOHMC_CALTIMING4 0xf801008c +#define S10_MPFE_IOHMC_CALTIMING9 0xf80100a0 +#define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) +#define S10_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \ + (((value) & 0x00000060) >> 5) + + +#define S10_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 +#define S10_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 +#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 +#define S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff +#define S10_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 + + +#define S10_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c + +#define S10_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110 + +#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) +#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) +#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) +#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) +#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) + +#define S10_MPFE_DDR(x) (0xf8000000 + x) +#define S10_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c +#define S10_MPFE_DDR_MAIN_SCHED 0xf8000400 +#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408 +#define S10_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c +#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f +#define S10_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410 +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c +#define S10_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414 +#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438 +#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 +#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4 +#define S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0 +#define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0 +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1)) +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2 +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3)) +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4 +#define S10_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5)) + +#define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x)) +#define S10_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210 +#define S10_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008 +#define HMC_ADP_DDRIOCTRL 0x8 +#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) +#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9) +#define ADP_DRAMADDRWIDTH 0xe0 + +#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) +#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) + +/* timing 2 */ +#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) +#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) +#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) +#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) + +/* timing 3 */ +#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12) +#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) + +/* timing 4 */ +#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6) + +#define DDRTIMING_BWRATIO_OFST 31 +#define DDRTIMING_WRTORD_OFST 26 +#define DDRTIMING_RDTOWR_OFST 21 +#define DDRTIMING_BURSTLEN_OFST 18 +#define DDRTIMING_WRTOMISS_OFST 12 +#define DDRTIMING_RDTOMISS_OFST 6 +#define DDRTIMING_ACTTOACT_OFST 0 + +#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) + +#define DDRMODE_AUTOPRECHARGE_OFST 1 +#define DDRMODE_BWRATIOEXTENDED_OFST 0 + + +#define S10_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x0000007f) >> 0) +#define S10_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0000000f) >> 0) + +#define S10_CCU_CPU0_MPRT_DDR 0xf7004400 +#define S10_CCU_CPU0_MPRT_MEM0 0xf70045c0 +#define S10_CCU_CPU0_MPRT_MEM1A 0xf70045e0 +#define S10_CCU_CPU0_MPRT_MEM1B 0xf7004600 +#define S10_CCU_CPU0_MPRT_MEM1C 0xf7004620 +#define S10_CCU_CPU0_MPRT_MEM1D 0xf7004640 +#define S10_CCU_CPU0_MPRT_MEM1E 0xf7004660 +#define S10_CCU_IOM_MPRT_MEM0 0xf7018560 +#define S10_CCU_IOM_MPRT_MEM1A 0xf7018580 +#define S10_CCU_IOM_MPRT_MEM1B 0xf70185a0 +#define S10_CCU_IOM_MPRT_MEM1C 0xf70185c0 +#define S10_CCU_IOM_MPRT_MEM1D 0xf70185e0 +#define S10_CCU_IOM_MPRT_MEM1E 0xf7018600 + +#define S10_NOC_FW_DDR_SCR 0xf8020100 +#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802011c +#define S10_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020118 +#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802019c +#define S10_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020198 + +#define S10_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020100 +#define S10_CCU_NOC_DI_SET_MSK 0x10 + +#define S10_SYSMGR_CORE_HMC_CLK 0xffd120b4 +#define S10_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001 + +#define S10_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0x0000ffff) >> 0) +#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 +#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0 +#define S10_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f +#define S10_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7 + +#define S10_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000 +#define S10_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100 +#define S10_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001 + +#define S10_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001 +#define S10_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 +#define S10_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100 +#define S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x00000001) >> 0) + + +#define S10_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) +#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) +#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) +#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) +#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) +#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) + +#define S10_SDRAM_0_LB_ADDR 0x0 + +int init_hard_memory_controller(void); + +#endif diff --git a/plat/intel/soc/stratix10/include/s10_mmc.h b/plat/intel/soc/stratix10/include/s10_mmc.h new file mode 100644 index 0000000..99f86f5 --- /dev/null +++ b/plat/intel/soc/stratix10/include/s10_mmc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __S10_MMC_H__ +#define __S10_MMC_H__ + +void s10_mmc_init(void); + +#endif /* S10_MMC_H */ diff --git a/plat/intel/soc/stratix10/include/s10_pinmux.h b/plat/intel/soc/stratix10/include/s10_pinmux.h new file mode 100644 index 0000000..82367d7 --- /dev/null +++ b/plat/intel/soc/stratix10/include/s10_pinmux.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __S10_PINMUX_H__ +#define __S10_PINMUX_H__ + +#define S10_PINMUX_PIN0SEL 0xffd13000 +#define S10_PINMUX_IO0CTRL 0xffd13130 +#define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300 +#define S10_PINMUX_IO0_DELAY 0xffd13400 + +#include "socfpga_handoff.h" + +void config_pinmux(handoff *handoff); + +#endif + diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h new file mode 100644 index 0000000..88c0b46 --- /dev/null +++ b/plat/intel/soc/stratix10/include/s10_system_manager.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef S10_SOCFPGA_SYSTEMMANAGER_H +#define S10_SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ +#define SOCFPGA_SYSMGR_SILICONID_1 0x00 +#define SOCFPGA_SYSMGR_SILICONID_2 0x04 +#define SOCFPGA_SYSMGR_WDDBG 0x08 +#define SOCFPGA_SYSMGR_MPU_STATUS 0x10 +#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C +#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 +#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 +#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C +#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 +#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ +#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ +#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ +#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 +#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 +#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C +#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 +#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 +#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 +#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C +#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 +#define SOCFPGA_SYSMGR_OSC_TRIM 0x84 +#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 +#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C +#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 +#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C +#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 +/* NOC configuration value for Agilex5 */ +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 +#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 +#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC +#define SOCFPGA_SYSMGR_GPO 0xE4 +#define SOCFPGA_SYSMGR_GPI 0xE8 +#define SOCFPGA_SYSMGR_MPU 0xF0 +#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 +#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 +#define SOCFPGA_SYSMGR_DFI_INTF 0xFC +#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 +#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 +#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 +#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C +#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 +#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 +#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 +#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C +#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 +#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 +#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 +#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C +#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 +#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 +#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 +#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 +#define SOCFPGA_SYSMGR_MPFE_status 0x22C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C + +#define DMA0_STREAM_CTRL_REG 0x10D1217C +#define DMA1_STREAM_CTRL_REG 0x10D12180 +#define SDM_STREAM_CTRL_REG 0x10D12184 +#define USB2_STREAM_CTRL_REG 0x10D12188 +#define USB3_STREAM_CTRL_REG 0x10D1218C +#define SDMMC_STREAM_CTRL_REG 0x10D12190 +#define NAND_STREAM_CTRL_REG 0x10D12194 +#define ETR_STREAM_CTRL_REG 0x10D12198 +#define TSN0_STREAM_CTRL_REG 0x10D1219C +#define TSN1_STREAM_CTRL_REG 0x10D121A0 +#define TSN2_STREAM_CTRL_REG 0x10D121A4 + +/* Stream ID configuration value for Agilex5 */ +#define TSN0 0x00010001 +#define TSN1 0x00020002 +#define TSN2 0x00030003 +#define NAND 0x00040004 +#define SDMMC 0x00050005 +#define USB0 0x00060006 +#define USB1 0x00070007 +#define DMA0 0x00080008 +#define DMA1 0x00090009 +#define SDM 0x000A000A +#define CORE_SIGHT_DEBUG 0x000B000B + +/* Field Masking */ +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) +#define IDLE_DATA_LWSOC2FPGA BIT(4) +#define IDLE_DATA_SOC2FPGA BIT(0) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) +#define SYSMGR_ECC_OCRAM_MASK BIT(1) +#define SYSMGR_ECC_DDR0_MASK BIT(16) +#define SYSMGR_ECC_DDR1_MASK BIT(17) +#define WSTREAMIDEN_REG_CTRL BIT(0) +#define RSTREAMIDEN_REG_CTRL BIT(1) +#define WMMUSECSID_REG_VAL BIT(4) +#define RMMUSECSID_REG_VAL BIT(5) + +/* Macros */ + +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) +#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL | \ + RSTREAMIDEN_REG_CTRL +#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL | \ + RSTREAMIDEN_REG_CTRL | \ + WMMUSECSID_REG_VAL | RMMUSECSID_REG_VAL + +#endif /* S10_SOCFPGA_SYSTEMMANAGER_H */ diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h new file mode 100644 index 0000000..7c9f15a --- /dev/null +++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include <platform_def.h> +#include "s10_system_manager.h" + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#define PLAT_PRIMARY_CPU 0 +#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT +#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT + +/* FPGA config helpers */ +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 + +/* QSPI Setting */ +#define CAD_QSPIDATA_OFST 0xff900000 +#define CAD_QSPI_OFFSET 0xff8d2000 + +/* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 +#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) + +#define SOCFPGA_MMC_REG_BASE 0xff808000 + +#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 +#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x0) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0xFFE00000) +#define OCRAM_SIZE (0x00040000) + +#define MEM64_BASE (0x0100000000) +#define MEM64_SIZE (0x1F00000000) + +#define DEVICE1_BASE (0x80000000) +#define DEVICE1_SIZE (0x60000000) + +#define DEVICE2_BASE (0xF7000000) +#define DEVICE2_SIZE (0x08E00000) + +#define DEVICE3_BASE (0xFFFC0000) +#define DEVICE3_SIZE (0x00008000) + +#define DEVICE4_BASE (0x2000000000) +#define DEVICE4_SIZE (0x0100000000) + +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) + +#define BL31_BASE (0x1000) +#define BL31_LIMIT (0x81000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0xFFC02000) +#define PLAT_UART1_BASE (0xFFC02100) + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define PLAT_GIC_BASE (0xFFFC0000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) +#define PLAT_GICR_BASE 0 + +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) +#define PLAT_HZ_CONVERT_TO_MHZ (1000000) + +/******************************************************************************* + * SDMMC related pointer function + ******************************************************************************/ +#define SDMMC_READ_BLOCKS mmc_read_blocks +#define SDMMC_WRITE_BLOCKS mmc_write_blocks + +/******************************************************************************* + * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset + * is done and HPS should trigger warm reset via RMR_EL3. + ******************************************************************************/ +#define L2_RESET_DONE_REG 0xFFD12218 + +/* Platform specific system counter */ +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk() + +#endif /* PLATSOCFPGA_DEF_H */ + |