1 files changed, 91 insertions, 0 deletions
diff --git a/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
new file mode 100644
index 0000000..89c9c0a
--- /dev/null
+++ b/plat/nxp/soc-ls1046a/ls1046aqds/ddr_init.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2018-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+#include <errata.h>
+#include "platform_def.h"
+
+static const struct rc_timing rce[] = {
+	{U(1600), U(8), U(7)},
+	{U(1867), U(8), U(7)},
+	{U(2134), U(8), U(9)},
+	{}
+};
+
+static const struct board_timing udimm[] = {
+	{U(0x04), rce, U(0x01020304), U(0x06070805)},
+};
+
+int ddr_board_options(struct ddr_info *priv)
+{
+	int ret;
+	struct memctl_opt *popts = &priv->opt;
+
+	if (popts->rdimm) {
+		debug("RDIMM parameters not set.\n");
+		return -EINVAL;
+	}
+
+	ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
+	if (ret != 0) {
+		return ret;
+	}
+
+	popts->wrlvl_override = U(1);
+	popts->wrlvl_sample = U(0x0);	/* 32 clocks */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN	|
+			  DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm)	|
+			  DDR_CDR2_VREF_TRAIN_EN		|
+			  DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = U(0x70);
+
+	return 0;
+}
+
+long long init_ddr(void)
+{
+	int spd_addr[] = { NXP_SPD_EEPROM0 };
+	struct ddr_info info;
+	struct sysinfo sys;
+	long long dram_size;
+
+	zeromem(&sys, sizeof(sys));
+	if (get_clocks(&sys)) {
+		ERROR("System clocks are not set\n");
+		assert(0);
+	}
+	debug("platform clock %lu\n", sys.freq_platform);
+	debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+	debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+	zeromem(&info, sizeof(struct ddr_info));
+	info.num_ctlrs = 1;
+	info.dimm_on_ctlr = 1;
+	info.clk = get_ddr_freq(&sys, 0);
+	info.spd_addr = spd_addr;
+	info.ddr[0] = (void *)NXP_DDR_ADDR;
+
+	dram_size = dram_init(&info);
+
+	if (dram_size < 0) {
+		ERROR("DDR init failed.\n");
+	}
+
+#ifdef ERRATA_SOC_A008850
+	erratum_a008850_post();
+#endif
+
+	return dram_size;
+}