1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
|
/*
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <arch.h>
#include <arch_helpers.h>
#include <drivers/arm/gic600ae_fmu.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#define GICFMU_IDLE_TIMEOUT_US U(2000000)
/* Macro to write 32-bit FMU registers */
#define GIC_FMU_WRITE_32(base, reg, val) \
do { \
/* \
* This register receives the unlock key that is required for \
* writes to FMU registers to be successful. \
*/ \
mmio_write_32(base + GICFMU_KEY, 0xBE); \
/* Perform the actual write */ \
mmio_write_32((base) + (reg), (val)); \
} while (false)
/* Macro to write 64-bit FMU registers */
#define GIC_FMU_WRITE_64(base, reg, n, val) \
do { \
/* \
* This register receives the unlock key that is required for \
* writes to FMU registers to be successful. \
*/ \
mmio_write_32(base + GICFMU_KEY, 0xBE); \
/* \
* APB bus is 32-bit wide; so split the 64-bit write into \
* two 32-bit writes \
*/ \
mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
} while (false)
/* Helper function to wait until FMU is ready to accept the next command */
static void wait_until_fmu_is_idle(uintptr_t base)
{
uint32_t timeout_count = GICFMU_IDLE_TIMEOUT_US;
uint64_t status;
/* wait until status is 'busy' */
do {
status = (gic_fmu_read_status(base) & BIT(0));
if (timeout_count-- == 0U) {
ERROR("GIC600 AE FMU is not responding\n");
panic();
}
udelay(1U);
} while (status == U(0));
}
#define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \
do { \
/* Wait until FMU is ready */ \
wait_until_fmu_is_idle(base); \
/* Actual register write */ \
GIC_FMU_WRITE_32(base, reg, val); \
/* Wait until FMU is ready */ \
wait_until_fmu_is_idle(base); \
} while (false)
#define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \
do { \
/* Wait until FMU is ready */ \
wait_until_fmu_is_idle(base); \
/* Actual register write */ \
GIC_FMU_WRITE_64(base, reg, n, val); \
/* Wait until FMU is ready */ \
wait_until_fmu_is_idle(base); \
} while (false)
/*******************************************************************************
* GIC FMU functions for accessing the Fault Management Unit registers
******************************************************************************/
/*
* Accessors to read the Error Record Feature Register bits corresponding
* to an error record 'n'
*/
uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n)
{
/*
* APB bus is 32-bit wide; so split the 64-bit read into
* two 32-bit reads
*/
uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U);
reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32);
return reg_val;
}
/*
* Accessors to read the Error Record Control Register bits corresponding
* to an error record 'n'
*/
uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n)
{
/*
* APB bus is 32-bit wide; so split the 64-bit read into
* two 32-bit reads
*/
uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U);
reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32);
return reg_val;
}
/*
* Accessors to read the Error Record Primary Status Register bits
* corresponding to an error record 'n'
*/
uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n)
{
/*
* APB bus is 32-bit wide; so split the 64-bit read into
* two 32-bit reads
*/
uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U);
reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32);
return reg_val;
}
/*
* Accessors to read the Error Group Status Register
*/
uint64_t gic_fmu_read_errgsr(uintptr_t base)
{
/*
* APB bus is 32-bit wide; so split the 64-bit read into
* two 32-bit reads
*/
uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRGSR_LO);
reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRGSR_HI) << 32);
return reg_val;
}
/*
* Accessors to read the Ping Control Register
*/
uint32_t gic_fmu_read_pingctlr(uintptr_t base)
{
return mmio_read_32(base + GICFMU_PINGCTLR);
}
/*
* Accessors to read the Ping Now Register
*/
uint32_t gic_fmu_read_pingnow(uintptr_t base)
{
return mmio_read_32(base + GICFMU_PINGNOW);
}
/*
* Accessors to read the Ping Mask Register
*/
uint64_t gic_fmu_read_pingmask(uintptr_t base)
{
/*
* APB bus is 32-bit wide; so split the 64-bit read into
* two 32-bit reads
*/
uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_PINGMASK_LO);
reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_PINGMASK_HI) << 32);
return reg_val;
}
/*
* Accessors to read the FMU Status Register
*/
uint32_t gic_fmu_read_status(uintptr_t base)
{
return mmio_read_32(base + GICFMU_STATUS);
}
/*
* Accessors to read the Error Record ID Register
*/
uint32_t gic_fmu_read_erridr(uintptr_t base)
{
return mmio_read_32(base + GICFMU_ERRIDR);
}
/*
* Accessors to write a 64 bit value to the Error Record Control Register
*/
void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val)
{
GIC_FMU_WRITE_64(base, GICFMU_ERRCTLR, n, val);
}
/*
* Accessors to write a 64 bit value to the Error Record Primary Status
* Register
*/
void gic_fmu_write_errstatus(uintptr_t base, unsigned int n, uint64_t val)
{
/* Wait until FMU is ready before writing */
GIC_FMU_WRITE_ON_IDLE_64(base, GICFMU_ERRSTATUS, n, val);
}
/*
* Accessors to write a 32 bit value to the Ping Control Register
*/
void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val)
{
GIC_FMU_WRITE_32(base, GICFMU_PINGCTLR, val);
}
/*
* Accessors to write a 32 bit value to the Ping Now Register
*/
void gic_fmu_write_pingnow(uintptr_t base, uint32_t val)
{
/* Wait until FMU is ready before writing */
GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_PINGNOW, val);
}
/*
* Accessors to write a 32 bit value to the Safety Mechanism Enable Register
*/
void gic_fmu_write_smen(uintptr_t base, uint32_t val)
{
/* Wait until FMU is ready before writing */
GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMEN, val);
}
/*
* Accessors to write a 32 bit value to the Safety Mechanism Inject Error
* Register
*/
void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val)
{
/* Wait until FMU is ready before writing */
GIC_FMU_WRITE_ON_IDLE_32(base, GICFMU_SMINJERR, val);
}
/*
* Accessors to write a 64 bit value to the Ping Mask Register
*/
void gic_fmu_write_pingmask(uintptr_t base, uint64_t val)
{
GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
}
/*
* Helper function to disable all safety mechanisms for a given block
*/
void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid)
{
uint32_t smen, max_smid = U(0);
/* Sanity check block ID */
assert((blkid >= FMU_BLK_GICD) && (blkid <= FMU_BLK_PPI31));
/* Find the max safety mechanism ID for the block */
switch (blkid) {
case FMU_BLK_GICD:
max_smid = FMU_SMID_GICD_MAX;
break;
case FMU_BLK_SPICOL:
max_smid = FMU_SMID_SPICOL_MAX;
break;
case FMU_BLK_WAKERQ:
max_smid = FMU_SMID_WAKERQ_MAX;
break;
case FMU_BLK_ITS0...FMU_BLK_ITS7:
max_smid = FMU_SMID_ITS_MAX;
break;
case FMU_BLK_PPI0...FMU_BLK_PPI31:
max_smid = FMU_SMID_PPI_MAX;
break;
default:
assert(false);
break;
}
/* Disable all Safety Mechanisms for a given block id */
for (unsigned int i = 0U; i < max_smid; i++) {
smen = (blkid << FMU_SMEN_BLK_SHIFT) | (i << FMU_SMEN_SMID_SHIFT);
gic_fmu_write_smen(base, smen);
}
}
|
