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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) 2023, Protonic Holland - All Rights Reserved
* Author: David Jander <david@protonic.nl>
*/
/dts-v1/;
#include "stm32mp151.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxad-pinctrl.dtsi"
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-ddr3-1x2Gb-1066-binG.dtsi"
/ {
model = "Protonic PRTT1A";
compatible = "prt,prtt1a", "st,stm32mp151";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
serial0 = &uart4;
};
memory@c0000000 {
device_type = "memory";
reg = <0xC0000000 0x10000000>;
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
secure-status = "okay";
};
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a
&qspi_bk1_pins_a
&qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <104000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&qspi_bk1_pins_a {
pins {
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
};
};
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSI
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSI
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSI
>;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = <2 80 0 0 0 PQR(1,0,0)>;
frac = <0x800>;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = <2 65 1 0 0 PQR(1,1,1)>;
frac = <0x1400>;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = <1 33 1 16 36 PQR(1,1,1)>;
frac = <0x1a04>;
};
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = <1 39 3 11 4 PQR(1,1,1)>;
};
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
bus-width = <4>;
status = "okay";
};
&sdmmc1_b4_pins_a {
pins1 {
bias-pull-up;
};
pins2 {
bias-pull-up;
};
};
/* NOTE: Although the PRTT1A does not have an eMMC, we declare it
* anyway, in order to be able to use the same binary for the
* PRTT1C also. All involved pins are N.C. on PRTT1A/S for that
* reason, so it should do no harm. All inputs configured with
* pull-ups to avoid floating inputs. */
&sdmmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
bus-width = <8>;
status = "okay";
};
&sdmmc2_b4_pins_a {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
<STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
};
};
&sdmmc2_d47_pins_a {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
};
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
&uart4_pins_a {
pins1 {
pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-pull-up;
};
};
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