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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-12 05:43:14 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-12 05:43:14 +0000 |
commit | 8dd16259287f58f9273002717ec4d27e97127719 (patch) | |
tree | 3863e62a53829a84037444beab3abd4ed9dfc7d0 /third_party/rust/wasm-encoder/src/core/code.rs | |
parent | Releasing progress-linux version 126.0.1-1~progress7.99u1. (diff) | |
download | firefox-8dd16259287f58f9273002717ec4d27e97127719.tar.xz firefox-8dd16259287f58f9273002717ec4d27e97127719.zip |
Merging upstream version 127.0.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'third_party/rust/wasm-encoder/src/core/code.rs')
-rw-r--r-- | third_party/rust/wasm-encoder/src/core/code.rs | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/third_party/rust/wasm-encoder/src/core/code.rs b/third_party/rust/wasm-encoder/src/core/code.rs index 76bfd7afde..4b04b0b72b 100644 --- a/third_party/rust/wasm-encoder/src/core/code.rs +++ b/third_party/rust/wasm-encoder/src/core/code.rs @@ -274,6 +274,34 @@ impl Encode for MemArg { } } +/// The memory ordering for atomic instructions. +/// +/// For an in-depth explanation of memory orderings, see the C++ documentation +/// for [`memory_order`] or the Rust documentation for [`atomic::Ordering`]. +/// +/// [`memory_order`]: https://en.cppreference.com/w/cpp/atomic/memory_order +/// [`atomic::Ordering`]: https://doc.rust-lang.org/std/sync/atomic/enum.Ordering.html +#[derive(Clone, Copy, Debug)] +pub enum Ordering { + /// For a load, it acquires; this orders all operations before the last + /// "releasing" store. For a store, it releases; this orders all operations + /// before it at the next "acquiring" load. + AcqRel, + /// Like `AcqRel` but all threads see all sequentially consistent operations + /// in the same order. + SeqCst, +} + +impl Encode for Ordering { + fn encode(&self, sink: &mut Vec<u8>) { + let flag: u8 = match self { + Ordering::SeqCst => 0, + Ordering::AcqRel => 1, + }; + sink.push(flag); + } +} + /// Describe an unchecked SIMD lane index. pub type Lane = u8; @@ -980,6 +1008,16 @@ pub enum Instruction<'a> { I64AtomicRmw8CmpxchgU(MemArg), I64AtomicRmw16CmpxchgU(MemArg), I64AtomicRmw32CmpxchgU(MemArg), + + // More atomic instructions (the shared-everything-threads proposal) + GlobalAtomicGet { + ordering: Ordering, + global_index: u32, + }, + GlobalAtomicSet { + ordering: Ordering, + global_index: u32, + }, } impl Encode for Instruction<'_> { @@ -2787,7 +2825,7 @@ impl Encode for Instruction<'_> { 0x113u32.encode(sink); } - // Atmoic instructions from the thread proposal + // Atomic instructions from the thread proposal Instruction::MemoryAtomicNotify(memarg) => { sink.push(0xFE); sink.push(0x00); @@ -3123,6 +3161,26 @@ impl Encode for Instruction<'_> { sink.push(0x4E); memarg.encode(sink); } + + // Atomic instructions from the shared-everything-threads proposal + Instruction::GlobalAtomicGet { + ordering, + global_index, + } => { + sink.push(0xFE); + sink.push(0x4F); + ordering.encode(sink); + global_index.encode(sink); + } + Instruction::GlobalAtomicSet { + ordering, + global_index, + } => { + sink.push(0xFE); + sink.push(0x50); + ordering.encode(sink); + global_index.encode(sink); + } } } } |