Adding upstream version 20230625.upstream/20230625upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

4 files changed, 137 insertions, 0 deletions

diff --git a/dsp56k/Makefile b/dsp56k/Makefile
new file mode 100644
index 0000000..c758a28
--- /dev/null
+++ b/dsp56k/Makefile
@@ -0,0 +1,6 @@
+bootstrap.bin: bootstrap.asm concat-bootstrap.pl
+	a56 bootstrap.asm >/dev/null
+	perl concat-bootstrap.pl <a56.out >bootstrap.bin
+
+clean:
+	rm -f a56.out bootstrap.bin
diff --git a/dsp56k/bootstrap.asm b/dsp56k/bootstrap.asm
new file mode 100644
index 0000000..a411047
--- /dev/null
+++ b/dsp56k/bootstrap.asm
@@ -0,0 +1,98 @@
+; Author: Frederik Noring <noring@nocrew.org>
+;
+; This file is subject to the terms and conditions of the GNU General Public
+; License.  See the file COPYING in the main directory of this archive
+; for more details.
+
+; DSP56k loader
+
+; Host Interface
+M_BCR   EQU     $FFFE           ; Port A Bus Control Register
+M_PBC   EQU     $FFE0           ; Port B Control Register
+M_PBDDR EQU     $FFE2           ; Port B Data Direction Register
+M_PBD   EQU     $FFE4           ; Port B Data Register
+M_PCC   EQU     $FFE1           ; Port C Control Register
+M_PCDDR EQU     $FFE3           ; Port C Data Direction Register
+M_PCD   EQU     $FFE5           ; Port C Data Register
+
+M_HCR   EQU     $FFE8           ; Host Control Register
+M_HSR   EQU     $FFE9           ; Host Status Register
+M_HRX   EQU     $FFEB           ; Host Receive Data Register
+M_HTX   EQU     $FFEB           ; Host Transmit Data Register
+
+; SSI, Synchronous Serial Interface
+M_RX    EQU     $FFEF           ; Serial Receive Data Register
+M_TX    EQU     $FFEF           ; Serial Transmit Data Register
+M_CRA   EQU     $FFEC           ; SSI Control Register A
+M_CRB   EQU     $FFED           ; SSI Control Register B
+M_SR    EQU     $FFEE           ; SSI Status Register
+M_TSR   EQU     $FFEE           ; SSI Time Slot Register
+
+; Exception Processing
+M_IPR   EQU     $FFFF           ; Interrupt Priority Register
+
+        org     P:$0
+start   jmp     <$40
+
+        org     P:$40
+;       ; Zero 16384 DSP X and Y words
+;       clr     A #0,r0
+;       clr     B #0,r4
+;       do      #64,<_block1
+;       rep     #256
+;       move    A,X:(r0)+ B,Y:(r4)+
+;_block1        ; Zero (32768-512) Program words
+;       clr     A #512,r0
+;       do      #126,<_block2
+;       rep     #256
+;       move    A,P:(r0)+
+;_block2
+
+        ; Copy DSP program control
+        move    #real,r0
+        move    #upload,r1
+        do      #upload_end-upload,_copy
+        movem    P:(r0)+,x0
+        movem    x0,P:(r1)+
+_copy   movep   #4,X:<<M_HCR
+        movep   #$c00,X:<<M_IPR
+        and     #<$fe,mr
+        jmp     upload
+
+real
+        org     P:$7ea9
+upload
+        movep   #1,X:<<M_PBC
+        movep   #0,X:<<M_BCR
+
+next    jclr    #0,X:<<M_HSR,*
+        movep   X:<<M_HRX,A
+        move    #>3,x0
+        cmp     x0,A #>1,x0
+        jeq     <$0
+_get_address
+        jclr    #0,X:<<M_HSR,_get_address
+        movep   X:<<M_HRX,r0
+_get_length
+        jclr    #0,X:<<M_HSR,_get_length
+        movep   X:<<M_HRX,y0
+        cmp     x0,A #>2,x0
+        jeq     load_X
+        cmp     x0,A
+        jeq     load_Y
+
+load_P  do      y0,_load_P
+        jclr    #0,X:<<M_HSR,*
+        movep   X:<<M_HRX,P:(r0)+
+_load_P jmp     next
+load_X  do      y0,_load_X
+        jclr    #0,X:<<M_HSR,*
+        movep   X:<<M_HRX,X:(r0)+
+_load_X jmp     next
+load_Y  do      y0,_load_Y
+        jclr    #0,X:<<M_HSR,*
+        movep   X:<<M_HRX,Y:(r0)+
+_load_Y jmp     next
+
+upload_end
+        end
diff --git a/dsp56k/bootstrap.bin b/dsp56k/bootstrap.bin
new file mode 100644
index 0000000..3180ce8
--- /dev/null
+++ b/dsp56k/bootstrap.bin
diff --git a/dsp56k/concat-bootstrap.pl b/dsp56k/concat-bootstrap.pl
new file mode 100644
index 0000000..b6d9003
--- /dev/null
+++ b/dsp56k/concat-bootstrap.pl
@@ -0,0 +1,33 @@
+# Postprocessor for dsp56k bootstrap code.
+#
+# Copyright Ben Hutchings 2011.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+
+use strict;
+use warnings;
+
+my @memory;
+my %symbol;
+
+# Reconstruct memory image and symbol table
+while (<>) {
+    if (/^P ([0-9A-F]{4}) ([0-9A-F]{6})\n/) {
+	$memory[hex($1)] = hex($2);
+    } elsif (/^I ([0-9A-F]{6}) (\w+)\n/) {
+	$symbol{$2} = hex($1);
+    } else {
+	print STDERR "W: did not recognise line $.\n";
+    }
+}
+
+# Concatenate first and second stage.  Second stage is assembled
+# between 'upload' and 'upload_end', but initially loaded at
+# 'real' (end of the first stage).
+for (0 .. ($symbol{real} - 1), $symbol{upload} .. ($symbol{upload_end} - 1)) {
+    my $word = $memory[$_] || 0;
+    print pack('CCC', $word / 65536, ($word / 256) % 256, $word % 256);
+}