diff options
Diffstat (limited to 'src/cmd/compile/internal/ssa/_gen')
4 files changed, 71 insertions, 66 deletions
diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules index aac6873..2a4c59e 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules @@ -1020,10 +1020,6 @@ (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem) (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem) -(MOVLQZX x) && zeroUpper32Bits(x,3) => x -(MOVWQZX x) && zeroUpper48Bits(x,3) => x -(MOVBQZX x) && zeroUpper56Bits(x,3) => x - // replace load from same location as preceding store with zero/sign extension (or copy in case of full width) (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBQZX x) (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWQZX x) diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules index a1e63d6..1dd8045 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules @@ -6,3 +6,8 @@ (SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)
(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)
(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)
+
+// See comments in ARM64latelower.rules for why these are here.
+(MOVLQZX x) && zeroUpper32Bits(x,3) => x
+(MOVWQZX x) && zeroUpper48Bits(x,3) => x
+(MOVBQZX x) && zeroUpper56Bits(x,3) => x
diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64.rules b/src/cmd/compile/internal/ssa/_gen/ARM64.rules index c5ee028..18a6586 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64.rules @@ -1054,61 +1054,6 @@ (MOVWUloadidx4 ptr idx (MOVWstorezeroidx4 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) (MOVDloadidx8 ptr idx (MOVDstorezeroidx8 ptr2 idx2 _)) && isSamePtr(ptr, ptr2) && isSamePtr(idx, idx2) => (MOVDconst [0]) -// don't extend after proper load -(MOVBreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHload _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x) -(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x) -(MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x) - -// fold double extensions -(MOVBreg x:(MOVBreg _)) => (MOVDreg x) -(MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHreg x:(MOVBreg _)) => (MOVDreg x) -(MOVHreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHreg x:(MOVHreg _)) => (MOVDreg x) -(MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) -(MOVWreg x:(MOVBreg _)) => (MOVDreg x) -(MOVWreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVWreg x:(MOVHreg _)) => (MOVDreg x) -(MOVWreg x:(MOVWreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) -(MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) - // don't extend before store (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem) (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) @@ -1572,18 +1517,11 @@ (LessThanNoov (InvertFlags x)) => (CSEL0 [OpARM64NotEqual] (GreaterEqualNoov <typ.Bool> x) x) (GreaterEqualNoov (InvertFlags x)) => (CSINC [OpARM64NotEqual] (LessThanNoov <typ.Bool> x) (MOVDconst [0]) x) -// Boolean-generating instructions (NOTE: NOT all boolean Values) always -// zero upper bit of the register; no need to zero-extend -(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => (MOVDreg x) - // Don't bother extending if we're not using the higher bits. (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x -// omit unsign extension -(MOVWUreg x) && zeroUpper32Bits(x, 3) => x - // omit sign extension (MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c]) (MOVHreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffff8000) == 0 => (ANDconst <t> x [c]) diff --git a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules index d0c2099..e50d985 100644 --- a/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules +++ b/src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules @@ -19,3 +19,69 @@ (CMNWconst [c] x) && !isARM64addcon(int64(c)) => (CMNW x (MOVDconst [int64(c)])) (ADDSconstflags [c] x) && !isARM64addcon(c) => (ADDSflags x (MOVDconst [c])) + +// These rules remove unneeded sign/zero extensions. +// They occur in late lower because they rely on the fact +// that their arguments don't get rewritten to a non-extended opcode instead. + +// Boolean-generating instructions (NOTE: NOT all boolean Values) always +// zero upper bit of the register; no need to zero-extend +(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => x + +// omit unsigned extension +(MOVWUreg x) && zeroUpper32Bits(x, 3) => x + +// don't extend after proper load +(MOVBreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHload _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUload _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUload _ _)) => (MOVDreg x) +(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVDreg x) +(MOVHreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWreg x:(MOVWloadidx4 _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUloadidx2 _ _ _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUloadidx4 _ _ _)) => (MOVDreg x) + +// fold double extensions +(MOVBreg x:(MOVBreg _)) => (MOVDreg x) +(MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHreg x:(MOVBreg _)) => (MOVDreg x) +(MOVHreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHreg x:(MOVHreg _)) => (MOVDreg x) +(MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) +(MOVWreg x:(MOVBreg _)) => (MOVDreg x) +(MOVWreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVWreg x:(MOVHreg _)) => (MOVDreg x) +(MOVWreg x:(MOVWreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) +(MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) |