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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
commitace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch)
treeb2d64bc10158fdd5497876388cd68142ca374ed3 /Documentation/devicetree/bindings/power/reset
parentInitial commit. (diff)
downloadlinux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz
linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/power/reset')
-rw-r--r--Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml82
-rw-r--r--Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml114
-rw-r--r--Documentation/devicetree/bindings/power/reset/axxia-reset.txt20
-rw-r--r--Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml31
-rw-r--r--Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt17
-rw-r--r--Documentation/devicetree/bindings/power/reset/gpio-poweroff.yaml59
-rw-r--r--Documentation/devicetree/bindings/power/reset/gpio-restart.yaml79
-rw-r--r--Documentation/devicetree/bindings/power/reset/keystone-reset.txt67
-rw-r--r--Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt33
-rw-r--r--Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt20
-rw-r--r--Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml52
-rw-r--r--Documentation/devicetree/bindings/power/reset/ocelot-reset.txt19
-rw-r--r--Documentation/devicetree/bindings/power/reset/qcom,pon.yaml144
-rw-r--r--Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml35
-rw-r--r--Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt15
-rw-r--r--Documentation/devicetree/bindings/power/reset/reboot-mode.yaml49
-rw-r--r--Documentation/devicetree/bindings/power/reset/regulator-poweroff.yaml37
-rw-r--r--Documentation/devicetree/bindings/power/reset/restart-handler.yaml30
-rw-r--r--Documentation/devicetree/bindings/power/reset/restart-poweroff.txt8
-rw-r--r--Documentation/devicetree/bindings/power/reset/st-reset.txt11
-rw-r--r--Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml62
-rw-r--r--Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml55
-rw-r--r--Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml71
-rw-r--r--Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml83
24 files changed, 1193 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml
new file mode 100644
index 0000000000..f559a2cfd8
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/atmel,at91sam9260-shdwc.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/atmel,at91sam9260-shdwc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 SHDWC Shutdown Controller
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+description: |
+ Microchip AT91 SHDWC shutdown controller controls the power supplies VDDIO
+ and VDDCORE and the wake-up detection on debounced input lines.
+
+properties:
+ compatible:
+ enum:
+ - atmel,at91sam9260-shdwc
+ - atmel,at91sam9rl-shdwc
+ - atmel,at91sam9x5-shdwc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ atmel,wakeup-mode:
+ description: operation mode of the wakeup mode
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [ none, high, low, any ]
+
+ atmel,wakeup-counter:
+ description: counter on wake-up 0
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+
+ atmel,wakeup-rtt-timer:
+ description: enable real-time timer wake-up
+ type: boolean
+
+ atmel,wakeup-rtc-timer:
+ description: enable real-time clock wake-up
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,at91sam9x5-shdwc
+ then:
+ properties:
+ atmel,wakeup-rtt-timer: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,at91sam9260-shdwc
+ then:
+ properties:
+ atmel,wakeup-rtc-timer: false
+
+additionalProperties: false
+
+examples:
+ - |
+ shdwc: poweroff@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
new file mode 100644
index 0000000000..8c58e12cdb
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/atmel,sama5d2-shdwc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 SAMA5D2 SHDWC Shutdown Controller
+
+maintainers:
+ - Claudiu Beznea <claudiu.beznea@microchip.com>
+
+description: |
+ Microchip AT91 SHDWC shutdown controller controls the power supplies VDDIO
+ and VDDCORE and the wake-up detection on debounced input lines.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: microchip,sama7g5-shdwc
+ - const: syscon
+ - enum:
+ - atmel,sama5d2-shdwc
+ - microchip,sam9x60-shdwc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ debounce-delay-us:
+ description:
+ Minimum wake-up inputs debouncer period in microseconds. It is usually a
+ board-related property.
+
+ atmel,wakeup-rtc-timer:
+ description: enable real-time clock wake-up
+ type: boolean
+
+ atmel,wakeup-rtt-timer:
+ description: enable real-time timer wake-up
+ type: boolean
+
+patternProperties:
+ "^input@[0-15]$":
+ description:
+ Wake-up input nodes. These are usually described in the "board" part of
+ the Device Tree. Note also that input 0 is linked to the wake-up pin and
+ is frequently used.
+ type: object
+ properties:
+ reg:
+ description: contains the wake-up input index
+ minimum: 0
+ maximum: 15
+
+ atmel,wakeup-active-high:
+ description:
+ The corresponding wake-up input described by the child forces the
+ wake-up of the core power supply on a high level. The default is to
+ be active low.
+ type: boolean
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,sama5d2-shdwc
+ then:
+ properties:
+ atmel,wakeup-rtt-timer: false
+
+additionalProperties: false
+
+examples:
+ - |
+ shdwc: poweroff@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ debounce-delay-us = <976>;
+
+ input@0 {
+ reg = <0>;
+ };
+
+ input@1 {
+ reg = <1>;
+ atmel,wakeup-active-high;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/power/reset/axxia-reset.txt b/Documentation/devicetree/bindings/power/reset/axxia-reset.txt
new file mode 100644
index 0000000000..47e720d249
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/axxia-reset.txt
@@ -0,0 +1,20 @@
+Axxia Restart Driver
+
+This driver can do reset of the Axxia SoC. It uses the registers in the syscon
+block to initiate a chip reset.
+
+Required Properties:
+ -compatible: "lsi,axm55xx-reset"
+ -syscon: phandle to the syscon node.
+
+Example:
+
+ syscon: syscon@2010030000 {
+ compatible = "lsi,axxia-syscon", "syscon";
+ reg = <0x20 0x10030000 0 0x2000>;
+ };
+
+ reset: reset@2010031000 {
+ compatible = "lsi,axm55xx-reset";
+ syscon = <&syscon>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml
new file mode 100644
index 0000000000..3e28a59d71
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/brcm,bcm21664-resetmgr.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/brcm,bcm21664-resetmgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Kona family reset manager
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,bcm21664-resetmgr
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@35001f00 {
+ compatible = "brcm,bcm21664-resetmgr";
+ reg = <0x35001f00 0x24>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt
new file mode 100644
index 0000000000..7fec3e1002
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/gemini-poweroff.txt
@@ -0,0 +1,17 @@
+* Device-Tree bindings for Cortina Systems Gemini Poweroff
+
+This is a special IP block in the Cortina Gemini SoC that only
+deals with different ways to power the system down.
+
+Required properties:
+- compatible: should be "cortina,gemini-power-controller"
+- reg: should contain the physical memory base and size
+- interrupts: should contain the power management interrupt
+
+Example:
+
+power-controller@4b000000 {
+ compatible = "cortina,gemini-power-controller";
+ reg = <0x4b000000 0x100>;
+ interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
+};
diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.yaml
new file mode 100644
index 0000000000..b54ec003a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/gpio-poweroff.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO controlled power off
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: >
+ System power off support via a GPIO line. When a shutdown is
+ executed the operating system is expected to switch the GPIO
+ from inactive to active. After a delay (active-delay-ms) it
+ is expected to be switched back to inactive. After another
+ delay (inactive-delay-ms) it is configured as active again.
+ Finally the operating system assumes the power off failed if
+ the system is still running after waiting some time (timeout-ms).
+
+properties:
+ compatible:
+ const: gpio-poweroff
+
+ gpios:
+ maxItems: 1
+
+ input:
+ type: boolean
+ description: >
+ Initially configure the GPIO line as an input. Only reconfigure
+ it to an output when the power-off sequence is initiated. If this optional
+ property is not specified, the GPIO is initialized as an output in its inactive state.
+
+ active-delay-ms:
+ default: 100
+ description: Delay to wait after driving gpio active
+
+ inactive-delay-ms:
+ default: 100
+ description: Delay to wait after driving gpio inactive
+
+ timeout-ms:
+ default: 3000
+ description: Time to wait before assuming the power off sequence failed.
+
+required:
+ - compatible
+ - gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 4 0>;
+ timeout-ms = <3000>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/gpio-restart.yaml b/Documentation/devicetree/bindings/power/reset/gpio-restart.yaml
new file mode 100644
index 0000000000..53535de0d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/gpio-restart.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO controlled reset
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: >
+ Drive a GPIO line that can be used to restart the system from a restart handler.
+
+ This binding supports level and edge triggered reset. At driver load time, the driver will
+ request the given gpio line and install a restart handler. If the optional properties
+ 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
+ not driven until the restart is initiated.
+
+ When the system is restarted, the restart handler will be invoked in priority order. The GPIO
+ is configured as an output, and driven active, triggering a level triggered reset condition.
+ This will also cause an inactive->active edge condition, triggering positive edge triggered
+ reset. After a delay specified by active-delay, the GPIO is set to inactive, thus causing an
+ active->inactive edge, triggering negative edge triggered reset. After a delay specified by
+ inactive-delay, the GPIO is driven active again. After a delay specified by wait-delay, the
+ restart handler completes allowing other restart handlers to be attempted.
+
+allOf:
+ - $ref: restart-handler.yaml#
+
+properties:
+ compatible:
+ const: gpio-restart
+
+ gpios:
+ description: The GPIO to set high/low, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be low to reset the board
+ set it to "Active Low", otherwise set GPIO to "Active High".
+
+ open-source:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Treat the GPIO as being open source and defer driving it to when the restart is
+ initiated. If this optional property is not specified, the GPIO is initialized as an output
+ in its inactive state.
+
+ priority:
+ default: 129
+
+ active-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Delay (default 100) to wait after driving gpio active [ms]
+ default: 100
+
+ inactive-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Delay (default 100) to wait after driving gpio inactive [ms]
+ default: 100
+
+ wait-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Delay (default 3000) to wait after completing restart sequence [ms]
+ default: 100
+
+additionalProperties: false
+
+required:
+ - compatible
+ - gpios
+
+examples:
+ - |
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 4 0>;
+ priority = <128>;
+ active-delay = <100>;
+ inactive-delay = <100>;
+ wait-delay = <3000>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt
new file mode 100644
index 0000000000..c5c03789ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt
@@ -0,0 +1,67 @@
+* Device tree bindings for Texas Instruments keystone reset
+
+This node is intended to allow SoC reset in case of software reset
+of selected watchdogs.
+
+The Keystone SoCs can contain up to 4 watchdog timers to reset
+SoC. Each watchdog timer event input is connected to the Reset Mux
+block. The Reset Mux block can be configured to cause reset or not.
+
+Additionally soft or hard reset can be configured.
+
+Required properties:
+
+- compatible: ti,keystone-reset
+
+- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
+ access pll controller registers and the offset to use
+ reset control registers.
+
+- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
+ access device state control registers and the offset
+ in order to use mux block registers for all watchdogs.
+
+Optional properties:
+
+- ti,soft-reset: Boolean option indicating soft reset.
+ By default hard reset is used.
+
+- ti,wdt-list: WDT list that can cause SoC reset. It's not related
+ to WDT driver, it's just needed to enable a SoC related
+ reset that's triggered by one of WDTs. The list is
+ in format: <0>, <2>; It can be in random order and
+ begins from 0 to 3, as keystone can contain up to 4 SoC
+ reset watchdogs and can be in random order.
+
+Example 1:
+Setup keystone reset so that in case software reset or
+WDT0 is triggered it issues hard reset for SoC.
+
+pllctrl: pll-controller@2310000 {
+ compatible = "ti,keystone-pllctrl", "syscon";
+ reg = <0x02310000 0x200>;
+};
+
+devctrl: device-state-control@2620000 {
+ compatible = "ti,keystone-devctrl", "syscon";
+ reg = <0x02620000 0x1000>;
+};
+
+rstctrl: reset-controller {
+ compatible = "ti,keystone-reset";
+ ti,syscon-pll = <&pllctrl 0xe4>;
+ ti,syscon-dev = <&devctrl 0x328>;
+ ti,wdt-list = <0>;
+};
+
+Example 2:
+Setup keystone reset so that in case of software reset or
+WDT0 or WDT2 is triggered it issues soft reset for SoC.
+
+rstctrl: reset-controller {
+ compatible = "ti,keystone-reset";
+ ti,syscon-pll = <&pllctrl 0xe4>;
+ ti,syscon-dev = <&devctrl 0x328>;
+ ti,wdt-list = <0>, <2>;
+ ti,soft-reset;
+};
diff --git a/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt
new file mode 100644
index 0000000000..38e54b3fd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt
@@ -0,0 +1,33 @@
+Binding for the LTC2952 PowerPath controller
+
+This chip is used to externally trigger a system shut down. Once the trigger has
+been sent, the chip's watchdog has to be reset to gracefully shut down.
+A full powerdown can be triggered via the kill signal.
+
+Required properties:
+
+- compatible: Must contain: "lltc,ltc2952"
+- watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's watchdog line
+- kill-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's kill line
+
+Optional properties:
+- trigger-gpios: phandle + gpio-specifier for the GPIO connected to the
+ chip's trigger line. If this property is not set, the
+ trigger function is ignored and the chip is kept alive
+ until an explicit kill signal is received
+- trigger-delay-ms The number of milliseconds to wait after trigger line
+ assertion before executing shut down procedure.
+ The default is 2500ms.
+
+Example:
+
+ltc2952 {
+ compatible = "lltc,ltc2952";
+
+ trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ trigger-delay-ms = <2000>;
+ watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+};
diff --git a/Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt b/Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt
new file mode 100644
index 0000000000..933f0c48e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/mt6323-poweroff.txt
@@ -0,0 +1,20 @@
+Device Tree Bindings for Power Controller on MediaTek PMIC
+
+The power controller which could be found on PMIC is responsible for externally
+powering off or on the remote MediaTek SoC through the circuit BBPU.
+
+Required properties:
+- compatible: Should be one of follows
+ "mediatek,mt6323-pwrc": for MT6323 PMIC
+
+Example:
+
+ pmic {
+ compatible = "mediatek,mt6323";
+
+ ...
+
+ power-controller {
+ compatible = "mediatek,mt6323-pwrc";
+ };
+ }
diff --git a/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml
new file mode 100644
index 0000000000..14a262bcbf
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/nvmem-reboot-mode.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/nvmem-reboot-mode.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic NVMEM reboot mode
+
+maintainers:
+ - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+
+description:
+ This driver gets the reboot mode magic value from the reboot-mode driver
+ and stores it in the NVMEM cell named "reboot-mode". The bootloader can
+ then read it and take different action according to the value.
+
+properties:
+ compatible:
+ const: nvmem-reboot-mode
+
+ nvmem-cells:
+ description:
+ A phandle pointing to the nvmem-cells node where the vendor-specific
+ magic value representing the reboot mode is stored.
+ maxItems: 1
+
+ nvmem-cell-names:
+ items:
+ - const: reboot-mode
+
+patternProperties:
+ "^mode-.+":
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Vendor-specific mode value written to the mode register
+
+required:
+ - compatible
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+examples:
+ - |
+ reboot-mode {
+ compatible = "nvmem-reboot-mode";
+ nvmem-cells = <&reboot_reason>;
+ nvmem-cell-names = "reboot-mode";
+ mode-recovery = <0x01>;
+ mode-bootloader = <0x02>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 0000000000..c5de7b555f
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,19 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
+
+Required Properties:
+
+ - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
+ "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
+
+Example:
+ reset@1070008 {
+ compatible = "mscc,ocelot-chip-reset";
+ reg = <0x1070008 0x4>;
+ };
+
diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
new file mode 100644
index 0000000000..5e460128b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/qcom,pon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PON Device
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description: |
+ The Power On device for Qualcomm PM8xxx is MFD supporting pwrkey
+ and resin along with the Android reboot-mode.
+
+ This DT node has pwrkey and resin as sub nodes.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pm8916-pon
+ - qcom,pm8941-pon
+ - qcom,pms405-pon
+ - qcom,pm8998-pon
+ - qcom,pmk8350-pon
+
+ reg:
+ description: |
+ Specifies the SPMI base address for the PON (power-on) peripheral. For
+ PMICs that have the PON peripheral (GEN3) split into PON_HLOS and PON_PBS
+ (e.g. PMK8350), this can hold addresses of both PON_HLOS and PON_PBS
+ peripherals. In that case, the PON_PBS address needs to be specified to
+ facilitate software debouncing on some PMIC.
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
+ pwrkey:
+ type: object
+ $ref: /schemas/input/qcom,pm8941-pwrkey.yaml#
+
+ resin:
+ type: object
+ $ref: /schemas/input/qcom,pm8941-pwrkey.yaml#
+
+ watchdog:
+ type: object
+ $ref: /schemas/watchdog/qcom,pm8916-wdt.yaml
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pm8916-pon
+ - qcom,pms405-pon
+ - qcom,pm8998-pon
+ then:
+ allOf:
+ - $ref: reboot-mode.yaml#
+
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: pon
+
+ # Special case for pm8941, which doesn't store reset mode
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,pm8941-pon
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: pon
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,pmk8350-pon
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 2
+ reg-names:
+ minItems: 1
+ items:
+ - const: hlos
+ - const: pbs
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include <dt-bindings/spmi/spmi.h>
+ spmi_bus: spmi@c440000 {
+ reg = <0x0c440000 0x1100>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ pmk8350: pmic@0 {
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmk8350_pon: pon_hlos@1300 {
+ reg = <0x1300>;
+ compatible = "qcom,pm8998-pon";
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = < 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH >;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+ };
+
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml
new file mode 100644
index 0000000000..527962d54a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/qcom,pshold.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/qcom,pshold.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SoC restart and power off
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ A power supply hold (ps-hold) bit is set to power the Qualcomm chipsets.
+ Clearing that bit allows us to restart/power off. The difference between
+ power off and restart is determined by unique power manager IC settings.
+
+properties:
+ compatible:
+ const: qcom,pshold
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@fc4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0xfc4ab000 0x4>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt b/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt
new file mode 100644
index 0000000000..c363d71731
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/qnap-poweroff.txt
@@ -0,0 +1,15 @@
+* QNAP Power Off
+
+QNAP NAS devices have a microcontroller controlling the main power
+supply. This microcontroller is connected to UART1 of the Kirkwood and
+Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
+microcontroller to turn the power off.
+
+Synology NAS devices use a similar scheme, but a different baud rate,
+9600, and a different character, '1'.
+
+Required Properties:
+- compatible: Should be "qnap,power-off" or "synology,power-off"
+
+- reg: Address and length of the register set for UART1
+- clocks: tclk clock
diff --git a/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml
new file mode 100644
index 0000000000..ad0a0b95ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/reboot-mode.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/reboot-mode.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic reboot mode core map
+
+maintainers:
+ - Andy Yan <andy.yan@rock-chips.com>
+
+description: |
+ This driver get reboot mode arguments and call the write
+ interface to store the magic value in special register
+ or ram. Then the bootloader can read it and take different
+ action according to the argument stored.
+
+ All mode properties are vendor specific, it is a indication to tell
+ the bootloader what to do when the system reboots, and should be named
+ as mode-xxx = <magic> (xxx is mode name, magic should be a non-zero value).
+
+ For example, modes common Android platform are:
+ - normal: Normal reboot mode, system reboot with command "reboot".
+ - recovery: Android Recovery mode, it is a mode to format the device or update a new image.
+ - bootloader: Android fastboot mode, it's a mode to re-flash partitions on the Android based device.
+ - loader: A bootloader mode, it's a mode used to download image on Rockchip platform,
+ usually used in development.
+
+properties:
+ mode-normal:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Default value to set on a reboot if no command was provided.
+
+patternProperties:
+ "^mode-.*$":
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+additionalProperties: true
+
+examples:
+ - |
+ reboot-mode {
+ mode-normal = <0>;
+ mode-recovery = <1>;
+ mode-bootloader = <2>;
+ mode-loader = <3>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/regulator-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/regulator-poweroff.yaml
new file mode 100644
index 0000000000..e9417557cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/regulator-poweroff.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/regulator-poweroff.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Force-disable power regulator to turn the power off.
+
+maintainers:
+ - Michael Klein <michael@fossekall.de>
+
+description: |
+ When the power-off handler is called, a power regulator is disabled by
+ calling regulator_force_disable(). If the power is still on and the
+ CPU still running after a 3000ms delay, a warning is emitted.
+
+properties:
+ compatible:
+ const: regulator-poweroff
+
+ cpu-supply:
+ description:
+ regulator to disable on power-down
+
+required:
+ - compatible
+ - cpu-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ regulator-poweroff {
+ compatible = "regulator-poweroff";
+ cpu-supply = <&reg_vcc1v2>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/restart-handler.yaml b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml
new file mode 100644
index 0000000000..965a834a3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/restart-handler.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Restart and shutdown handler Common Properties
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description:
+ Restart and shutdown handler device is responsible for powering off the
+ system, e.g. my cutting off the power. System might have several restart
+ handlers, which usually are tried from most precise to last resort.
+
+properties:
+ priority:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ A priority ranging from 0 to 255 according to the following guidelines::
+ 0:: Restart handler of last resort, with limited restart capabilities.
+ 128:: Typical, default restart handler; use if no other restart handler
+ is expected to be available, and/or if restart functionality is
+ sufficient to restart the entire system.
+ 255:: Highest priority restart handler, will preempt all other restart handlers.
+ minimum: 0
+ maximum: 255
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt b/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt
new file mode 100644
index 0000000000..5776e684af
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/restart-poweroff.txt
@@ -0,0 +1,8 @@
+* Restart Power Off
+
+Buffalo Linkstation LS-XHL and LS-CHLv2, and other devices power off
+by restarting and letting u-boot keep hold of the machine until the
+user presses a button.
+
+Required Properties:
+- compatible: Should be "restart-poweroff"
diff --git a/Documentation/devicetree/bindings/power/reset/st-reset.txt b/Documentation/devicetree/bindings/power/reset/st-reset.txt
new file mode 100644
index 0000000000..b63948737d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/st-reset.txt
@@ -0,0 +1,11 @@
+*Device-Tree bindings for ST SW reset functionality
+
+Required properties:
+- compatible: should be "stih407-restart".
+- st,syscfg: should be a phandle of the syscfg node.
+
+Example node:
+ restart {
+ compatible = "st,stih407-restart";
+ st,syscfg = <&syscfg_sbc_reg>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
new file mode 100644
index 0000000000..3412fe7e1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/syscon-poweroff.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic SYSCON mapped register poweroff driver
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |+
+ This is a generic poweroff driver using syscon to map the poweroff register.
+ The poweroff is generally performed with a write to the poweroff register
+ defined by the register map pointed by syscon reference plus the offset
+ with the value and mask defined in the poweroff node.
+ Default will be little endian mode, 32 bit access only.
+
+properties:
+ compatible:
+ const: syscon-poweroff
+
+ mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Update only the register bits defined by the mask (32 bit).
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the poweroff register (in bytes).
+
+ regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the register map node.
+
+ value:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The poweroff value written to the poweroff register (32 bit access).
+
+required:
+ - compatible
+ - regmap
+ - offset
+
+additionalProperties: false
+
+allOf:
+ - if:
+ not:
+ required:
+ - mask
+ then:
+ required:
+ - value
+
+examples:
+ - |
+ poweroff {
+ compatible = "syscon-poweroff";
+ regmap = <&regmapnode>;
+ offset = <0x0>;
+ mask = <0x7a>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml
new file mode 100644
index 0000000000..9b1ffceefe
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot-mode.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/syscon-reboot-mode.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic SYSCON reboot mode driver
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ This driver gets reboot mode magic value from reboot-mode driver
+ and stores it in a SYSCON mapped register. Then the bootloader
+ can read it and take different action according to the magic
+ value stored. The SYSCON mapped register is retrieved from the
+ parental dt-node plus the offset. So the SYSCON reboot-mode node
+ should be represented as a sub-node of a "syscon", "simple-mfd" node.
+
+properties:
+ compatible:
+ const: syscon-reboot-mode
+
+ mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Update only the register bits defined by the mask (32 bit)
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the mode register (in bytes)
+
+patternProperties:
+ "^mode-.+":
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Vendor-specific mode value written to the mode register
+
+additionalProperties: false
+
+required:
+ - compatible
+ - offset
+
+examples:
+ - |
+ #include <dt-bindings/soc/rockchip,boot-mode.h>
+
+ reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x40>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-bootloader = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
new file mode 100644
index 0000000000..75061124d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic SYSCON mapped register reset driver
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |+
+ This is a generic reset driver using syscon to map the reset register.
+ The reset is generally performed with a write to the reset register
+ defined by the SYSCON register map base plus the offset with the value and
+ mask defined in the reboot node. Default will be little endian mode, 32 bit
+ access only. The SYSCON registers map is normally retrieved from the
+ parental dt-node. So the SYSCON reboot node should be represented as a
+ sub-node of a "syscon", "simple-mfd" node. Though the regmap property
+ pointing to the system controller node is also supported.
+
+properties:
+ compatible:
+ const: syscon-reboot
+
+ mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Update only the register bits defined by the mask (32 bit).
+
+ offset:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Offset in the register map for the reboot register (in bytes).
+
+ regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ deprecated: true
+ description: |
+ Phandle to the register map node. This property is deprecated in favor of
+ the syscon-reboot node been a child of a system controller node.
+
+ value:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The reset value written to the reboot register (32 bit access).
+
+ priority:
+ default: 192
+
+required:
+ - compatible
+ - offset
+
+additionalProperties: false
+
+allOf:
+ - $ref: restart-handler.yaml#
+ - if:
+ not:
+ required:
+ - mask
+ then:
+ required:
+ - value
+
+examples:
+ - |
+ reboot {
+ compatible = "syscon-reboot";
+ regmap = <&regmapnode>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
new file mode 100644
index 0000000000..45792e2169
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq MPSoC Power Management
+
+maintainers:
+ - Michal Simek <michal.simek@amd.com>
+
+description: |
+ The zynqmp-power node describes the power management configurations.
+ It will control remote suspend/shutdown interfaces.
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-power
+
+ interrupts:
+ maxItems: 1
+
+ mboxes:
+ description: |
+ Standard property to specify a Mailbox. Each value of
+ the mboxes property should contain a phandle to the
+ mailbox controller device node and an args specifier
+ that will be the phandle to the intended sub-mailbox
+ child node to be used for communication. See
+ Documentation/devicetree/bindings/mailbox/mailbox.txt
+ for more details about the generic mailbox controller
+ and client driver bindings. Also see
+ Documentation/devicetree/bindings/mailbox/ \
+ xlnx,zynqmp-ipi-mailbox.txt for typical controller that
+ is used to communicate with this System controllers.
+ items:
+ - description: tx channel
+ - description: rx channel
+
+ mbox-names:
+ description:
+ Name given to channels seen in the 'mboxes' property.
+ items:
+ - const: tx
+ - const: rx
+
+required:
+ - compatible
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |+
+
+ // Example with interrupt method:
+
+ firmware {
+ zynqmp-firmware {
+ zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ };
+ };
+
+ - |+
+
+ // Example with IPI mailbox method:
+
+ firmware {
+ zynqmp-firmware {
+ zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ mboxes = <&ipi_mailbox_pmu1 0>,
+ <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+...