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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:40:19 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:40:19 +0000 |
| commit | 9f0fc191371843c4fc000a226b0a26b6c059aacd (patch) | |
| tree | 35f8be3ef04506ac891ad001e8c41e535ae8d01d /Documentation/i2c | |
| parent | Releasing progress-linux version 6.6.15-2~progress7.99u1. (diff) | |
| download | linux-9f0fc191371843c4fc000a226b0a26b6c059aacd.tar.xz linux-9f0fc191371843c4fc000a226b0a26b6c059aacd.zip | |
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/i2c')
| -rw-r--r-- | Documentation/i2c/fault-codes.rst | 4 | ||||
| -rw-r--r-- | Documentation/i2c/i2c-address-translators.rst | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/i2c/fault-codes.rst b/Documentation/i2c/fault-codes.rst index 80b14e718b..b0864d1268 100644 --- a/Documentation/i2c/fault-codes.rst +++ b/Documentation/i2c/fault-codes.rst @@ -39,6 +39,10 @@ Also, codes returned by adapter probe methods follow rules which are specific to their host bus (such as PCI, or the platform bus). +EAFNOSUPPORT + Returned by I2C adapters not supporting 10 bit addresses when + they are requested to use such an address. + EAGAIN Returned by I2C adapters when they lose arbitration in master transmit mode: some other master was transmitting different diff --git a/Documentation/i2c/i2c-address-translators.rst b/Documentation/i2c/i2c-address-translators.rst index b22ce9f41e..6845c114e4 100644 --- a/Documentation/i2c/i2c-address-translators.rst +++ b/Documentation/i2c/i2c-address-translators.rst @@ -71,7 +71,7 @@ Transaction: - Physical I2C transaction on bus A, slave address 0x20 - ATR chip detects transaction on address 0x20, finds it in table, propagates transaction on bus B with address translated to 0x10, - keeps clock streched on bus A waiting for reply + keeps clock stretched on bus A waiting for reply - Slave X chip (on bus B) detects transaction at its own physical address 0x10 and replies normally - ATR chip stops clock stretching and forwards reply on bus A, |