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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-19 21:00:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-06-19 21:00:51 +0000 |
| commit | 6d03a247468059b0e59c821ef39e6762d4d6fc30 (patch) | |
| tree | 17b9c00de2c62e68c965c742cdbc206f77a375da /arch/arm/boot/dts/renesas/r8a73a4.dtsi | |
| parent | Releasing progress-linux version 6.8.12-1~progress7.99u1. (diff) | |
| download | linux-6d03a247468059b0e59c821ef39e6762d4d6fc30.tar.xz linux-6d03a247468059b0e59c821ef39e6762d4d6fc30.zip | |
Merging upstream version 6.9.2.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm/boot/dts/renesas/r8a73a4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/renesas/r8a73a4.dtsi | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index d1f4cbd099..ac654ff45d 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -624,6 +624,13 @@ clock-div = <2>; clock-mult = <1>; }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&main_div2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; @@ -689,9 +696,8 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < @@ -705,7 +711,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 |