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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-11 08:27:49 +0000 |
| commit | ace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch) | |
| tree | b2d64bc10158fdd5497876388cd68142ca374ed3 /arch/arm64/boot/dts/broadcom | |
| parent | Initial commit. (diff) | |
| download | linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip | |
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/broadcom')
47 files changed, 5558 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile new file mode 100644 index 0000000000..8b4591ddd2 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Enables support for device-tree overlays +DTC_FLAGS := -@ + +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-cm4-io.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb + +subdir-y += bcmbca +subdir-y += northstar2 +subdir-y += stingray diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts new file mode 100644 index 0000000000..c7280bdefa --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts new file mode 100644 index 0000000000..d9d2852b79 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2711-rpi-400.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts new file mode 100644 index 0000000000..8810322aa6 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2711-rpi-cm4-io.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts new file mode 100644 index 0000000000..17d778a7e0 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-a-plus.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2837-rpi-3-a-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts new file mode 100644 index 0000000000..0cf6240b6b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b-plus.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2837-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts new file mode 100644 index 0000000000..f429468fd8 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2837-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts new file mode 100644 index 0000000000..3fa21bd16b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2837-rpi-cm3-io3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 0000000000..363381a0cf --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/broadcom/bcm2837-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile new file mode 100644 index 0000000000..27741b71ba --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm4906-netgear-r8000p.dtb \ + bcm4906-tplink-archer-c2300-v1.dtb \ + bcm4908-asus-gt-ac5300.dtb \ + bcm4908-netgear-raxe500.dtb \ + bcm94908.dtb \ + bcm4912-asus-gt-ax6000.dtb \ + bcm94912.dtb \ + bcm963158.dtb \ + bcm96858.dtb \ + bcm963146.dtb \ + bcm96856.dtb \ + bcm96813.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts new file mode 100644 index 0000000000..78204d71ec --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +#include "bcm4906.dtsi" + +/ { + compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; + model = "Netgear R8000P"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power-white { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + }; + + led-power-amber { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + }; + + led-wps { + function = LED_FUNCTION_WPS; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + + led-2ghz { + function = "2ghz"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + led-5ghz-1 { + function = "5ghz-1"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-5ghz-2 { + function = "5ghz-2"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + function = "usb2"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb3 { + function = "usb3"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; + linux,default-trigger = "usbport"; + }; + + led-wifi { + function = "wifi"; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 56 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&enet { + nvmem-cells = <&base_mac_addr>; + nvmem-cell-names = "mac-address"; +}; + +&usb_phy { + brcm,ioc = <1>; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@7 { + reg = <7>; + phy-mode = "internal"; + phy-handle = <&phy12>; + label = "wan"; + }; +}; + +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "nvmem-cells"; + label = "cferom"; + reg = <0x0 0x100000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x100000>; + + base_mac_addr: mac@106a0 { + reg = <0x106a0 0x6>; + }; + }; + + partition@100000 { + compatible = "brcm,bcm4908-firmware"; + label = "firmware"; + reg = <0x100000 0x4400000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts new file mode 100644 index 0000000000..fcf092c81b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +#include "bcm4906.dtsi" + +/ { + compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; + model = "TP-Link Archer C2300 V1"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led-2ghz { + function = "2ghz"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + function = "5ghz"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + + led-wan-amber { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_AMBER>; + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + }; + + led-wan-blue { + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + + led-lan { + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + led-wps { + function = LED_FUNCTION_WPS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + function = "usb2"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb3 { + function = "usb3"; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; + linux,default-trigger = "usbport"; + }; + + led-brightness { + function = LED_FUNCTION_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + key-brightness { + label = "LEDs"; + linux,code = <KEY_BRIGHTNESS_ZERO>; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + + key-wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + + key-wifi { + label = "WiFi"; + linux,code = <KEY_RFKILL>; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + key-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&usb_phy { + brcm,ioc = <1>; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@7 { + reg = <7>; + phy-mode = "internal"; + phy-handle = <&phy12>; + label = "wan"; + }; +}; + +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "brcm,bcm4908-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "cferom"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x100000 0x3900000>; + }; + + partition@5800000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x3a00000 0x3900000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi new file mode 100644 index 0000000000..d084c33d5c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "bcm4908.dtsi" + +/ { + cpus { + /delete-node/ cpu@2; + + /delete-node/ cpu@3; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts new file mode 100644 index 0000000000..d94a53d683 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +#include "bcm4908.dtsi" + +/ { + compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca"; + model = "Asus GT-AC5300"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + key-wifi { + label = "WiFi"; + linux,code = <KEY_RFKILL>; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + key-wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + key-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + key-brightness { + label = "LEDs"; + linux,code = <KEY_BRIGHTNESS_ZERO>; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&enet { + nvmem-cells = <&base_mac_addr>; + nvmem-cell-names = "mac-address"; +}; + +&usb_phy { + brcm,ioc = <1>; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan2"; + }; + + port@1 { + label = "lan1"; + }; + + port@2 { + label = "lan6"; + }; + + port@3 { + label = "lan5"; + }; + + /* External BCM53134S switch */ + port@7 { + label = "sw"; + reg = <7>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; +}; + +&mdio { + /* lan8 */ + ethernet-phy@0 { + reg = <0>; + }; + + /* lan7 */ + ethernet-phy@1 { + reg = <1>; + }; + + /* lan4 */ + ethernet-phy@2 { + reg = <2>; + }; + + /* lan3 */ + ethernet-phy@3 { + reg = <3>; + }; +}; + +&leds { + led@11 { + reg = <0x11>; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_WHITE>; + default-state = "on"; + active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pins_led_17_a>; + }; + + led@12 { + reg = <0x12>; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_RED>; + active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pins_led_18_a>; + }; + + led@14 { + reg = <0x14>; + function = LED_FUNCTION_WPS; + color = <LED_COLOR_ID_WHITE>; + active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pins_led_20_a>; + }; + + led@15 { + reg = <0x15>; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_WHITE>; + active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pins_led_21_a>; + }; + + led@19 { + reg = <0x19>; + function = LED_FUNCTION_LAN; + color = <LED_COLOR_ID_WHITE>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_led_25_a>; + }; +}; + +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + brcm,nand-has-wp; + + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "brcm,bcm4908-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "nvmem-cells"; + label = "cferom"; + reg = <0x0 0x100000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x100000>; + + base_mac_addr: mac@106a0 { + reg = <0x106a0 0x6>; + }; + }; + + partition@100000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x100000 0x5700000>; + }; + + partition@5800000 { + compatible = "brcm,bcm4908-firmware"; + reg = <0x5800000 0x5700000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts new file mode 100644 index 0000000000..23b96c6632 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "bcm4908.dtsi" + +/ { + compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca"; + model = "Netgear RAXE500"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; +}; + +&ehci { + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@7 { + reg = <7>; + phy-mode = "internal"; + phy-handle = <&phy12>; + label = "wan"; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi new file mode 100644 index 0000000000..2f124b027b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -0,0 +1,639 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/soc/bcm-pmb.h> + +/dts-v1/; + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + clocks { + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x80000000 0x281000>; + + enet: ethernet@2000 { + compatible = "brcm,bcm4908-enet"; + reg = <0x2000 0x1000>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; + }; + + usb_phy: usb-phy@c200 { + compatible = "brcm,bcm4908-usb-phy"; + reg = <0xc200 0x100>; + reg-names = "ctrl"; + power-domains = <&pmb BCM_PMB_HOST_USB>; + dr_mode = "host"; + brcm,has-xhci; + brcm,has-eohci; + #phy-cells = <1>; + status = "disabled"; + }; + + ehci: usb@c300 { + compatible = "generic-ehci"; + reg = <0xc300 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_phy PHY_TYPE_USB2>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + ohci: usb@c400 { + compatible = "generic-ohci"; + reg = <0xc400 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_phy PHY_TYPE_USB2>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + xhci: usb@d000 { + compatible = "generic-xhci"; + reg = <0xd000 0x8c8>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_phy PHY_TYPE_USB3>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + xhci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; + + bus@80000 { + compatible = "simple-bus"; + #size-cells = <1>; + #address-cells = <1>; + ranges = <0 0x80000 0x50000>; + + ethernet-switch@0 { + compatible = "brcm,bcm4908-switch"; + reg = <0x0 0x40000>, + <0x40000 0x110>, + <0x40340 0x30>, + <0x40380 0x30>, + <0x40600 0x34>, + <0x40800 0x208>; + reg-names = "core", "reg", "intrl2_0", + "intrl2_1", "fcb", "acb"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + brcm,num-gphy = <5>; + brcm,num-rgmii-ports = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-mode = "internal"; + phy-handle = <&phy8>; + }; + + port@1 { + reg = <1>; + phy-mode = "internal"; + phy-handle = <&phy9>; + }; + + port@2 { + reg = <2>; + phy-mode = "internal"; + phy-handle = <&phy10>; + }; + + port@3 { + reg = <3>; + phy-mode = "internal"; + phy-handle = <&phy11>; + }; + + port@8 { + reg = <8>; + phy-mode = "internal"; + ethernet = <&enet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + mdio: mdio@405c0 { + compatible = "brcm,unimac-mdio"; + reg = <0x405c0 0x8>; + reg-names = "mdio"; + #size-cells = <0>; + #address-cells = <1>; + + phy8: ethernet-phy@8 { + reg = <8>; + }; + + phy9: ethernet-phy@9 { + reg = <9>; + }; + + phy10: ethernet-phy@a { + reg = <10>; + }; + + phy11: ethernet-phy@b { + reg = <11>; + }; + + phy12: ethernet-phy@c { + reg = <12>; + }; + }; + }; + + procmon: bus@280000 { + compatible = "simple-bus"; + reg = <0x280000 0x1000>; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + pmb: power-controller@2800c0 { + compatible = "brcm,bcm4908-pmb"; + reg = <0x2800c0 0x40>; + #power-domain-cells = <1>; + }; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0xff800000 0x3000>; + + twd: timer-mfd@400 { + compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; + reg = <0x400 0x4c>; + ranges = <0x0 0x400 0x4c>; + + #address-cells = <1>; + #size-cells = <1>; + + timer@0 { + compatible = "brcm,bcm63138-timer"; + reg = <0x0 0x28>; + }; + + watchdog@28 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x28 0x8>; + }; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; + reg = <0x500 0x28>, <0x528 0x28>; + + #gpio-cells = <2>; + gpio-controller; + }; + + pinctrl@560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0x560 0x10>; + + pins_led_0_a: led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + + pins_led_1_a: led_1-a-pins { + function = "led_1"; + groups = "led_1_grp_a"; + }; + + pins_led_2_a: led_2-a-pins { + function = "led_2"; + groups = "led_2_grp_a"; + }; + + pins_led_3_a: led_3-a-pins { + function = "led_3"; + groups = "led_3_grp_a"; + }; + + pins_led_4_a: led_4-a-pins { + function = "led_4"; + groups = "led_4_grp_a"; + }; + + pins_led_5_a: led_5-a-pins { + function = "led_5"; + groups = "led_5_grp_a"; + }; + + pins_led_6_a: led_6-a-pins { + function = "led_6"; + groups = "led_6_grp_a"; + }; + + pins_led_7_a: led_7-a-pins { + function = "led_7"; + groups = "led_7_grp_a"; + }; + + pins_led_8_a: led_8-a-pins { + function = "led_8"; + groups = "led_8_grp_a"; + }; + + pins_led_9_a: led_9-a-pins { + function = "led_9"; + groups = "led_9_grp_a"; + }; + + pins_led_10_a: led_10-a-pins { + function = "led_10"; + groups = "led_10_grp_a"; + }; + + pins_led_11_a: led_11-a-pins { + function = "led_11"; + groups = "led_11_grp_a"; + }; + + pins_led_12_a: led_12-a-pins { + function = "led_12"; + groups = "led_12_grp_a"; + }; + + pins_led_13_a: led_13-a-pins { + function = "led_13"; + groups = "led_13_grp_a"; + }; + + pins_led_14_a: led_14-a-pins { + function = "led_14"; + groups = "led_14_grp_a"; + }; + + pins_led_15_a: led_15-a-pins { + function = "led_15"; + groups = "led_15_grp_a"; + }; + + pins_led_16_a: led_16-a-pins { + function = "led_16"; + groups = "led_16_grp_a"; + }; + + pins_led_17_a: led_17-a-pins { + function = "led_17"; + groups = "led_17_grp_a"; + }; + + pins_led_18_a: led_18-a-pins { + function = "led_18"; + groups = "led_18_grp_a"; + }; + + pins_led_19_a: led_19-a-pins { + function = "led_19"; + groups = "led_19_grp_a"; + }; + + pins_led_20_a: led_20-a-pins { + function = "led_20"; + groups = "led_20_grp_a"; + }; + + pins_led_21_a: led_21-a-pins { + function = "led_21"; + groups = "led_21_grp_a"; + }; + + pins_led_22_a: led_22-a-pins { + function = "led_22"; + groups = "led_22_grp_a"; + }; + + pins_led_23_a: led_23-a-pins { + function = "led_23"; + groups = "led_23_grp_a"; + }; + + pins_led_24_a: led_24-a-pins { + function = "led_24"; + groups = "led_24_grp_a"; + }; + + pins_led_25_a: led_25-a-pins { + function = "led_25"; + groups = "led_25_grp_a"; + }; + + pins_led_26_a: led_26-a-pins { + function = "led_26"; + groups = "led_26_grp_a"; + }; + + pins_led_27_a: led_27-a-pins { + function = "led_27"; + groups = "led_27_grp_a"; + }; + + pins_led_28_a: led_28-a-pins { + function = "led_28"; + groups = "led_28_grp_a"; + }; + + pins_led_29_a: led_29-a-pins { + function = "led_29"; + groups = "led_29_grp_a"; + }; + + pins_led_30_a: led_30-a-pins { + function = "led_30"; + groups = "led_30_grp_a"; + }; + + pins_led_31_a: led_31-a-pins { + function = "led_31"; + groups = "led_31_grp_a"; + }; + + pins_hs_uart: hs_uart-pins { + function = "hs_uart"; + groups = "hs_uart_grp"; + }; + + pins_i2c_a: i2c-a-pins { + function = "i2c"; + groups = "i2c_grp_a"; + }; + + pins_i2c_b: i2c-b-pins { + function = "i2c"; + groups = "i2c_grp_b"; + }; + + pins_i2s: i2s-pins { + function = "i2s"; + groups = "i2s_grp"; + }; + + pins_nand_ctrl: nand_ctrl-pins { + function = "nand_ctrl"; + groups = "nand_ctrl_grp"; + }; + + pins_nand_data: nand_data-pins { + function = "nand_data"; + groups = "nand_data_grp"; + }; + + pins_emmc_ctrl: emmc_ctrl-pins { + function = "emmc_ctrl"; + groups = "emmc_ctrl_grp"; + }; + + pins_usb0_pwr: usb0_pwr-pins { + function = "usb0_pwr"; + groups = "usb0_pwr_grp"; + }; + + pins_usb1_pwr: usb1_pwr-pins { + function = "usb1_pwr"; + groups = "usb1_pwr_grp"; + }; + }; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "okay"; + }; + + leds: leds@800 { + compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; + reg = <0x800 0xdc>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + nand-controller@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "nand_ctlrdy"; + status = "okay"; + + nandcs: nand@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + + i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x58>; + clock-frequency = <97500>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_i2c_a>; + status = "disabled"; + }; + + misc@2600 { + compatible = "brcm,misc", "simple-mfd"; + reg = <0x2600 0xe4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x2600 0xe4>; + + reset-controller@2644 { + compatible = "brcm,bcm4908-misc-pcie-reset"; + reg = <0x44 0x04>; + #reset-cells = <1>; + }; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&twd>; + offset = <0x34>; + mask = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts new file mode 100644 index 0000000000..ed554666e9 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca"; + model = "Asus GT-AX6000"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi new file mode 100644 index 0000000000..d658c81f72 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm4912", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi new file mode 100644 index 0000000000..4f474d4702 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm63146", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi new file mode 100644 index 0000000000..909f254dc4 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm63158", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi new file mode 100644 index 0000000000..685ae32951 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6813", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi new file mode 100644 index 0000000000..820553ce54 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6856", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + periph_clk:periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi new file mode 100644 index 0000000000..0eb93c2982 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6858", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk:periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x62000>; + + twd: timer-mfd@400 { + compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; + reg = <0x400 0x4c>; + ranges = <0x0 0x400 0x4c>; + + #address-cells = <1>; + #size-cells = <1>; + + timer@0 { + compatible = "brcm,bcm63138-timer"; + reg = <0x0 0x28>; + }; + + watchdog@28 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x28 0x8>; + }; + }; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts new file mode 100644 index 0000000000..c4e6e71f63 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4908.dtsi" + +/ { + model = "Broadcom BCM94908 Reference Board"; + compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts new file mode 100644 index 0000000000..e69cd68321 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + model = "Broadcom BCM94912 Reference Board"; + compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts new file mode 100644 index 0000000000..db2c82d6df --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63146.dtsi" + +/ { + model = "Broadcom BCM963146 Reference Board"; + compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts new file mode 100644 index 0000000000..25c12bc635 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + model = "Broadcom BCM963158 Reference Board"; + compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts new file mode 100644 index 0000000000..faba21f031 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6813.dtsi" + +/ { + model = "Broadcom BCM96813 Reference Board"; + compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts new file mode 100644 index 0000000000..9808331eed --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6856.dtsi" + +/ { + model = "Broadcom BCM96856 Reference Board"; + compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts new file mode 100644 index 0000000000..1f561c8e13 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6858.dtsi" + +/ { + model = "Broadcom BCM96858 Reference Board"; + compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/Makefile b/arch/arm64/boot/dts/broadcom/northstar2/Makefile new file mode 100644 index 0000000000..601e1e6312 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb +dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi new file mode 100644 index 0000000000..99009fdf10 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi @@ -0,0 +1,105 @@ +/* + * BSD LICENSE + * + * Copyright (c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/clock/bcm-ns2.h> + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + lcpll_ddr: lcpll_ddr@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: lcpll_ports@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: genpll_scr@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + genpll_sw: genpll_sw@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts new file mode 100644 index 0000000000..fbf0392b83 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -0,0 +1,236 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "ns2.dtsi" + +/ { + model = "Broadcom NS2 SVK"; + compatible = "brcm,ns2-svk", "brcm,ns2"; + + aliases { + serial0 = &uart3; + serial1 = &uart0; + serial2 = &uart1; + serial3 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x66130000"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; +}; + +&enet { + status = "okay"; +}; + +&pci_phy0 { + status = "okay"; +}; + +&pci_phy1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie8 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&ssp0 { + status = "okay"; + + slic@0 { + compatible = "silabs,si3226x"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable = <0>; + pl022,com-mode = <0>; + pl022,rx-level-trig = <1>; + pl022,tx-level-trig = <1>; + pl022,ctrl-len = <11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; +}; + +&ssp1 { + status = "okay"; + + at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + at25,byte-len = <0x8000>; + at25,addr-mode = <2>; + at25,page-size = <64>; + spi-cpha; + spi-cpol; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable = <0>; + pl022,com-mode = <0>; + pl022,rx-level-trig = <1>; + pl022,tx-level-trig = <1>; + pl022,ctrl-len = <11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sdio0 { + status = "okay"; +}; + +&sdio1 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mdio_mux_iproc { + mdio@10 { + gphy0: eth-phy@10 { + enet-phy-lane-swap; + reg = <0x10>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&qspi { + bspi-sel = <0>; + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts new file mode 100644 index 0000000000..1d314f17bb --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -0,0 +1,191 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "ns2.dtsi" + +/ { + model = "Broadcom NS2 XMC"; + compatible = "brcm,ns2-xmc", "brcm,ns2"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "earlycon=uart8250,mmio32,0x66130000"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000001 0x00000000>; + }; +}; + +&enet { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mdio_mux_iproc { + mdio@10 { + gphy0: eth-phy@10 { + reg = <0x10>; + }; + }; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00280000>; /* 2.5MB */ + read-only; + }; + + partition@280000 { + label = "nenv"; + reg = <0x00280000 0x00040000>; /* 0.25MB */ + read-only; + }; + + partition@2c0000 { + label = "ndtb"; + reg = <0x002c0000 0x00040000>; /* 0.25MB */ + read-only; + }; + + partition@300000 { + label = "nsystem"; + reg = <0x00300000 0x03d00000>; /* 61MB */ + read-only; + }; + + partition@4000000 { + label = "nrootfs"; + reg = <0x04000000 0x06400000>; /* 100MB */ + }; + + partition@a400000 { + label = "ncustfs"; + reg = <0x0a400000 0x35c00000>; /* 860MB */ + }; + }; +}; + +&pci_phy0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie8 { + status = "okay"; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&qspi { + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <62500000>; + m25p,default-addr-width = <3>; + reg = <0x0 0x0>; + + partition@0 { + label = "bl0"; + reg = <0x00000000 0x00080000>; /* 512KB */ + }; + + partition@80000 { + label = "fip"; + reg = <0x00080000 0x00150000>; /* 1344KB */ + }; + + partition@1e0000 { + label = "env"; + reg = <0x001e0000 0x00010000>;/* 64KB */ + }; + + partition@1f0000 { + label = "dtb"; + reg = <0x001f0000 0x00010000>; /* 64KB */ + }; + + partition@200000 { + label = "kernel"; + reg = <0x00200000 0x00e00000>; /* 14MB */ + }; + + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x01000000>; /* 16MB */ + }; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi new file mode 100644 index 0000000000..9dcd25ec2c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -0,0 +1,765 @@ +/* + * BSD LICENSE + * + * Copyright (c) 2015 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/memreserve/ 0x81000000 0x00200000; + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/bcm-ns2.h> + +/ { + compatible = "brcm,ns2"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + A57_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + A57_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0 1>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + A57_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0 2>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + A57_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0 3>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + CLUSTER0_L2: l2-cache@0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&A57_0>, + <&A57_1>, + <&A57_2>, + <&A57_3>; + }; + + pcie0: pcie@20020000 { + compatible = "brcm,iproc-pcie"; + reg = <0 0x20020000 0 0x1000>; + dma-coherent; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <0>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; + + brcm,pcie-ob; + brcm,pcie-ob-oarr-size; + brcm,pcie-ob-axi-offset = <0x00000000>; + brcm,pcie-ob-window-size = <256>; + + status = "disabled"; + + phys = <&pci_phy0>; + phy-names = "pcie-phy"; + + msi-parent = <&v2m0>; + }; + + pcie4: pcie@50020000 { + compatible = "brcm,iproc-pcie"; + reg = <0 0x50020000 0 0x1000>; + dma-coherent; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + + linux,pci-domain = <4>; + + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; + + brcm,pcie-ob; + brcm,pcie-ob-oarr-size; + brcm,pcie-ob-axi-offset = <0x30000000>; + brcm,pcie-ob-window-size = <256>; + + status = "disabled"; + + phys = <&pci_phy1>; + phy-names = "pcie-phy"; + + msi-parent = <&v2m0>; + }; + + pcie8: pcie@60c00000 { + compatible = "brcm,iproc-pcie-paxc"; + reg = <0 0x60c00000 0 0x1000>; + dma-coherent; + linux,pci-domain = <8>; + + bus-range = <0x0 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; + + status = "disabled"; + + msi-parent = <&v2m0>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + #include "ns2-clock.dtsi" + + enet: ethernet@61000000 { + compatible = "brcm,ns2-amac"; + reg = <0x61000000 0x1000>, + <0x61090000 0x1000>, + <0x61030000 0x100>; + reg-names = "amac_base", "idm_base", "nicpm_base"; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + phy-handle = <&gphy0>; + phy-mode = "rgmii"; + status = "disabled"; + }; + + pdc0: iproc-pdc0@612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; /* PDC FS0 regs */ + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + dma-coherent; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + crypto0: crypto@612d0000 { + compatible = "brcm,spum-crypto"; + reg = <0x612d0000 0x900>; + mboxes = <&pdc0 0>; + }; + + pdc1: iproc-pdc1@612e0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612e0000 0x445>; /* PDC FS1 regs */ + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + dma-coherent; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + crypto1: crypto@612f0000 { + compatible = "brcm,spum-crypto"; + reg = <0x612f0000 0x900>; + mboxes = <&pdc1 0>; + }; + + pdc2: iproc-pdc2@61300000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61300000 0x445>; /* PDC FS2 regs */ + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + dma-coherent; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + crypto2: crypto@61310000 { + compatible = "brcm,spum-crypto"; + reg = <0x61310000 0x900>; + mboxes = <&pdc2 0>; + }; + + pdc3: iproc-pdc3@61320000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x61320000 0x445>; /* PDC FS3 regs */ + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + dma-coherent; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; + + crypto3: crypto@61330000 { + compatible = "brcm,spum-crypto"; + reg = <0x61330000 0x900>; + mboxes = <&pdc3 0>; + }; + + dma0: dma-controller@61360000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x61360000 0x1000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&iprocslow>; + clock-names = "apb_pclk"; + }; + + smmu: iommu@64000000 { + compatible = "arm,mmu-500"; + reg = <0x64000000 0x40000>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + }; + + pinctrl: pinctrl@6501d130 { + compatible = "brcm,ns2-pinmux"; + reg = <0x6501d130 0x08>, + <0x660a0028 0x04>, + <0x660009b0 0x40>; + }; + + gpio_aon: gpio@65024800 { + compatible = "brcm,iproc-gpio"; + reg = <0x65024800 0x50>, + <0x65024008 0x18>; + ngpios = <6>; + #gpio-cells = <2>; + gpio-controller; + }; + + gic: interrupt-controller@65210000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x65210000 0x1000>, + <0x65220000 0x1000>, + <0x65240000 0x2000>, + <0x65260000 0x1000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | + IRQ_TYPE_LEVEL_HIGH)>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x652e0000 0x80000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x00000 0x1000>; + arm,msi-base-spi = <72>; + arm,msi-num-spis = <16>; + }; + + v2m1: v2m@10000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x10000 0x1000>; + arm,msi-base-spi = <88>; + arm,msi-num-spis = <16>; + }; + + v2m2: v2m@20000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x20000 0x1000>; + arm,msi-base-spi = <104>; + arm,msi-num-spis = <16>; + }; + + v2m3: v2m@30000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x30000 0x1000>; + arm,msi-base-spi = <120>; + arm,msi-num-spis = <16>; + }; + + v2m4: v2m@40000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x40000 0x1000>; + arm,msi-base-spi = <136>; + arm,msi-num-spis = <16>; + }; + + v2m5: v2m@50000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x50000 0x1000>; + arm,msi-base-spi = <152>; + arm,msi-num-spis = <16>; + }; + + v2m6: v2m@60000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x60000 0x1000>; + arm,msi-base-spi = <168>; + arm,msi-num-spis = <16>; + }; + + v2m7: v2m@70000 { + compatible = "arm,gic-v2m-frame"; + interrupt-parent = <&gic>; + msi-controller; + reg = <0x70000 0x1000>; + arm,msi-base-spi = <184>; + arm,msi-num-spis = <16>; + }; + }; + + cci@65590000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x65590000 0x1000>; + ranges = <0 0x65590000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + usbdrd_phy: phy@66000960 { + #phy-cells = <0>; + compatible = "brcm,ns2-drd-phy"; + reg = <0x66000960 0x24>, + <0x67012800 0x4>, + <0x6501d148 0x4>, + <0x664d0700 0x4>; + reg-names = "icfg", "rst-ctrl", + "crmu-ctrl", "usb2-strap"; + id-gpios = <&gpio_g 30 0>; + vbus-gpios = <&gpio_g 31 0>; + status = "disabled"; + }; + + pwm: pwm@66010000 { + compatible = "brcm,iproc-pwm"; + reg = <0x66010000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + + mdio_mux_iproc: mdio-mux@66020000 { + compatible = "brcm,mdio-mux-iproc"; + reg = <0x66020000 0x250>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + pci_phy0: pci-phy@0 { + compatible = "brcm,ns2-pcie-phy"; + reg = <0x0>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + mdio@7 { + reg = <0x7>; + #address-cells = <1>; + #size-cells = <0>; + + pci_phy1: pci-phy@0 { + compatible = "brcm,ns2-pcie-phy"; + reg = <0x0>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + mdio@10 { + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + timer0: timer@66030000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66030000 0x1000>; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer1: timer@66040000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66040000 0x1000>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer2: timer@66050000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66050000 0x1000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer3: timer@66060000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x66060000 0x1000>; + interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, + <&iprocslow>, + <&iprocslow>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + i2c0: i2c@66080000 { + compatible = "brcm,iproc-i2c"; + reg = <0x66080000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + wdt0: watchdog@66090000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x66090000 0x1000>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + gpio_g: gpio@660a0000 { + compatible = "brcm,iproc-gpio"; + reg = <0x660a0000 0x50>; + ngpios = <32>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c1: i2c@660b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x660b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + uart0: serial@66100000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66100000 0x100>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@66110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66110000 0x100>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@66120000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66120000 0x100>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@66130000 { + compatible = "snps,dw-apb-uart"; + reg = <0x66130000 0x100>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc>; + status = "disabled"; + }; + + ssp0: spi@66180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x66180000 0x1000>; + interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: spi@66190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x66190000 0x1000>; + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&iprocslow>, <&iprocslow>; + clock-names = "sspclk", "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hwrng: hwrng@66220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x66220000 0x28>; + }; + + sata_phy: sata_phy@663f0100 { + compatible = "brcm,iproc-ns2-sata-phy"; + reg = <0x663f0100 0x1f00>, + <0x663f004c 0x10>; + reg-names = "phy", "phy-ctrl"; + #address-cells = <1>; + #size-cells = <0>; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + sata: sata@663f2000 { + compatible = "brcm,iproc-ahci", "generic-ahci"; + reg = <0x663f2000 0x1000>; + dma-coherent; + reg-names = "ahci"; + interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + phy-names = "sata-phy"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + phy-names = "sata-phy"; + }; + }; + + sdio0: sdhci@66420000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x66420000 0x100>; + interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + bus-width = <8>; + clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; + status = "disabled"; + }; + + sdio1: sdhci@66430000 { + compatible = "brcm,sdhci-iproc-cygnus"; + reg = <0x66430000 0x100>; + interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + bus-width = <8>; + clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; + status = "disabled"; + }; + + nand: nand@66460000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x66460000 0x600>, + <0x67015408 0x600>, + <0x66460f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + brcm,nand-has-wp; + }; + + qspi: spi@66470200 { + compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; + reg = <0x66470200 0x184>, + <0x66470000 0x124>, + <0x67017408 0x004>, + <0x664703a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "spi_l1_intr"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/Makefile b/arch/arm64/boot/dts/broadcom/stingray/Makefile new file mode 100644 index 0000000000..20c7d0aa6c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742k.dtb +dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958742t.dtb + +dtb-$(CONFIG_ARCH_BCM_IPROC) += bcm958802a802x.dtb diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi new file mode 100644 index 0000000000..8fe7325cfb --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -0,0 +1,112 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "stingray-board-base.dtsi" + +/ { + sdio0_vddo_ctrl_reg: sdio0_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio0_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 18 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; + + sdio1_vddo_ctrl_reg: sdio1_vddo_ctrl { + compatible = "regulator-gpio"; + regulator-name = "sdio1_vddo_ctrl_reg"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pca9505 19 0>; + states = <3300000 0x0 + 1800000 0x1>; + }; +}; + +&pwm { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9505: pca9505@20 { + compatible = "nxp,pca9505"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; +}; + +&i2c1 { + status = "okay"; + + pcf8574: pcf8574@27 { + compatible = "nxp,pcf8574a"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + }; +}; + +&enet { + status = "okay"; +}; + +&nand { + status = "okay"; + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-bus-width = <16>; + brcm,nand-oob-sector-size = <16>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&sdio0 { + vqmmc-supply = <&sdio0_vddo_ctrl_reg>; + status = "okay"; +}; + +&sdio1 { + vqmmc-supply = <&sdio1_vddo_ctrl_reg>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts new file mode 100644 index 0000000000..dfac910a45 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -0,0 +1,86 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm958742-base.dtsi" + +/ { + compatible = "brcm,bcm958742k", "brcm,stingray"; + model = "Stingray Combo SVK (BCM958742K)"; +}; + +&gphy0 { + enet-phy-lane-swap; +}; + +&sdio0 { + mmc-ddr-1_8v; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&ssp0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 34 0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ssp1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio_hsls 96 0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts new file mode 100644 index 0000000000..55ba495ef5 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts @@ -0,0 +1,48 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm958742-base.dtsi" + +/ { + compatible = "brcm,bcm958742t", "brcm,stingray"; + model = "Stingray SST100 (BCM958742T)"; +}; + +&gphy0 { + enet-phy-lane-swap; +}; + +&sdio0 { + mmc-ddr-1_8v; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts new file mode 100644 index 0000000000..66471a25e4 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + +/dts-v1/; + +#include "stingray-board-base.dtsi" + +/ { + compatible = "brcm,bcm958802a802x", "brcm,stingray"; + model = "Stingray PS225xx (BCM958802A802x)"; +}; + +&enet { + status = "disabled"; +}; + +&sdio0 { + no-1-8-v; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi new file mode 100644 index 0000000000..cdd709491f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright(c) 2016-2018 Broadcom + */ + +#include "stingray.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&memory { /* Default DRAM banks */ + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */ +}; + +&enet { + phy-mode = "rgmii-id"; + phy-handle = <&gphy0>; +}; + +&uart1 { + status = "okay"; +}; + +&sdio0 { + non-removable; + full-pwr-cycle; +}; + +&sdio1 { + full-pwr-cycle; +}; + +&mdio_mux_iproc { + mdio@10 { + gphy0: eth-phy@10 { + reg = <0x10>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi new file mode 100644 index 0000000000..10a106aca2 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi @@ -0,0 +1,182 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/clock/bcm-sr.h> + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + crmu_ref25m: crmu_ref25m { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&osc>; + clock-div = <2>; + clock-mult = <1>; + }; + + genpll0: genpll0@1d104 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll0"; + reg = <0x0001d104 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll0", "clk_125m", "clk_scr", + "clk_250", "clk_pcie_axi", + "clk_paxc_axi_x2", + "clk_paxc_axi"; + }; + + genpll2: genpll2@1d1ac { + #clock-cells = <1>; + compatible = "brcm,sr-genpll2"; + reg = <0x0001d1ac 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll2", "clk_nic", + "clk_ts_500_ref", "clk_125_nitro", + "clk_chimp", "clk_nic_flash", + "clk_fs"; + }; + + genpll3: genpll3@1d1e0 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll3"; + reg = <0x0001d1e0 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll3", "clk_hsls", + "clk_sdio"; + }; + + genpll4: genpll4@1d214 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll4"; + reg = <0x0001d214 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll4", "clk_ccn", + "clk_tpiu_pll", "clk_noc", + "clk_chclk_fs4", + "clk_bridge_fscpu"; + }; + + genpll5: genpll5@1d248 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll5"; + reg = <0x0001d248 0x32>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "genpll5", "clk_fs4_hf", + "clk_crypto_ae", "clk_raid_ae"; + }; + + lcpll0: lcpll0@1d0c4 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll0"; + reg = <0x0001d0c4 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll0", "clk_sata_refp", + "clk_sata_refn", "clk_sata_350", + "clk_sata_500"; + }; + + lcpll1: lcpll1@1d138 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll1"; + reg = <0x0001d138 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll1", "clk_wan", + "clk_usb_ref", + "clk_crmu_ts"; + }; + + hsls_clk: hsls_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 1>; + clock-div = <1>; + clock-mult = <1>; + }; + + hsls_div2_clk: hsls_div2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <2>; + clock-mult = <1>; + + }; + + hsls_div4_clk: hsls_div4_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsls_25m_clk: hsls_25m_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&crmu_ref25m>; + clock-div = <1>; + clock-mult = <1>; + }; + + hsls_25m_div2_clk: hsls_25m_div2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hsls_25m_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + + sdio0_clk: sdio0_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; + clock-div = <1>; + clock-mult = <1>; + }; + + sdio1_clk: sdio1_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; + clock-div = <1>; + clock-mult = <1>; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi new file mode 100644 index 0000000000..9666969c8c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -0,0 +1,118 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + fs4: fs4 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x67000000 0x00800000>; + + crypto_mbox: crypto_mbox@0 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x00000000 0x200000>; + msi-parent = <&gic_its 0x4100>; + #mbox-cells = <3>; + dma-coherent; + }; + + raid_mbox: raid_mbox@400000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x00400000 0x200000>; + dma-coherent; + msi-parent = <&gic_its 0x4300>; + #mbox-cells = <3>; + }; + + raid0: raid@0 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 0 0x1 0xff00>, + <&raid_mbox 1 0x1 0xff00>, + <&raid_mbox 2 0x1 0xff00>, + <&raid_mbox 3 0x1 0xff00>; + }; + + raid1: raid@1 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 4 0x1 0xff00>, + <&raid_mbox 5 0x1 0xff00>, + <&raid_mbox 6 0x1 0xff00>, + <&raid_mbox 7 0x1 0xff00>; + }; + + raid2: raid@2 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 8 0x1 0xff00>, + <&raid_mbox 9 0x1 0xff00>, + <&raid_mbox 10 0x1 0xff00>, + <&raid_mbox 11 0x1 0xff00>; + }; + + raid3: raid@3 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 12 0x1 0xff00>, + <&raid_mbox 13 0x1 0xff00>, + <&raid_mbox 14 0x1 0xff00>, + <&raid_mbox 15 0x1 0xff00>; + }; + + raid4: raid@4 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 16 0x1 0xff00>, + <&raid_mbox 17 0x1 0xff00>, + <&raid_mbox 18 0x1 0xff00>, + <&raid_mbox 19 0x1 0xff00>; + }; + + raid5: raid@5 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 20 0x1 0xff00>, + <&raid_mbox 21 0x1 0xff00>, + <&raid_mbox 22 0x1 0xff00>, + <&raid_mbox 23 0x1 0xff00>; + }; + + raid6: raid@6 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 24 0x1 0xff00>, + <&raid_mbox 25 0x1 0xff00>, + <&raid_mbox 26 0x1 0xff00>, + <&raid_mbox 27 0x1 0xff00>; + }; + + raid7: raid@7 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 28 0x1 0xff00>, + <&raid_mbox 29 0x1 0xff00>, + <&raid_mbox 30 0x1 0xff00>, + <&raid_mbox 31 0x1 0xff00>; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi new file mode 100644 index 0000000000..663e517567 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + +pcie8: pcie@60400000 { + compatible = "brcm,iproc-pcie-paxc-v2"; + reg = <0 0x60400000 0 0x1000>; + linux,pci-domain = <8>; + + bus-range = <0x0 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>; + + dma-coherent; + + msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */ + <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */ + <0x101 &gic_its 0x2080 0x1>, /* PF1 */ + <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */ + <0x102 &gic_its 0x2100 0x1>, /* PF2 */ + <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */ + <0x103 &gic_its 0x2180 0x1>, /* PF3 */ + <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */ + <0x104 &gic_its 0x2200 0x1>, /* PF4 */ + <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */ + <0x105 &gic_its 0x2280 0x1>, /* PF5 */ + <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */ + <0x106 &gic_its 0x2300 0x1>, /* PF6 */ + <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */ + <0x107 &gic_its 0x2380 0x1>, /* PF7 */ + <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */ + + phys = <&pcie_phy 8>; + phy-names = "pcie-phy"; +}; + +pcie-ss { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40000000 0x800>; + + pcie_phy: phy@0 { + compatible = "brcm,sr-pcie-phy"; + reg = <0x0 0x200>; + brcm,sr-cdru = <&cdru>; + brcm,sr-mhb = <&mhb>; + #phy-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi new file mode 100644 index 0000000000..46a8275219 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -0,0 +1,346 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h> + + pinconf: pinconf@140000 { + compatible = "pinconf-single"; + reg = <0x00140000 0x250>; + pinctrl-single,register-width = <32>; + + /* pinconf functions */ + }; + + pinmux: pinmux@14029c { + compatible = "pinctrl-single"; + reg = <0x0014029c 0x26c>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + pinctrl-single,gpio-range = < + &range 0 91 MODE_GPIO + &range 95 60 MODE_GPIO + >; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + /* pinctrl functions */ + tsio_pins: gpio-14-pins { + pinctrl-single,pins = < + 0x038 MODE_NITRO /* tsio_0 */ + 0x03c MODE_NITRO /* tsio_1 */ + >; + }; + + nor_pins: pnor-adv-n-pins { + pinctrl-single,pins = < + 0x0ac MODE_PNOR /* nand_ce1_n */ + 0x0b0 MODE_PNOR /* nand_ce0_n */ + 0x0b4 MODE_PNOR /* nand_we_n */ + 0x0b8 MODE_PNOR /* nand_wp_n */ + 0x0bc MODE_PNOR /* nand_re_n */ + 0x0c0 MODE_PNOR /* nand_rdy_bsy_n */ + 0x0c4 MODE_PNOR /* nand_io0_0 */ + 0x0c8 MODE_PNOR /* nand_io1_0 */ + 0x0cc MODE_PNOR /* nand_io2_0 */ + 0x0d0 MODE_PNOR /* nand_io3_0 */ + 0x0d4 MODE_PNOR /* nand_io4_0 */ + 0x0d8 MODE_PNOR /* nand_io5_0 */ + 0x0dc MODE_PNOR /* nand_io6_0 */ + 0x0e0 MODE_PNOR /* nand_io7_0 */ + 0x0e4 MODE_PNOR /* nand_io8_0 */ + 0x0e8 MODE_PNOR /* nand_io9_0 */ + 0x0ec MODE_PNOR /* nand_io10_0 */ + 0x0f0 MODE_PNOR /* nand_io11_0 */ + 0x0f4 MODE_PNOR /* nand_io12_0 */ + 0x0f8 MODE_PNOR /* nand_io13_0 */ + 0x0fc MODE_PNOR /* nand_io14_0 */ + 0x100 MODE_PNOR /* nand_io15_0 */ + 0x104 MODE_PNOR /* nand_ale_0 */ + 0x108 MODE_PNOR /* nand_cle_0 */ + 0x040 MODE_PNOR /* pnor_adv_n */ + 0x044 MODE_PNOR /* pnor_baa_n */ + 0x048 MODE_PNOR /* pnor_bls_0_n */ + 0x04c MODE_PNOR /* pnor_bls_1_n */ + 0x050 MODE_PNOR /* pnor_cre */ + 0x054 MODE_PNOR /* pnor_cs_2_n */ + 0x058 MODE_PNOR /* pnor_cs_1_n */ + 0x05c MODE_PNOR /* pnor_cs_0_n */ + 0x060 MODE_PNOR /* pnor_we_n */ + 0x064 MODE_PNOR /* pnor_oe_n */ + 0x068 MODE_PNOR /* pnor_intr */ + 0x06c MODE_PNOR /* pnor_dat_0 */ + 0x070 MODE_PNOR /* pnor_dat_1 */ + 0x074 MODE_PNOR /* pnor_dat_2 */ + 0x078 MODE_PNOR /* pnor_dat_3 */ + 0x07c MODE_PNOR /* pnor_dat_4 */ + 0x080 MODE_PNOR /* pnor_dat_5 */ + 0x084 MODE_PNOR /* pnor_dat_6 */ + 0x088 MODE_PNOR /* pnor_dat_7 */ + 0x08c MODE_PNOR /* pnor_dat_8 */ + 0x090 MODE_PNOR /* pnor_dat_9 */ + 0x094 MODE_PNOR /* pnor_dat_10 */ + 0x098 MODE_PNOR /* pnor_dat_11 */ + 0x09c MODE_PNOR /* pnor_dat_12 */ + 0x0a0 MODE_PNOR /* pnor_dat_13 */ + 0x0a4 MODE_PNOR /* pnor_dat_14 */ + 0x0a8 MODE_PNOR /* pnor_dat_15 */ + >; + }; + + nand_pins: nand-ce1-n-pins { + pinctrl-single,pins = < + 0x0ac MODE_NAND /* nand_ce1_n */ + 0x0b0 MODE_NAND /* nand_ce0_n */ + 0x0b4 MODE_NAND /* nand_we_n */ + 0x0b8 MODE_NAND /* nand_wp_n */ + 0x0bc MODE_NAND /* nand_re_n */ + 0x0c0 MODE_NAND /* nand_rdy_bsy_n */ + 0x0c4 MODE_NAND /* nand_io0_0 */ + 0x0c8 MODE_NAND /* nand_io1_0 */ + 0x0cc MODE_NAND /* nand_io2_0 */ + 0x0d0 MODE_NAND /* nand_io3_0 */ + 0x0d4 MODE_NAND /* nand_io4_0 */ + 0x0d8 MODE_NAND /* nand_io5_0 */ + 0x0dc MODE_NAND /* nand_io6_0 */ + 0x0e0 MODE_NAND /* nand_io7_0 */ + 0x0e4 MODE_NAND /* nand_io8_0 */ + 0x0e8 MODE_NAND /* nand_io9_0 */ + 0x0ec MODE_NAND /* nand_io10_0 */ + 0x0f0 MODE_NAND /* nand_io11_0 */ + 0x0f4 MODE_NAND /* nand_io12_0 */ + 0x0f8 MODE_NAND /* nand_io13_0 */ + 0x0fc MODE_NAND /* nand_io14_0 */ + 0x100 MODE_NAND /* nand_io15_0 */ + 0x104 MODE_NAND /* nand_ale_0 */ + 0x108 MODE_NAND /* nand_cle_0 */ + >; + }; + + pwm0_pins: pwm-0-pins { + pinctrl-single,pins = < + 0x10c MODE_NITRO + >; + }; + + pwm1_pins: pwm-1-pins { + pinctrl-single,pins = < + 0x110 MODE_NITRO + >; + }; + + pwm2_pins: pwm-2-pins { + pinctrl-single,pins = < + 0x114 MODE_NITRO + >; + }; + + pwm3_pins: pwm-3-pins { + pinctrl-single,pins = < + 0x118 MODE_NITRO + >; + }; + + dbu_rxd_pins: uart1-sin-nitro-pins { + pinctrl-single,pins = < + 0x11c MODE_NITRO /* dbu_rxd */ + 0x120 MODE_NITRO /* dbu_txd */ + >; + }; + + uart1_pins: uart1-sin-nand-pins { + pinctrl-single,pins = < + 0x11c MODE_NAND /* uart1_sin */ + 0x120 MODE_NAND /* uart1_out */ + >; + }; + + uart2_pins: uart2-sin-pins { + pinctrl-single,pins = < + 0x124 MODE_NITRO /* uart2_sin */ + 0x128 MODE_NITRO /* uart2_out */ + >; + }; + + uart3_pins: uart3-sin-pins { + pinctrl-single,pins = < + 0x12c MODE_NITRO /* uart3_sin */ + 0x130 MODE_NITRO /* uart3_out */ + >; + }; + + i2s_pins: i2s-bitclk-pins { + pinctrl-single,pins = < + 0x134 MODE_NITRO /* i2s_bitclk */ + 0x138 MODE_NITRO /* i2s_sdout */ + 0x13c MODE_NITRO /* i2s_sdin */ + 0x140 MODE_NITRO /* i2s_ws */ + 0x144 MODE_NITRO /* i2s_mclk */ + 0x148 MODE_NITRO /* i2s_spdif_out */ + >; + }; + + qspi_pins: qspi-hold-n-pins { + pinctrl-single,pins = < + 0x14c MODE_NAND /* qspi_hold_n */ + 0x150 MODE_NAND /* qspi_wp_n */ + 0x154 MODE_NAND /* qspi_sck */ + 0x158 MODE_NAND /* qspi_cs_n */ + 0x15c MODE_NAND /* qspi_mosi */ + 0x160 MODE_NAND /* qspi_miso */ + >; + }; + + mdio_pins: ext-mdio-pins { + pinctrl-single,pins = < + 0x164 MODE_NITRO /* ext_mdio */ + 0x168 MODE_NITRO /* ext_mdc */ + >; + }; + + i2c0_pins: i2c0-sda-pins { + pinctrl-single,pins = < + 0x16c MODE_NITRO /* i2c0_sda */ + 0x170 MODE_NITRO /* i2c0_scl */ + >; + }; + + i2c1_pins: i2c1-sda-pins { + pinctrl-single,pins = < + 0x174 MODE_NITRO /* i2c1_sda */ + 0x178 MODE_NITRO /* i2c1_scl */ + >; + }; + + sdio0_pins: sdio0-cd-l-pins { + pinctrl-single,pins = < + 0x17c MODE_NITRO /* sdio0_cd_l */ + 0x180 MODE_NITRO /* sdio0_clk_sdcard */ + 0x184 MODE_NITRO /* sdio0_data0 */ + 0x188 MODE_NITRO /* sdio0_data1 */ + 0x18c MODE_NITRO /* sdio0_data2 */ + 0x190 MODE_NITRO /* sdio0_data3 */ + 0x194 MODE_NITRO /* sdio0_data4 */ + 0x198 MODE_NITRO /* sdio0_data5 */ + 0x19c MODE_NITRO /* sdio0_data6 */ + 0x1a0 MODE_NITRO /* sdio0_data7 */ + 0x1a4 MODE_NITRO /* sdio0_cmd */ + 0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */ + 0x1ac MODE_NITRO /* sdio0_led_on */ + 0x1b0 MODE_NITRO /* sdio0_wp */ + >; + }; + + sdio1_pins: sdio1-cd-l-pins { + pinctrl-single,pins = < + 0x1b4 MODE_NITRO /* sdio1_cd_l */ + 0x1b8 MODE_NITRO /* sdio1_clk_sdcard */ + 0x1bc MODE_NITRO /* sdio1_data0 */ + 0x1c0 MODE_NITRO /* sdio1_data1 */ + 0x1c4 MODE_NITRO /* sdio1_data2 */ + 0x1c8 MODE_NITRO /* sdio1_data3 */ + 0x1cc MODE_NITRO /* sdio1_data4 */ + 0x1d0 MODE_NITRO /* sdio1_data5 */ + 0x1d4 MODE_NITRO /* sdio1_data6 */ + 0x1d8 MODE_NITRO /* sdio1_data7 */ + 0x1dc MODE_NITRO /* sdio1_cmd */ + 0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */ + 0x1e4 MODE_NITRO /* sdio1_led_on */ + 0x1e8 MODE_NITRO /* sdio1_wp */ + >; + }; + + spi0_pins: spi0-sck-nand-pins { + pinctrl-single,pins = < + 0x1ec MODE_NITRO /* spi0_sck */ + 0x1f0 MODE_NITRO /* spi0_rxd */ + 0x1f4 MODE_NITRO /* spi0_fss */ + 0x1f8 MODE_NITRO /* spi0_txd */ + >; + }; + + spi1_pins: spi1-sck-nand-pins { + pinctrl-single,pins = < + 0x1fc MODE_NITRO /* spi1_sck */ + 0x200 MODE_NITRO /* spi1_rxd */ + 0x204 MODE_NITRO /* spi1_fss */ + 0x208 MODE_NITRO /* spi1_txd */ + >; + }; + + nuart_pins: uart0-sin-nitro-pins { + pinctrl-single,pins = < + 0x20c MODE_NITRO /* nuart_rxd */ + 0x210 MODE_NITRO /* nuart_txd */ + >; + }; + + uart0_pins: uart0-sin-nand-pins { + pinctrl-single,pins = < + 0x20c MODE_NAND /* uart0_sin */ + 0x210 MODE_NAND /* uart0_out */ + 0x214 MODE_NAND /* uart0_rts */ + 0x218 MODE_NAND /* uart0_cts */ + 0x21c MODE_NAND /* uart0_dtr */ + 0x220 MODE_NAND /* uart0_dcd */ + 0x224 MODE_NAND /* uart0_dsr */ + 0x228 MODE_NAND /* uart0_ri */ + >; + }; + + drdu2_pins: drdu2-overcurrent-pins { + pinctrl-single,pins = < + 0x22c MODE_NITRO /* drdu2_overcurrent */ + 0x230 MODE_NITRO /* drdu2_vbus_ppc */ + 0x234 MODE_NITRO /* drdu2_vbus_present */ + 0x238 MODE_NITRO /* drdu2_id */ + >; + }; + + drdu3_pins: drdu3-overcurrent-pins { + pinctrl-single,pins = < + 0x23c MODE_NITRO /* drdu3_overcurrent */ + 0x240 MODE_NITRO /* drdu3_vbus_ppc */ + 0x244 MODE_NITRO /* drdu3_vbus_present */ + 0x248 MODE_NITRO /* drdu3_id */ + >; + }; + + usb3h_pins: usb3h-overcurrent-pins { + pinctrl-single,pins = < + 0x24c MODE_NITRO /* usb3h_overcurrent */ + 0x250 MODE_NITRO /* usb3h_vbus_ppc */ + >; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi new file mode 100644 index 0000000000..ac4f7b8f92 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + *Copyright(c) 2018 Broadcom + */ + usb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x68500000 0x0 0x00400000>; + + /* + * Internally, USB bus to the interconnect can only address up + * to 40-bit + */ + dma-ranges = <0 0 0 0 0x100 0x0>; + + usbphy0: usb-phy@0 { + compatible = "brcm,sr-usb-combo-phy"; + reg = <0x0 0x00000000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + }; + + xhci0: usb@1000 { + compatible = "generic-xhci"; + reg = <0x0 0x00001000 0x0 0x1000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0 1>, <&usbphy0 0>; + phy-names = "phy0", "phy1"; + dma-coherent; + status = "disabled"; + }; + + bdc0: usb@2000 { + compatible = "brcm,bdc-v0.16"; + reg = <0x0 0x00002000 0x0 0x1000>; + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0 0>, <&usbphy0 1>; + phy-names = "phy0", "phy1"; + dma-coherent; + status = "disabled"; + }; + + usbphy1: usb-phy@10000 { + compatible = "brcm,sr-usb-combo-phy"; + reg = <0x0 0x00010000 0x0 0x100>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbphy2: usb-phy@20000 { + compatible = "brcm,sr-usb-hs-phy"; + reg = <0x0 0x00020000 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + xhci1: usb@11000 { + compatible = "generic-xhci"; + reg = <0x0 0x00011000 0x0 0x1000>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy1 1>, <&usbphy2>, <&usbphy1 0>; + phy-names = "phy0", "phy1", "phy2"; + dma-coherent; + status = "disabled"; + }; + + bdc1: usb@21000 { + compatible = "brcm,bdc-v0.16"; + reg = <0x0 0x00021000 0x0 0x1000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy2>; + phy-names = "phy0"; + dma-coherent; + status = "disabled"; + }; + }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi new file mode 100644 index 0000000000..f049687d6b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -0,0 +1,717 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2015-2017 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,stingray"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&CLUSTER0_L2>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&CLUSTER1_L2>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&CLUSTER2_L2>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + next-level-cache = <&CLUSTER2_L2>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&CLUSTER3_L2>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x301>; + enable-method = "psci"; + next-level-cache = <&CLUSTER3_L2>; + }; + + CLUSTER0_L2: l2-cache@0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + + CLUSTER1_L2: l2-cache@100 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + + CLUSTER2_L2: l2-cache@200 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + + CLUSTER3_L2: l2-cache@300 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + memory: memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + mhb: syscon@60401000 { + compatible = "brcm,sr-mhb", "syscon"; + reg = <0 0x60401000 0 0x38c>; + }; + + scr { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x61000000 0x05000000>; + + ccn: ccn@0 { + compatible = "arm,ccn-502"; + reg = <0x00000000 0x900000>; + interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@2c00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + reg = <0x02c00000 0x010000>, /* GICD */ + <0x02e00000 0x600000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@63c20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x02c20000 0x10000>; + }; + }; + + smmu: iommu@3000000 { + compatible = "arm,mmu-500"; + reg = <0x03000000 0x80000>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <2>; + }; + }; + + crmu: crmu { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x66400000 0x100000>; + + #include "stingray-clock.dtsi" + + otp: otp@1c400 { + compatible = "brcm,ocotp-v2"; + reg = <0x0001c400 0x68>; + brcm,ocotp-size = <2048>; + status = "okay"; + }; + + cdru: syscon@1d000 { + compatible = "brcm,sr-cdru", "syscon"; + reg = <0x0001d000 0x400>; + }; + + gpio_crmu: gpio@24800 { + compatible = "brcm,iproc-gpio"; + reg = <0x00024800 0x4c>; + ngpios = <6>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + #include "stingray-fs4.dtsi" + #include "stingray-pcie.dtsi" + #include "stingray-usb.dtsi" + + hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x68900000 0x17700000>; + + #include "stingray-pinctrl.dtsi" + + mdio_mux_iproc: mdio-mux@20000 { + compatible = "brcm,mdio-mux-iproc"; + reg = <0x00020000 0x250>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { /* PCIe serdes */ + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* USB */ + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@10 { /* RGMII */ + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm: pwm@10000 { + compatible = "brcm,iproc-pwm"; + reg = <0x00010000 0x1000>; + clocks = <&crmu_ref25m>; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer0: timer@30000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00030000 0x1000>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer1: timer@40000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00040000 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer2: timer@50000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00050000 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer3: timer@60000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00060000 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer4: timer@70000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00070000 0x1000>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer5: timer@80000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00080000 0x1000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer6: timer@90000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x00090000 0x1000>; + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + timer7: timer@a0000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x000a0000 0x1000>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, + <&hsls_25m_div2_clk>, + <&hsls_div4_clk>; + clock-names = "timer1", "timer2", "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@b0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x000b0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + wdt0: watchdog@c0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x000c0000 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; + clock-names = "wdog_clk", "apb_pclk"; + timeout-sec = <60>; + }; + + gpio_hsls: gpio@d0000 { + compatible = "brcm,iproc-gpio"; + reg = <0x000d0000 0x864>; + ngpios = <151>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinmux 0 0 16>, + <&pinmux 16 71 2>, + <&pinmux 18 131 8>, + <&pinmux 26 83 6>, + <&pinmux 32 123 4>, + <&pinmux 36 43 24>, + <&pinmux 60 89 2>, + <&pinmux 62 73 4>, + <&pinmux 66 95 28>, + <&pinmux 94 127 4>, + <&pinmux 98 139 10>, + <&pinmux 108 16 27>, + <&pinmux 135 77 6>, + <&pinmux 141 67 4>, + <&pinmux 145 149 6>; + }; + + i2c1: i2c@e0000 { + compatible = "brcm,iproc-i2c"; + reg = <0x000e0000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <100000>; + status = "disabled"; + }; + + uart0: serial@100000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00100000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart1: serial@110000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00110000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@120000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00120000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart3: serial@130000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00130000 0x1000>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ssp0: spi@180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00180000 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "sspclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssp1: spi@190000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00190000 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; + clock-names = "sspclk", "apb_pclk"; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hwrng: hwrng@220000 { + compatible = "brcm,iproc-rng200"; + reg = <0x00220000 0x28>; + }; + + dma0: dma-controller@310000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x00310000 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&hsls_div2_clk>; + clock-names = "apb_pclk"; + iommus = <&smmu 0x6000 0x0000>; + }; + + enet: ethernet@340000 { + compatible = "brcm,amac"; + reg = <0x00340000 0x1000>; + reg-names = "amac_base"; + dma-coherent; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + nand: nand@360000 { + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; + reg = <0x00360000 0x600>, + <0x0050a408 0x600>, + <0x00360f00 0x20>; + reg-names = "nand", "iproc-idm", "iproc-ext"; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + brcm,nand-has-wp; + status = "disabled"; + }; + + sdio0: sdhci@3f1000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f1000 0x100>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <8>; + clocks = <&sdio0_clk>; + iommus = <&smmu 0x6002 0x0000>; + status = "disabled"; + }; + + sdio1: sdhci@3f2000 { + compatible = "brcm,sdhci-iproc"; + reg = <0x003f2000 0x100>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + bus-width = <8>; + clocks = <&sdio1_clk>; + iommus = <&smmu 0x6003 0x0000>; + status = "disabled"; + }; + }; + + tmons { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x8f100000 0x100>; + + tmon: tmon@0 { + compatible = "brcm,sr-thermal"; + reg = <0x0 0x40>; + brcm,tmon-mask = <0x3f>; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + ihost0_thermal: ihost0-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 0>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost1_thermal: ihost1-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 1>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost2_thermal: ihost2-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 2>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + ihost3_thermal: ihost3-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 3>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + crmu_thermal: crmu-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 4>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + nitro_thermal: nitro-thermal { + polling-delay-passive = <0>; + polling-delay = <1000>; + thermal-sensors = <&tmon 5>; + trips { + cpu-crit { + temperature = <105000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + nic-hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x7fffffff>; + + nic_i2c0: i2c@60826100 { + compatible = "brcm,iproc-nic-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60826100 0x100>, + <0x60e00408 0x1000>; + brcm,ape-hsls-addr-mask = <0x03400000>; + clock-frequency = <100000>; + status = "disabled"; + }; + }; +}; |