diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:36 +0000 |
---|---|---|
committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:36 +0000 |
commit | 50ba0232fd5312410f1b65247e774244f89a628e (patch) | |
tree | fd8f2fc78e9e548af0ff9590276602ee6125be00 /arch/arm64/boot/dts/mediatek/mt8195.dtsi | |
parent | Releasing progress-linux version 6.7.12-1~progress7.99u1. (diff) | |
download | linux-50ba0232fd5312410f1b65247e774244f89a628e.tar.xz linux-50ba0232fd5312410f1b65247e774244f89a628e.zip |
Merging upstream version 6.8.9.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8195.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 464 |
1 files changed, 462 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 6708c4d21a..4dd7f75563 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -538,7 +538,7 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8195_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { reg = <MT8195_POWER_DOMAIN_MFG1>; clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; @@ -1119,7 +1119,7 @@ lvts_ap: thermal-sensor@1100b000 { compatible = "mediatek,mt8195-lvts-ap"; - reg = <0 0x1100b000 0 0x1000>; + reg = <0 0x1100b000 0 0xc00>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1128,6 +1128,18 @@ #thermal-sensor-cells = <1>; }; + svs: svs@1100bc00 { + compatible = "mediatek,mt8195-svs"; + reg = <0 0x1100bc00 0 0x400>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names = "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; @@ -1686,6 +1698,9 @@ lvts_efuse_data2: lvts2-calib@1d0 { reg = <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 { @@ -1718,6 +1733,26 @@ }; }; + mipi_tx0: dsi-phy@11c80000 { + compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c80000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_tx1: dsi-phy@11c90000 { + compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c90000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx1_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + i2c5: i2c@11d00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -1963,6 +1998,116 @@ compatible = "mediatek,mt8195-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; + }; + + dma-controller@14001000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, + <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; + clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; + mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, + <&gce1 13 CMDQ_THR_PRIO_1>, + <&gce1 14 CMDQ_THR_PRIO_1>, + <&gce1 21 CMDQ_THR_PRIO_1>, + <&gce1 22 CMDQ_THR_PRIO_1>; + #dma-cells = <1>; + }; + + display@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14002000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + }; + + display@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + }; + + display@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + }; + + display@14005000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14005000 0 0x1000>; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14006000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, + <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; + }; + + display@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14007000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; + + display@14008000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@14009000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; + }; + + display@1400a000 { + compatible = "mediatek,mt8195-mdp3-padding"; + reg = <0 0x1400a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_PADDING>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0 0x1400b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + }; + + dma-controller@1400c000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x1400c000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, + <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + #dma-cells = <1>; }; mutex@1400f000 { @@ -2077,6 +2222,7 @@ compatible = "mediatek,mt8195-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; }; mutex@14f01000 { @@ -2112,6 +2258,289 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; }; + display@14f06000 { + compatible = "mediatek,mt8195-mdp3-split"; + reg = <0 0x14f06000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, + <&vppsys1 CLK_VPP1_HDMI_META>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f07000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0 0x14f07000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; + }; + + dma-controller@14f08000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f08000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, + <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f09000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f09000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, + <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f0a000 { + compatible = "mediatek,mt8195-mdp3-rdma"; + reg = <0 0x14f0a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, + <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + display@14f0b000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; + }; + + display@14f0c000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0c000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; + }; + + display@14f0d000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0 0x14f0d000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; + }; + + display@14f0e000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f0e000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; + }; + + display@14f0f000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f0f000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; + }; + + display@14f10000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0 0x14f10000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; + }; + + display@14f11000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f11000 0 0x1000>; + interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f12000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f12000 0 0x1000>; + interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f13000 { + compatible = "mediatek,mt8195-mdp3-aal"; + reg = <0 0x14f13000 0 0x1000>; + interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f14000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f14000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, + <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; + }; + + display@14f15000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f15000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, + <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; + }; + + display@14f16000 { + compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; + reg = <0 0x14f16000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, + <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; + }; + + display@14f17000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f17000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; + }; + + display@14f18000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f18000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; + }; + + display@14f19000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0 0x14f19000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; + }; + + display@14f1a000 { + compatible = "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1a000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1b000 { + compatible = "mediatek,mt8195-mdp3-merge"; + reg = <0 0x14f1b000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1c000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1c000 0 0x1000>; + interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1d000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1d000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; + interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1e000 { + compatible = "mediatek,mt8195-mdp3-color"; + reg = <0 0x14f1e000 0 0x1000>; + interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f1f000 { + compatible = "mediatek,mt8195-mdp3-ovl"; + reg = <0 0x14f1f000 0 0x1000>; + interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; + }; + + display@14f20000 { + compatible = "mediatek,mt8195-mdp3-padding"; + reg = <0 0x14f20000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f21000 { + compatible = "mediatek,mt8195-mdp3-padding"; + reg = <0 0x14f21000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + display@14f22000 { + compatible = "mediatek,mt8195-mdp3-padding"; + reg = <0 0x14f22000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + + dma-controller@14f23000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f23000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, + <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f24000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f24000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + + dma-controller@14f25000 { + compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; + reg = <0 0x14f25000 0 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + #dma-cells = <1>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0 0x15000000 0 0x1000>; @@ -2623,6 +3052,7 @@ reg = <0 0x1c01a000 0 0x1000>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; #clock-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; }; @@ -2741,6 +3171,20 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; }; + dsi0: dsi@1c008000 { + compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x1c008000 0 0x1000>; + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSI0>, + <&vdosys0 CLK_VDO0_DSI0_DSI>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + dsc0: dsc@1c009000 { compatible = "mediatek,mt8195-disp-dsc"; reg = <0 0x1c009000 0 0x1000>; @@ -2750,6 +3194,20 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; }; + dsi1: dsi@1c012000 { + compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x1c012000 0 0x1000>; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + clocks = <&vdosys0 CLK_VDO0_DSI1>, + <&vdosys0 CLK_VDO0_DSI1_DSI>, + <&mipi_tx1>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx1>; + phy-names = "dphy"; + status = "disabled"; + }; + merge0: merge@1c014000 { compatible = "mediatek,mt8195-disp-merge"; reg = <0 0x1c014000 0 0x1000>; @@ -2776,6 +3234,7 @@ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; }; @@ -2846,6 +3305,7 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; clock-names = "vdo1_mutex"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; }; |