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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:36 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 18:50:36 +0000 |
commit | 50ba0232fd5312410f1b65247e774244f89a628e (patch) | |
tree | fd8f2fc78e9e548af0ff9590276602ee6125be00 /arch/arm64/boot/dts/sprd/ums512.dtsi | |
parent | Releasing progress-linux version 6.7.12-1~progress7.99u1. (diff) | |
download | linux-50ba0232fd5312410f1b65247e774244f89a628e.tar.xz linux-50ba0232fd5312410f1b65247e774244f89a628e.zip |
Merging upstream version 6.8.9.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'arch/arm64/boot/dts/sprd/ums512.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/sprd/ums512.dtsi | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index cc4459551e..dbdb79f8e9 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -683,8 +683,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f040000 0 0x1000>; cpu = <&CPU0>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -700,8 +700,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f140000 0 0x1000>; cpu = <&CPU1>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -717,8 +717,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f240000 0 0x1000>; cpu = <&CPU2>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -734,8 +734,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f340000 0 0x1000>; cpu = <&CPU3>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -751,8 +751,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f440000 0 0x1000>; cpu = <&CPU4>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -768,8 +768,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f540000 0 0x1000>; cpu = <&CPU5>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -785,8 +785,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f640000 0 0x1000>; cpu = <&CPU6>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { @@ -802,8 +802,8 @@ compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x3f740000 0 0x1000>; cpu = <&CPU7>; - clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; - clock-names = "apb_pclk", "clk_cs", "cs_src"; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; out-ports { port { |