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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
commitace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch)
treeb2d64bc10158fdd5497876388cd68142ca374ed3 /arch/openrisc/Kconfig
parentInitial commit. (diff)
downloadlinux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz
linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
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+# SPDX-License-Identifier: GPL-2.0
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.rst.
+#
+
+config OPENRISC
+ def_bool y
+ select ARCH_32BIT_OFF_T
+ select ARCH_HAS_DMA_SET_UNCACHED
+ select ARCH_HAS_DMA_CLEAR_UNCACHED
+ select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+ select COMMON_CLK
+ select OF
+ select OF_EARLY_FLATTREE
+ select IRQ_DOMAIN
+ select GPIOLIB
+ select HAVE_ARCH_TRACEHOOK
+ select SPARSE_IRQ
+ select GENERIC_IRQ_CHIP
+ select GENERIC_IRQ_PROBE
+ select GENERIC_IRQ_SHOW
+ select GENERIC_PCI_IOMAP
+ select GENERIC_IOREMAP
+ select GENERIC_CPU_DEVICES
+ select HAVE_PCI
+ select HAVE_UID16
+ select GENERIC_ATOMIC64
+ select GENERIC_CLOCKEVENTS_BROADCAST
+ select GENERIC_SMP_IDLE_THREAD
+ select MODULES_USE_ELF_RELA
+ select HAVE_DEBUG_STACKOVERFLOW
+ select OR1K_PIC
+ select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
+ select ARCH_USE_QUEUED_RWLOCKS
+ select OMPIC if SMP
+ select PCI_DOMAINS_GENERIC if PCI
+ select PCI_MSI if PCI
+ select ARCH_WANT_FRAME_POINTERS
+ select GENERIC_IRQ_MULTI_HANDLER
+ select MMU_GATHER_NO_RANGE if MMU
+ select TRACE_IRQFLAGS_SUPPORT
+
+config CPU_BIG_ENDIAN
+ def_bool y
+
+config MMU
+ def_bool y
+
+config GENERIC_HWEIGHT
+ def_bool y
+
+config NO_IOPORT_MAP
+ def_bool y
+
+# For now, use generic checksum functions
+#These can be reimplemented in assembly later if so inclined
+config GENERIC_CSUM
+ def_bool y
+
+config STACKTRACE_SUPPORT
+ def_bool y
+
+config LOCKDEP_SUPPORT
+ def_bool y
+
+menu "Processor type and features"
+
+choice
+ prompt "Subarchitecture"
+ default OR1K_1200
+
+config OR1K_1200
+ bool "OR1200"
+ help
+ Generic OpenRISC 1200 architecture
+
+endchoice
+
+config DCACHE_WRITETHROUGH
+ bool "Have write through data caches"
+ default n
+ help
+ Select this if your implementation features write through data caches.
+ Selecting 'N' here will allow the kernel to force flushing of data
+ caches at relevant times. Most OpenRISC implementations support write-
+ through data caches.
+
+ If unsure say N here
+
+config OPENRISC_BUILTIN_DTB
+ string "Builtin DTB"
+ default ""
+
+menu "Class II Instructions"
+
+config OPENRISC_HAVE_INST_FF1
+ bool "Have instruction l.ff1"
+ default y
+ help
+ Select this if your implementation has the Class II instruction l.ff1
+
+config OPENRISC_HAVE_INST_FL1
+ bool "Have instruction l.fl1"
+ default y
+ help
+ Select this if your implementation has the Class II instruction l.fl1
+
+config OPENRISC_HAVE_INST_MUL
+ bool "Have instruction l.mul for hardware multiply"
+ default y
+ help
+ Select this if your implementation has a hardware multiply instruction
+
+config OPENRISC_HAVE_INST_DIV
+ bool "Have instruction l.div for hardware divide"
+ default y
+ help
+ Select this if your implementation has a hardware divide instruction
+
+config OPENRISC_HAVE_INST_CMOV
+ bool "Have instruction l.cmov for conditional move"
+ default n
+ help
+ This config enables gcc to generate l.cmov instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.cmov conistional move instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_ROR
+ bool "Have instruction l.ror for rotate right"
+ default n
+ help
+ This config enables gcc to generate l.ror instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.ror rotate right instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_RORI
+ bool "Have instruction l.rori for rotate right with immediate"
+ default n
+ help
+ This config enables gcc to generate l.rori instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.rori rotate right with immediate instruction.
+
+ Say N if you are unsure.
+
+config OPENRISC_HAVE_INST_SEXT
+ bool "Have instructions l.ext* for sign extension"
+ default n
+ help
+ This config enables gcc to generate l.ext* instructions when compiling
+ the kernel which in general will improve performance and reduce the
+ binary size.
+
+ Select this if your implementation has support for the Class II
+ l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
+
+ Say N if you are unsure.
+
+endmenu
+
+config NR_CPUS
+ int "Maximum number of CPUs (2-32)"
+ range 2 32
+ depends on SMP
+ default "2"
+
+config SMP
+ bool "Symmetric Multi-Processing support"
+ help
+ This enables support for systems with more than one CPU. If you have
+ a system with only one CPU, say N. If you have a system with more
+ than one CPU, say Y.
+
+ If you don't know what to do here, say N.
+
+source "kernel/Kconfig.hz"
+
+config OPENRISC_NO_SPR_SR_DSX
+ bool "use SPR_SR_DSX software emulation" if OR1K_1200
+ default y
+ help
+ SPR_SR_DSX bit is status register bit indicating whether
+ the last exception has happened in delay slot.
+
+ OpenRISC architecture makes it optional to have it implemented
+ in hardware and the OR1200 does not have it.
+
+ Say N here if you know that your OpenRISC processor has
+ SPR_SR_DSX bit implemented. Say Y if you are unsure.
+
+config OPENRISC_HAVE_SHADOW_GPRS
+ bool "Support for shadow gpr files" if !SMP
+ default y if SMP
+ help
+ Say Y here if your OpenRISC processor features shadowed
+ register files. They will in such case be used as a
+ scratch reg storage on exception entry.
+
+ On SMP systems, this feature is mandatory.
+ On a unicore system it's safe to say N here if you are unsure.
+
+config CMDLINE
+ string "Default kernel command string"
+ default ""
+ help
+ On some architectures there is currently no way for the boot loader
+ to pass arguments to the kernel. For these architectures, you should
+ supply some command-line options at build time by entering them
+ here.
+
+menu "Debugging options"
+
+config JUMP_UPON_UNHANDLED_EXCEPTION
+ bool "Try to die gracefully"
+ default y
+ help
+ Now this puts kernel into infinite loop after first oops. Till
+ your kernel crashes this doesn't have any influence.
+
+ Say Y if you are unsure.
+
+config OPENRISC_ESR_EXCEPTION_BUG_CHECK
+ bool "Check for possible ESR exception bug"
+ default n
+ help
+ This option enables some checks that might expose some problems
+ in kernel.
+
+ Say N if you are unsure.
+
+endmenu
+
+endmenu