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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-11 08:27:49 +0000
commitace9429bb58fd418f0c81d4c2835699bddf6bde6 (patch)
treeb2d64bc10158fdd5497876388cd68142ca374ed3 /drivers/gpu/drm/amd/amdkfd/Kconfig
parentInitial commit. (diff)
downloadlinux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.tar.xz
linux-ace9429bb58fd418f0c81d4c2835699bddf6bde6.zip
Adding upstream version 6.6.15.upstream/6.6.15
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdkfd/Kconfig')
-rw-r--r--drivers/gpu/drm/amd/amdkfd/Kconfig40
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
new file mode 100644
index 0000000000..d3c3d3ab72
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: MIT
+#
+# Heterogeneous system architecture configuration
+#
+
+config HSA_AMD
+ bool "HSA kernel driver for AMD GPU devices"
+ depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64)
+ select HMM_MIRROR
+ select MMU_NOTIFIER
+ select DRM_AMDGPU_USERPTR
+ help
+ Enable this if you want to use HSA features on AMD GPU devices.
+
+config HSA_AMD_SVM
+ bool "Enable HMM-based shared virtual memory manager"
+ depends on HSA_AMD && DEVICE_PRIVATE
+ default y
+ select HMM_MIRROR
+ select MMU_NOTIFIER
+ help
+ Enable this to use unified memory and managed memory in HIP. This
+ memory manager supports two modes of operation. One based on
+ preemptions and one based on page faults. To enable page fault
+ based memory management on most GFXv9 GPUs, set the module
+ parameter amdgpu.noretry=0.
+
+config HSA_AMD_P2P
+ bool "HSA kernel driver support for peer-to-peer for AMD GPU devices"
+ depends on HSA_AMD && PCI_P2PDMA && DMABUF_MOVE_NOTIFY
+ help
+ Enable peer-to-peer (P2P) communication between AMD GPUs over
+ the PCIe bus. This can improve performance of multi-GPU compute
+ applications and libraries by enabling GPUs to access data directly
+ in peer GPUs' memory without intermediate copies in system memory.
+
+ This P2P feature is only enabled on compatible chipsets, and between
+ GPUs with large memory BARs that expose the entire VRAM in PCIe bus
+ address space within the physical address limits of the GPUs.
+