Merging upstream version 6.7.7.

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

14 files changed, 52 insertions, 1200 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
index 4a3e9e47b..af4d2065d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/Makefile
@@ -30,7 +30,6 @@ DCN30 := \
 	dcn30_dpp.o \
 	dcn30_optc.o \
 	dcn30_dccg.o \
-	dcn30_hwseq.o \
 	dcn30_mpc.o dcn30_vpg.o \
 	dcn30_afmt.o \
 	dcn30_dio_stream_encoder.o \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
index e0df9b006..ddb344056 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c
@@ -114,7 +114,6 @@ bool cm3_helper_translate_curve_to_hw_format(
 	struct pwl_result_data *rgb;
 	struct pwl_result_data *rgb_plus_1;
 	struct pwl_result_data *rgb_minus_1;
-	struct fixed31_32 end_value;
 
 	int32_t region_start, region_end;
 	int32_t i;
@@ -176,7 +175,7 @@ bool cm3_helper_translate_curve_to_hw_format(
 				NUMBER_SW_SEGMENTS;
 		for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 				i += increment) {
-			if (j == hw_points - 1)
+			if (j == hw_points)
 				break;
 			rgb_resulted[j].red = output_tf->tf_pts.red[i];
 			rgb_resulted[j].green = output_tf->tf_pts.green[i];
@@ -187,13 +186,13 @@ bool cm3_helper_translate_curve_to_hw_format(
 
 	/* last point */
 	start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
-	rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
-	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
-	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
+	rgb_resulted[hw_points].red = output_tf->tf_pts.red[start_index];
+	rgb_resulted[hw_points].green = output_tf->tf_pts.green[start_index];
+	rgb_resulted[hw_points].blue = output_tf->tf_pts.blue[start_index];
 
-	rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;
-	rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;
-	rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;
+	rgb_resulted[hw_points+1].red = rgb_resulted[hw_points].red;
+	rgb_resulted[hw_points+1].green = rgb_resulted[hw_points].green;
+	rgb_resulted[hw_points+1].blue = rgb_resulted[hw_points].blue;
 
 	// All 3 color channels have same x
 	corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),
@@ -220,34 +219,16 @@ bool cm3_helper_translate_curve_to_hw_format(
 	/* see comment above, m_arrPoints[1].y should be the Y value for the
 	 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 	 */
-	corner_points[1].red.y = rgb_resulted[hw_points - 1].red;
-	corner_points[1].green.y = rgb_resulted[hw_points - 1].green;
-	corner_points[1].blue.y = rgb_resulted[hw_points - 1].blue;
+	corner_points[1].red.y = rgb_resulted[hw_points].red;
+	corner_points[1].green.y = rgb_resulted[hw_points].green;
+	corner_points[1].blue.y = rgb_resulted[hw_points].blue;
 	corner_points[1].red.slope = dc_fixpt_zero;
 	corner_points[1].green.slope = dc_fixpt_zero;
 	corner_points[1].blue.slope = dc_fixpt_zero;
 
-	if (output_tf->tf == TRANSFER_FUNCTION_PQ || output_tf->tf == TRANSFER_FUNCTION_HLG) {
-		/* for PQ/HLG, we want to have a straight line from last HW X point,
-		 * and the slope to be such that we hit 1.0 at 10000/1000 nits.
-		 */
-
-		if (output_tf->tf == TRANSFER_FUNCTION_PQ)
-			end_value = dc_fixpt_from_int(125);
-		else
-			end_value = dc_fixpt_from_fraction(125, 10);
-
-		corner_points[1].red.slope = dc_fixpt_div(
-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].red.y),
-			dc_fixpt_sub(end_value, corner_points[1].red.x));
-		corner_points[1].green.slope = dc_fixpt_div(
-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].green.y),
-			dc_fixpt_sub(end_value, corner_points[1].green.x));
-		corner_points[1].blue.slope = dc_fixpt_div(
-			dc_fixpt_sub(dc_fixpt_one, corner_points[1].blue.y),
-			dc_fixpt_sub(end_value, corner_points[1].blue.x));
-	}
-	lut_params->hw_points_num = hw_points;
+	// DCN3+ have 257 pts in lieu of no separate slope registers
+	// Prior HW had 256 base+slope pairs
+	lut_params->hw_points_num = hw_points + 1;
 
 	k = 0;
 	for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
@@ -267,38 +248,37 @@ bool cm3_helper_translate_curve_to_hw_format(
 	rgb_plus_1 = rgb_resulted + 1;
 	rgb_minus_1 = rgb;
 
-	i = 1;
-	while (i != hw_points + 1) {
-		if (i >= hw_points - 1) {
-			if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
-				rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red);
-			if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
-				rgb_plus_1->green = dc_fixpt_add(rgb->green, rgb_minus_1->delta_green);
-			if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
-				rgb_plus_1->blue = dc_fixpt_add(rgb->blue, rgb_minus_1->delta_blue);
-		}
-
-		rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
-		rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
-		rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
+	if (fixpoint == true) {
+		i = 1;
+		while (i != hw_points + 2) {
+			if (i >= hw_points) {
+				if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
+					rgb_plus_1->red = dc_fixpt_add(rgb->red,
+							rgb_minus_1->delta_red);
+				if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
+					rgb_plus_1->green = dc_fixpt_add(rgb->green,
+							rgb_minus_1->delta_green);
+				if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
+					rgb_plus_1->blue = dc_fixpt_add(rgb->blue,
+							rgb_minus_1->delta_blue);
+			}
 
-		if (fixpoint == true) {
 			rgb->delta_red_reg   = dc_fixpt_clamp_u0d10(rgb->delta_red);
 			rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green);
 			rgb->delta_blue_reg  = dc_fixpt_clamp_u0d10(rgb->delta_blue);
 			rgb->red_reg         = dc_fixpt_clamp_u0d14(rgb->red);
 			rgb->green_reg       = dc_fixpt_clamp_u0d14(rgb->green);
 			rgb->blue_reg        = dc_fixpt_clamp_u0d14(rgb->blue);
-		}
 
-		++rgb_plus_1;
-		rgb_minus_1 = rgb;
-		++rgb;
-		++i;
+			++rgb_plus_1;
+			rgb_minus_1 = rgb;
+			++rgb;
+			++i;
+		}
 	}
 	cm3_helper_convert_to_custom_float(rgb_resulted,
 						lut_params->corner_points,
-						hw_points, fixpoint);
+						hw_points+1, fixpoint);
 
 	return true;
 }
@@ -603,24 +583,6 @@ bool cm3_helper_convert_to_custom_float(
 			return false;
 		}
 
-		if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
-						    &rgb->delta_red_reg)) {
-			BREAK_TO_DEBUGGER();
-			return false;
-		}
-
-		if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
-						    &rgb->delta_green_reg)) {
-			BREAK_TO_DEBUGGER();
-			return false;
-		}
-
-		if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
-						    &rgb->delta_blue_reg)) {
-			BREAK_TO_DEBUGGER();
-			return false;
-		}
-
 		++rgb;
 		++i;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
index 50dc83404..11f7746f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.c
@@ -613,16 +613,19 @@ static void dpp3_program_blnd_pwl(
 			REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 		REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 	} else {
+		REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
 		REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 4);
 		for (i = 0 ; i < num; i++)
 			REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg);
 		REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_red);
 
+		REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
 		REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 2);
 		for (i = 0 ; i < num; i++)
 			REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].green_reg);
 		REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, last_base_value_green);
 
+		REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0);
 		REG_UPDATE(CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, 1);
 		for (i = 0 ; i < num; i++)
 			REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].blue_reg);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
index 2082372d6..cea3208e4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h
@@ -195,7 +195,6 @@
 	TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
-	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\
 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
 	TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
@@ -427,7 +426,6 @@
 	type CM_GAMCOR_LUT_DATA; \
 	type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \
 	type CM_GAMCOR_LUT_READ_COLOR_SEL; \
-	type CM_GAMCOR_LUT_READ_DBG; \
 	type CM_GAMCOR_LUT_HOST_SEL; \
 	type CM_GAMCOR_LUT_CONFIG_MODE; \
 	type CM_GAMCOR_LUT_STATUS; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
index fc00ec0a0..a5d1b81e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.h
@@ -217,7 +217,6 @@
 	SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\
 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\
 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\
-	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_DBG, mask_sh),\
 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\
 	SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\
 	SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
@@ -525,7 +524,6 @@
 	type DWB_OGAM_LUT_DATA;\
 	type DWB_OGAM_LUT_WRITE_COLOR_MASK;\
 	type DWB_OGAM_LUT_READ_COLOR_SEL;\
-	type DWB_OGAM_LUT_READ_DBG;\
 	type DWB_OGAM_LUT_HOST_SEL;\
 	type DWB_OGAM_LUT_CONFIG_MODE;\
 	type DWB_OGAM_LUT_STATUS;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index 2861d974f..75547ce86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -316,7 +316,7 @@ bool hubp3_program_surface_flip_and_addr(
 	return true;
 }
 
-static void hubp3_program_tiling(
+void hubp3_program_tiling(
 	struct dcn20_hubp *hubp2,
 	const union dc_tiling_info *info,
 	const enum surface_pixel_format pixel_format)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
index 8a32772d4..b010531a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.h
@@ -278,6 +278,11 @@ void hubp3_setup(
 		struct _vcs_dpi_display_rq_regs_st *rq_regs,
 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
 
+void hubp3_program_tiling(
+		struct dcn20_hubp *hubp2,
+		const union dc_tiling_info *info,
+		const enum surface_pixel_format pixel_format);
+
 void hubp3_dcc_control(struct hubp *hubp, bool enable,
 		enum hubp_ind_block_size blk_size);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
deleted file mode 100644
index 255713ec2..000000000
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ /dev/null
@@ -1,1006 +0,0 @@
-/*
- * Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#include "dm_services.h"
-#include "dm_helpers.h"
-#include "core_types.h"
-#include "resource.h"
-#include "dcn30_hwseq.h"
-#include "dccg.h"
-#include "dce/dce_hwseq.h"
-#include "dcn30_mpc.h"
-#include "dcn30_dpp.h"
-#include "dcn10/dcn10_cm_common.h"
-#include "dcn30_cm_common.h"
-#include "reg_helper.h"
-#include "abm.h"
-#include "clk_mgr.h"
-#include "hubp.h"
-#include "dchubbub.h"
-#include "timing_generator.h"
-#include "opp.h"
-#include "ipp.h"
-#include "mpc.h"
-#include "mcif_wb.h"
-#include "dc_dmub_srv.h"
-#include "link_hwss.h"
-#include "dpcd_defs.h"
-#include "../dcn20/dcn20_hwseq.h"
-#include "dcn30_resource.h"
-#include "link.h"
-
-
-
-
-#define DC_LOGGER_INIT(logger)
-
-#define CTX \
-	hws->ctx
-#define REG(reg)\
-	hws->regs->reg
-#define DC_LOGGER \
-		dc->ctx->logger
-
-
-#undef FN
-#define FN(reg_name, field_name) \
-	hws->shifts->field_name, hws->masks->field_name
-
-bool dcn30_set_blend_lut(
-	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
-{
-	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
-	bool result = true;
-	struct pwl_params *blend_lut = NULL;
-
-	if (plane_state->blend_tf) {
-		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
-			blend_lut = &plane_state->blend_tf->pwl;
-		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
-			cm3_helper_translate_curve_to_hw_format(
-					plane_state->blend_tf, &dpp_base->regamma_params, false);
-			blend_lut = &dpp_base->regamma_params;
-		}
-	}
-	result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
-
-	return result;
-}
-
-static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
-				       const struct dc_stream_state *stream)
-{
-	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
-	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
-	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
-	bool result = false;
-	int acquired_rmu = 0;
-	int mpcc_id_projected = 0;
-
-	const struct pwl_params *shaper_lut = NULL;
-	//get the shaper lut params
-	if (stream->func_shaper) {
-		if (stream->func_shaper->type == TF_TYPE_HWPWL) {
-			shaper_lut = &stream->func_shaper->pwl;
-		} else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
-			cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
-							       &dpp_base->shaper_params, true);
-			shaper_lut = &dpp_base->shaper_params;
-		}
-	}
-
-	if (stream->lut3d_func &&
-	    stream->lut3d_func->state.bits.initialized == 1 &&
-	    stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
-		if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
-			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
-		else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
-			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
-		else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
-			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
-		if (mpcc_id_projected != mpcc_id)
-			BREAK_TO_DEBUGGER();
-		/* find the reason why logical layer assigned a different
-		 * mpcc_id into acquire_post_bldn_3dlut
-		 */
-		acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
-						       stream->lut3d_func->state.bits.rmu_mux_num);
-		if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
-			BREAK_TO_DEBUGGER();
-
-		result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d,
-						   stream->lut3d_func->state.bits.rmu_mux_num);
-		result = mpc->funcs->program_shaper(mpc, shaper_lut,
-						    stream->lut3d_func->state.bits.rmu_mux_num);
-	} else {
-		// loop through the available mux and release the requested mpcc_id
-		mpc->funcs->release_rmu(mpc, mpcc_id);
-	}
-
-	return result;
-}
-
-bool dcn30_set_input_transfer_func(struct dc *dc,
-				struct pipe_ctx *pipe_ctx,
-				const struct dc_plane_state *plane_state)
-{
-	struct dce_hwseq *hws = dc->hwseq;
-	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
-	enum dc_transfer_func_predefined tf;
-	bool result = true;
-	struct pwl_params *params = NULL;
-
-	if (dpp_base == NULL || plane_state == NULL)
-		return false;
-
-	tf = TRANSFER_FUNCTION_UNITY;
-
-	if (plane_state->in_transfer_func &&
-		plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
-		tf = plane_state->in_transfer_func->tf;
-
-	dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
-
-	if (plane_state->in_transfer_func) {
-		if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
-			params = &plane_state->in_transfer_func->pwl;
-		else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
-			cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
-					&dpp_base->degamma_params, false))
-			params = &dpp_base->degamma_params;
-	}
-
-	result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
-
-	if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
-		if (dpp_base->funcs->dpp_program_blnd_lut)
-			hws->funcs.set_blend_lut(pipe_ctx, plane_state);
-		if (dpp_base->funcs->dpp_program_shaper_lut &&
-				dpp_base->funcs->dpp_program_3dlut)
-			hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
-	}
-
-	return result;
-}
-
-bool dcn30_set_output_transfer_func(struct dc *dc,
-				struct pipe_ctx *pipe_ctx,
-				const struct dc_stream_state *stream)
-{
-	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
-	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
-	struct pwl_params *params = NULL;
-	bool ret = false;
-
-	/* program OGAM or 3DLUT only for the top pipe*/
-	if (pipe_ctx->top_pipe == NULL) {
-		/*program rmu shaper and 3dlut in MPC*/
-		ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
-		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
-			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
-				params = &stream->out_transfer_func->pwl;
-			else if (pipe_ctx->stream->out_transfer_func->type ==
-					TF_TYPE_DISTRIBUTED_POINTS &&
-					cm3_helper_translate_curve_to_hw_format(
-					stream->out_transfer_func,
-					&mpc->blender_params, false))
-				params = &mpc->blender_params;
-			 /* there are no ROM LUTs in OUTGAM */
-			if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
-				BREAK_TO_DEBUGGER();
-		}
-	}
-
-	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
-	return ret;
-}
-
-static void dcn30_set_writeback(
-		struct dc *dc,
-		struct dc_writeback_info *wb_info,
-		struct dc_state *context)
-{
-	struct mcif_wb *mcif_wb;
-	struct mcif_buf_params *mcif_buf_params;
-
-	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
-	ASSERT(wb_info->wb_enabled);
-	ASSERT(wb_info->mpcc_inst >= 0);
-	ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
-	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
-	mcif_buf_params = &wb_info->mcif_buf_params;
-
-	/* set DWB MPC mux */
-	dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
-			wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
-	/* set MCIF_WB buffer and arbitration configuration */
-	mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
-	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
-}
-
-void dcn30_update_writeback(
-		struct dc *dc,
-		struct dc_writeback_info *wb_info,
-		struct dc_state *context)
-{
-	struct dwbc *dwb;
-	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
-	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
-		__func__, wb_info->dwb_pipe_inst,\
-		wb_info->mpcc_inst);
-
-	dcn30_set_writeback(dc, wb_info, context);
-
-	/* update DWB */
-	dwb->funcs->update(dwb, &wb_info->dwb_params);
-}
-
-bool dcn30_mmhubbub_warmup(
-	struct dc *dc,
-	unsigned int num_dwb,
-	struct dc_writeback_info *wb_info)
-{
-	struct dwbc *dwb;
-	struct mcif_wb *mcif_wb;
-	struct mcif_warmup_params warmup_params = {0};
-	unsigned int  i, i_buf;
-	/*make sure there is no active DWB eanbled */
-	for (i = 0; i < num_dwb; i++) {
-		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
-		if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
-			/*can not do warmup while any dwb enabled*/
-			return false;
-		}
-	}
-
-	if (wb_info->mcif_warmup_params.p_vmid == 0)
-		return false;
-
-	/*check whether this is new interface: warmup big buffer once*/
-	if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
-		wb_info->mcif_warmup_params.region_size != 0) {
-		/*mmhubbub is shared, so it does not matter which MCIF*/
-		mcif_wb = dc->res_pool->mcif_wb[0];
-		/*warmup a big chunk of VM buffer at once*/
-		warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
-		warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
-		warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
-		warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
-
-		if (warmup_params.address_increment == 0)
-			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
-
-		mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
-		return true;
-	}
-	/*following is the original: warmup each DWB's mcif buffer*/
-	for (i = 0; i < num_dwb; i++) {
-		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
-		mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
-		/*warmup is for VM mode only*/
-		if (wb_info[i].mcif_buf_params.p_vmid == 0)
-			return false;
-
-		/* Warmup MCIF_WB */
-		for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
-			warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
-			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
-			warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
-			warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
-			mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
-		}
-	}
-	return true;
-}
-
-void dcn30_enable_writeback(
-		struct dc *dc,
-		struct dc_writeback_info *wb_info,
-		struct dc_state *context)
-{
-	struct dwbc *dwb;
-	struct mcif_wb *mcif_wb;
-
-	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
-	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
-
-	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
-		__func__, wb_info->dwb_pipe_inst,\
-		wb_info->mpcc_inst);
-	/* Update writeback pipe */
-	dcn30_set_writeback(dc, wb_info, context);
-
-	/* Enable MCIF_WB */
-	mcif_wb->funcs->enable_mcif(mcif_wb);
-	/* Enable DWB */
-	dwb->funcs->enable(dwb, &wb_info->dwb_params);
-}
-
-void dcn30_disable_writeback(
-		struct dc *dc,
-		unsigned int dwb_pipe_inst)
-{
-	struct dwbc *dwb;
-	struct mcif_wb *mcif_wb;
-
-	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
-	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
-	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
-	DC_LOG_DWB("%s dwb_pipe_inst = %d",\
-		__func__, dwb_pipe_inst);
-
-	/* disable DWB */
-	dwb->funcs->disable(dwb);
-	/* disable MCIF */
-	mcif_wb->funcs->disable_mcif(mcif_wb);
-	/* disable MPC DWB mux */
-	dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
-}
-
-void dcn30_program_all_writeback_pipes_in_tree(
-		struct dc *dc,
-		const struct dc_stream_state *stream,
-		struct dc_state *context)
-{
-	struct dc_writeback_info wb_info;
-	struct dwbc *dwb;
-	struct dc_stream_status *stream_status = NULL;
-	int i_wb, i_pipe, i_stream;
-	DC_LOG_DWB("%s", __func__);
-
-	ASSERT(stream);
-	for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
-		if (context->streams[i_stream] == stream) {
-			stream_status = &context->stream_status[i_stream];
-			break;
-		}
-	}
-	ASSERT(stream_status);
-
-	ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
-	/* For each writeback pipe */
-	for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
-
-		/* copy writeback info to local non-const so mpcc_inst can be set */
-		wb_info = stream->writeback_info[i_wb];
-		if (wb_info.wb_enabled) {
-
-			/* get the MPCC instance for writeback_source_plane */
-			wb_info.mpcc_inst = -1;
-			for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
-				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
-
-				if (!pipe_ctx->plane_state)
-					continue;
-
-				if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
-					wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
-					break;
-				}
-			}
-
-			if (wb_info.mpcc_inst == -1) {
-				/* Disable writeback pipe and disconnect from MPCC
-				 * if source plane has been removed
-				 */
-				dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
-				continue;
-			}
-
-			ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
-			dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
-			if (dwb->funcs->is_enabled(dwb)) {
-				/* writeback pipe already enabled, only need to update */
-				dc->hwss.update_writeback(dc, &wb_info, context);
-			} else {
-				/* Enable writeback pipe and connect to MPCC */
-				dc->hwss.enable_writeback(dc, &wb_info, context);
-			}
-		} else {
-			/* Disable writeback pipe and disconnect from MPCC */
-			dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
-		}
-	}
-}
-
-void dcn30_init_hw(struct dc *dc)
-{
-	struct abm **abms = dc->res_pool->multiple_abms;
-	struct dce_hwseq *hws = dc->hwseq;
-	struct dc_bios *dcb = dc->ctx->dc_bios;
-	struct resource_pool *res_pool = dc->res_pool;
-	int i;
-	int edp_num;
-	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
-
-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
-
-	// Initialize the dccg
-	if (res_pool->dccg->funcs->dccg_init)
-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
-
-	if (!dcb->funcs->is_accelerated_mode(dcb)) {
-		hws->funcs.bios_golden_init(dc);
-		hws->funcs.disable_vga(dc->hwseq);
-	}
-
-	if (dc->debug.enable_mem_low_power.bits.dmcu) {
-		// Force ERAM to shutdown if DMCU is not enabled
-		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
-			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
-		}
-	}
-
-	// Set default OPTC memory power states
-	if (dc->debug.enable_mem_low_power.bits.optc) {
-		// Shutdown when unassigned and light sleep in VBLANK
-		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
-	}
-
-	if (dc->debug.enable_mem_low_power.bits.vga) {
-		// Power down VGA memory
-		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
-	}
-
-	if (dc->ctx->dc_bios->fw_info_valid) {
-		res_pool->ref_clocks.xtalin_clock_inKhz =
-				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
-
-		if (res_pool->dccg && res_pool->hubbub) {
-
-			(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
-					dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
-					&res_pool->ref_clocks.dccg_ref_clock_inKhz);
-
-			(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
-					res_pool->ref_clocks.dccg_ref_clock_inKhz,
-					&res_pool->ref_clocks.dchub_ref_clock_inKhz);
-		} else {
-			// Not all ASICs have DCCG sw component
-			res_pool->ref_clocks.dccg_ref_clock_inKhz =
-					res_pool->ref_clocks.xtalin_clock_inKhz;
-			res_pool->ref_clocks.dchub_ref_clock_inKhz =
-					res_pool->ref_clocks.xtalin_clock_inKhz;
-		}
-	} else
-		ASSERT_CRITICAL(false);
-
-	for (i = 0; i < dc->link_count; i++) {
-		/* Power up AND update implementation according to the
-		 * required signal (which may be different from the
-		 * default signal on connector).
-		 */
-		struct dc_link *link = dc->links[i];
-
-		link->link_enc->funcs->hw_init(link->link_enc);
-
-		/* Check for enabled DIG to identify enabled display */
-		if (link->link_enc->funcs->is_dig_enabled &&
-			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
-			link->link_status.link_active = true;
-			if (link->link_enc->funcs->fec_is_active &&
-					link->link_enc->funcs->fec_is_active(link->link_enc))
-				link->fec_state = dc_link_fec_enabled;
-		}
-	}
-
-	/* we want to turn off all dp displays before doing detection */
-	dc->link_srv->blank_all_dp_displays(dc);
-
-	if (hws->funcs.enable_power_gating_plane)
-		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
-
-	/* If taking control over from VBIOS, we may want to optimize our first
-	 * mode set, so we need to skip powering down pipes until we know which
-	 * pipes we want to use.
-	 * Otherwise, if taking control is not possible, we need to power
-	 * everything down.
-	 */
-	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
-		hws->funcs.init_pipes(dc, dc->current_state);
-		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
-			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
-					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
-	}
-
-	/* In headless boot cases, DIG may be turned
-	 * on which causes HW/SW discrepancies.
-	 * To avoid this, power down hardware on boot
-	 * if DIG is turned on and seamless boot not enabled
-	 */
-	if (!dc->config.seamless_boot_edp_requested) {
-		struct dc_link *edp_links[MAX_NUM_EDP];
-		struct dc_link *edp_link = NULL;
-
-		dc_get_edp_links(dc, edp_links, &edp_num);
-		if (edp_num)
-			edp_link = edp_links[0];
-		if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
-				edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
-				dc->hwss.edp_backlight_control &&
-				dc->hwss.power_down &&
-				dc->hwss.edp_power_control) {
-			dc->hwss.edp_backlight_control(edp_link, false);
-			dc->hwss.power_down(dc);
-			dc->hwss.edp_power_control(edp_link, false);
-		} else {
-			for (i = 0; i < dc->link_count; i++) {
-				struct dc_link *link = dc->links[i];
-
-				if (link->link_enc->funcs->is_dig_enabled &&
-						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
-						dc->hwss.power_down) {
-					dc->hwss.power_down(dc);
-					break;
-				}
-
-			}
-		}
-	}
-
-	for (i = 0; i < res_pool->audio_count; i++) {
-		struct audio *audio = res_pool->audios[i];
-
-		audio->funcs->hw_init(audio);
-	}
-
-	for (i = 0; i < dc->link_count; i++) {
-		struct dc_link *link = dc->links[i];
-
-		if (link->panel_cntl)
-			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
-	}
-
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (abms[i] != NULL)
-			abms[i]->funcs->abm_init(abms[i], backlight);
-	}
-
-	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
-	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
-
-	if (!dc->debug.disable_clock_gate) {
-		/* enable all DCN clock gating */
-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
-
-		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
-	}
-
-	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
-		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
-
-	if (dc->clk_mgr->funcs->notify_wm_ranges)
-		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
-
-	//if softmax is enabled then hardmax will be set by a different call
-	if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
-		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
-
-	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
-		dc->res_pool->hubbub->funcs->force_pstate_change_control(
-				dc->res_pool->hubbub, false, false);
-	if (dc->res_pool->hubbub->funcs->init_crb)
-		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
-
-	// Get DMCUB capabilities
-	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);
-	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
-	dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
-}
-
-void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
-{
-	if (pipe_ctx == NULL)
-		return;
-
-	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
-		pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
-				pipe_ctx->stream_res.stream_enc,
-				enable);
-}
-
-void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
-{
-	bool is_hdmi_tmds;
-	bool is_dp;
-
-	ASSERT(pipe_ctx->stream);
-
-	if (pipe_ctx->stream_res.stream_enc == NULL)
-		return;  /* this is not root pipe */
-
-	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
-	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
-
-	if (!is_hdmi_tmds && !is_dp)
-		return;
-
-	if (is_hdmi_tmds)
-		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
-			pipe_ctx->stream_res.stream_enc,
-			&pipe_ctx->stream_res.encoder_info_frame);
-	else {
-		if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
-			pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
-				pipe_ctx->stream_res.stream_enc,
-				&pipe_ctx->stream_res.encoder_info_frame);
-
-		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
-			pipe_ctx->stream_res.stream_enc,
-			&pipe_ctx->stream_res.encoder_info_frame);
-	}
-}
-
-void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
-{
-	struct dc_stream_state    *stream     = pipe_ctx->stream;
-	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
-	bool                       enable     = false;
-	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
-	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
-							? dmdata_dp
-							: dmdata_hdmi;
-
-	/* if using dynamic meta, don't set up generic infopackets */
-	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
-		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
-		enable = true;
-	}
-
-	if (!hubp)
-		return;
-
-	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
-		return;
-
-	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
-							hubp->inst, mode);
-}
-
-bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
-{
-	union dmub_rb_cmd cmd;
-	uint32_t tmr_delay = 0, tmr_scale = 0;
-	struct dc_cursor_attributes cursor_attr;
-	bool cursor_cache_enable = false;
-	struct dc_stream_state *stream = NULL;
-	struct dc_plane_state *plane = NULL;
-
-	if (!dc->ctx->dmub_srv)
-		return false;
-
-	if (enable) {
-		if (dc->current_state) {
-			int i;
-
-			/* First, check no-memory-requests case */
-			for (i = 0; i < dc->current_state->stream_count; i++) {
-				if (dc->current_state->stream_status[i].plane_count)
-					/* Fail eligibility on a visible stream */
-					break;
-			}
-
-			if (i == dc->current_state->stream_count) {
-				/* Enable no-memory-requests case */
-				memset(&cmd, 0, sizeof(cmd));
-				cmd.mall.header.type = DMUB_CMD__MALL;
-				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
-				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
-
-				dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
-
-				return true;
-			}
-
-			stream = dc->current_state->streams[0];
-			plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
-
-			if (stream && plane) {
-				cursor_cache_enable = stream->cursor_position.enable &&
-						plane->address.grph.cursor_cache_addr.quad_part;
-				cursor_attr = stream->cursor_attributes;
-			}
-
-			/*
-			 * Second, check MALL eligibility
-			 *
-			 * single display only, single surface only, 8 and 16 bit formats only, no VM,
-			 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
-			 *
-			 * TODO: When we implement multi-display, PSR displays will be allowed if there is
-			 * a non-PSR display present, since in that case we can't do D0i3.2
-			 */
-			if (dc->current_state->stream_count == 1 &&
-					stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
-					dc->current_state->stream_status[0].plane_count == 1 &&
-					plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
-					plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
-					plane->address.page_table_base.quad_part == 0 &&
-					dc->hwss.does_plane_fit_in_mall &&
-					dc->hwss.does_plane_fit_in_mall(dc, plane,
-							cursor_cache_enable ? &cursor_attr : NULL)) {
-				unsigned int v_total = stream->adjust.v_total_max ?
-						stream->adjust.v_total_max : stream->timing.v_total;
-				unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
-						100LL, (v_total * stream->timing.h_total));
-
-				/*
-				 * one frame time in microsec:
-				 * Delay_Us = 1000000 / refresh
-				 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
-				 *
-				 * one frame time modified by 'additional timer percent' (p):
-				 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
-				 *                   = dynamic_delay_us * (1 + p / 100)
-				 *                   = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
-				 *                   = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
-				 *
-				 * formula for timer duration based on parameters, from regspec:
-				 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
-				 *
-				 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
-				 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
-				 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
-				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
-				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
-				 *
-				 * need to round up the result of the division before the subtraction
-				 */
-				unsigned int denom = refresh_hz * 6528;
-				unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
-
-				tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
-						(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
-						denom) - 64LL;
-
-				/* In some cases the stutter period is really big (tiny modes) in these
-				 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
-				 *
-				 * We can check if stutter_period is more than 1/10th the frame time to
-				 * consider if we can actually meet the range of hysteresis timer
-				 */
-				if (stutter_period > 100000/refresh_hz)
-					return false;
-
-				/* scale should be increased until it fits into 6 bits */
-				while (tmr_delay & ~0x3F) {
-					tmr_scale++;
-
-					if (tmr_scale > 3) {
-						/* Delay exceeds range of hysteresis timer */
-						ASSERT(false);
-						return false;
-					}
-
-					denom *= 2;
-					tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
-							(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
-							denom) - 64LL;
-				}
-
-				/* Copy HW cursor */
-				if (cursor_cache_enable) {
-					memset(&cmd, 0, sizeof(cmd));
-					cmd.mall.header.type = DMUB_CMD__MALL;
-					cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
-					cmd.mall.header.payload_bytes =
-							sizeof(cmd.mall) - sizeof(cmd.mall.header);
-
-					switch (cursor_attr.color_format) {
-					case CURSOR_MODE_MONO:
-						cmd.mall.cursor_bpp = 2;
-						break;
-					case CURSOR_MODE_COLOR_1BIT_AND:
-					case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-					case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-						cmd.mall.cursor_bpp = 32;
-						break;
-
-					case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
-					case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
-						cmd.mall.cursor_bpp = 64;
-						break;
-					}
-
-					cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
-					cmd.mall.cursor_copy_dst.quad_part =
-							(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
-					cmd.mall.cursor_width = cursor_attr.width;
-					cmd.mall.cursor_height = cursor_attr.height;
-					cmd.mall.cursor_pitch = cursor_attr.pitch;
-
-					dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
-
-					/* Use copied cursor, and it's okay to not switch back */
-					cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
-					dc_stream_set_cursor_attributes(stream, &cursor_attr);
-				}
-
-				/* Enable MALL */
-				memset(&cmd, 0, sizeof(cmd));
-				cmd.mall.header.type = DMUB_CMD__MALL;
-				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
-				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
-				cmd.mall.tmr_delay = tmr_delay;
-				cmd.mall.tmr_scale = tmr_scale;
-				cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
-
-				dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
-
-				return true;
-			}
-		}
-
-		/* No applicable optimizations */
-		return false;
-	}
-
-	/* Disable MALL */
-	memset(&cmd, 0, sizeof(cmd));
-	cmd.mall.header.type = DMUB_CMD__MALL;
-	cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
-	cmd.mall.header.payload_bytes =
-		sizeof(cmd.mall) - sizeof(cmd.mall.header);
-
-	dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
-
-	return true;
-}
-
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
-{
-	// add meta size?
-	unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
-			(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
-	unsigned int mall_size = dc->caps.mall_size_total;
-	unsigned int cursor_size = 0;
-
-	if (dc->debug.mall_size_override)
-		mall_size = 1024 * 1024 * dc->debug.mall_size_override;
-
-	if (cursor_attr) {
-		cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
-
-		switch (cursor_attr->color_format) {
-		case CURSOR_MODE_MONO:
-			cursor_size /= 2;
-			break;
-		case CURSOR_MODE_COLOR_1BIT_AND:
-		case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
-		case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
-			cursor_size *= 4;
-			break;
-
-		case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
-		case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
-			cursor_size *= 8;
-			break;
-		}
-	}
-
-	return (surface_size + cursor_size) < mall_size;
-}
-
-void dcn30_hardware_release(struct dc *dc)
-{
-	bool subvp_in_use = false;
-	uint32_t i;
-
-	dc_dmub_srv_p_state_delegate(dc, false, NULL);
-	dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
-
-	/* SubVP treated the same way as FPO. If driver disable and
-	 * we are using a SubVP config, disable and force on DCN side
-	 * to prevent P-State hang on driver enable.
-	 */
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-
-		if (!pipe->stream)
-			continue;
-
-		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
-			subvp_in_use = true;
-			break;
-		}
-	}
-	/* If pstate unsupported, or still supported
-	 * by firmware, force it supported by dcn
-	 */
-	if (dc->current_state)
-		if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
-				dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
-				dc->res_pool->hubbub->funcs->force_pstate_change_control)
-			dc->res_pool->hubbub->funcs->force_pstate_change_control(
-					dc->res_pool->hubbub, true, true);
-}
-
-void dcn30_set_disp_pattern_generator(const struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		enum controller_dp_test_pattern test_pattern,
-		enum controller_dp_color_space color_space,
-		enum dc_color_depth color_depth,
-		const struct tg_color *solid_color,
-		int width, int height, int offset)
-{
-	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
-			color_space, color_depth, solid_color, width, height, offset);
-}
-
-void dcn30_prepare_bandwidth(struct dc *dc,
-	struct dc_state *context)
-{
-	bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
-	/* Any transition into an FPO config should disable MCLK switching first to avoid
-	 * driver and FW P-State synchronization issues.
-	 */
-	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
-		dc->optimized_required = true;
-		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
-	}
-
-	if (dc->clk_mgr->dc_mode_softmax_enabled)
-		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
-				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
-			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
-
-	dcn20_prepare_bandwidth(dc, context);
-	/*
-	 * enabled -> enabled: do not disable
-	 * enabled -> disabled: disable
-	 * disabled -> enabled: don't care
-	 * disabled -> disabled: don't care
-	 */
-	if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
-		dc_dmub_srv_p_state_delegate(dc, false, context);
-
-	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) {
-		/* After disabling P-State, restore the original value to ensure we get the correct P-State
-		 * on the next optimize. */
-		context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support;
-	}
-}
-
-void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
-		int num_pipes, const struct dc_static_screen_params *params)
-{
-	unsigned int i;
-	unsigned int triggers = 0;
-
-	if (params->triggers.surface_update)
-		triggers |= 0x100;
-	if (params->triggers.cursor_update)
-		triggers |= 0x8;
-	if (params->triggers.force_trigger)
-		triggers |= 0x1;
-
-	for (i = 0; i < num_pipes; i++)
-		pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg,
-					triggers, params->num_frames);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
deleted file mode 100644
index ce19c5409..000000000
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
-* Copyright 2020 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DC_HWSS_DCN30_H__
-#define __DC_HWSS_DCN30_H__
-
-#include "hw_sequencer_private.h"
-#include "dcn20/dcn20_hwseq.h"
-struct dc;
-
-void dcn30_init_hw(struct dc *dc);
-void dcn30_program_all_writeback_pipes_in_tree(
-		struct dc *dc,
-		const struct dc_stream_state *stream,
-		struct dc_state *context);
-void dcn30_update_writeback(
-		struct dc *dc,
-		struct dc_writeback_info *wb_info,
-		struct dc_state *context);
-void dcn30_enable_writeback(
-		struct dc *dc,
-		struct dc_writeback_info *wb_info,
-		struct dc_state *context);
-void dcn30_disable_writeback(
-		struct dc *dc,
-		unsigned int dwb_pipe_inst);
-
-bool dcn30_mmhubbub_warmup(
-	struct dc *dc,
-	unsigned int num_dwb,
-	struct dc_writeback_info *wb_info);
-
-bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
-		const struct dc_plane_state *plane_state);
-
-bool dcn30_set_input_transfer_func(struct dc *dc,
-				struct pipe_ctx *pipe_ctx,
-				const struct dc_plane_state *plane_state);
-bool dcn30_set_output_transfer_func(struct dc *dc,
-				struct pipe_ctx *pipe_ctx,
-				const struct dc_stream_state *stream);
-void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
-void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
-void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
-
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
-		struct dc_cursor_attributes *cursor_attr);
-
-bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
-
-void dcn30_hardware_release(struct dc *dc);
-
-void dcn30_set_disp_pattern_generator(const struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		enum controller_dp_test_pattern test_pattern,
-		enum controller_dp_color_space color_space,
-		enum dc_color_depth color_depth,
-		const struct tg_color *solid_color,
-		int width, int height, int offset);
-
-void dcn30_set_hubp_blank(const struct dc *dc,
-		struct pipe_ctx *pipe_ctx,
-		bool blank_enable);
-
-void dcn30_prepare_bandwidth(struct dc *dc,
-	struct dc_state *context);
-
-void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx,
-		int num_pipes, const struct dc_static_screen_params *params);
-
-#endif /* __DC_HWSS_DCN30_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index 0de8b2783..9894caedf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -23,16 +23,16 @@
  *
  */
 
-#include "dce110/dce110_hw_sequencer.h"
-#include "dcn10/dcn10_hw_sequencer.h"
+#include "dce110/dce110_hwseq.h"
+#include "dcn10/dcn10_hwseq.h"
 #include "dcn20/dcn20_hwseq.h"
 #include "dcn21/dcn21_hwseq.h"
-#include "dcn30_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
 
 #include "dcn30_init.h"
 
 static const struct hw_sequencer_funcs dcn30_funcs = {
-	.program_gamut_remap = dcn10_program_gamut_remap,
+	.program_gamut_remap = dcn30_program_gamut_remap,
 	.init_hw = dcn30_init_hw,
 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 	.apply_ctx_for_surface = NULL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 6cf40c133..d1500b223 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -278,22 +278,10 @@ static void mpc3_program_ogam_pwl(
 {
 	uint32_t i;
 	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);
-	uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
-	uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
-	uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
-
-	/*the entries of DCN3AG gamma LUTs take 18bit base values as opposed to
-	 *38 base+delta values per entry in earlier DCN architectures
-	 *last base value for our lut is compute by adding the last base value
-	 *in our data + last delta
-	 */
 
 	if (is_rgb_equal(rgb,  num)) {
 		for (i = 0 ; i < num; i++)
 			REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
-
-		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red);
-
 	} else {
 
 		REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],
@@ -302,8 +290,6 @@ static void mpc3_program_ogam_pwl(
 		for (i = 0 ; i < num; i++)
 			REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg);
 
-		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red);
-
 		REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
 
 		REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],
@@ -312,8 +298,6 @@ static void mpc3_program_ogam_pwl(
 		for (i = 0 ; i < num; i++)
 			REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg);
 
-		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_green);
-
 		REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
 
 		REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id],
@@ -322,7 +306,6 @@ static void mpc3_program_ogam_pwl(
 		for (i = 0 ; i < num; i++)
 			REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg);
 
-		REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_blue);
 	}
 
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
index c8a3a6a96..5198f2167 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
@@ -779,7 +779,6 @@
 	type MPCC_MCM_1DLUT_LUT_DATA;\
 	type MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK;\
 	type MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL;\
-	type MPCC_MCM_1DLUT_LUT_READ_DBG;\
 	type MPCC_MCM_1DLUT_LUT_HOST_SEL;\
 	type MPCC_MCM_1DLUT_LUT_CONFIG_MODE;\
 	type MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index 5bf4d0aa6..b97bdb868 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -207,7 +207,7 @@ void optc3_set_odm_bypass(struct timing_generator *optc,
 			);
 
 	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
-	REG_SET(OTG_H_TIMING_CNTL, 0,
+	REG_UPDATE(OTG_H_TIMING_CNTL,
 			OTG_H_TIMING_DIV_MODE, h_div);
 
 	REG_SET(OPTC_MEMORY_CONFIG, 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 88c0b24a3..7b259cb5f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -44,7 +44,7 @@
 #include "dcn30/dcn30_optc.h"
 #include "dcn20/dcn20_hwseq.h"
 #include "dcn30/dcn30_hwseq.h"
-#include "dce110/dce110_hw_sequencer.h"
+#include "dce110/dce110_hwseq.h"
 #include "dcn30/dcn30_opp.h"
 #include "dcn20/dcn20_dsc.h"
 #include "dcn30/dcn30_vpg.h"
@@ -91,6 +91,8 @@
 #include "amdgpu_socbb.h"
 #include "dc_dmub_srv.h"
 
+#define DC_LOGGER \
+	dc->ctx->logger
 #define DC_LOGGER_INIT(logger)
 
 enum dcn30_clk_src_array_id {
@@ -727,6 +729,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.use_max_lb = true,
 	.exit_idle_opt_for_cursor_updates = true,
 	.enable_legacy_fast_update = false,
+	.using_dml2 = false,
 };
 
 static const struct dc_panel_config panel_config_defaults = {
@@ -2217,6 +2220,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = {
 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
+	.release_pipe = dcn20_release_pipe,
 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,