diff options
author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
---|---|---|
committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-05-18 17:39:57 +0000 |
commit | dc50eab76b709d68175a358d6e23a5a3890764d3 (patch) | |
tree | c754d0390db060af0213ff994f0ac310e4cfd6e9 /drivers/gpu/drm/amd/display/dc/inc | |
parent | Adding debian version 6.6.15-2. (diff) | |
download | linux-dc50eab76b709d68175a358d6e23a5a3890764d3.tar.xz linux-dc50eab76b709d68175a358d6e23a5a3890764d3.zip |
Merging upstream version 6.7.7.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_types.h | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 23 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/optc.h | 219 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h | 54 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 482 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 184 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/resource.h | 285 |
15 files changed, 601 insertions, 735 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index eaad1260bf..bc9cda3294 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -38,6 +38,7 @@ #include "mcif_wb.h" #include "panel_cntl.h" #include "dmub/inc/dmub_cmd.h" +#include "pg_cntl.h" #define MAX_CLOCK_SOURCES 7 #define MAX_SVP_PHANTOM_STREAMS 2 @@ -132,6 +133,16 @@ struct resource_funcs { const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe); + struct pipe_ctx *(*acquire_free_pipe_as_secondary_opp_head)( + const struct dc_state *cur_ctx, + struct dc_state *new_ctx, + const struct resource_pool *pool, + const struct pipe_ctx *otg_master); + + void (*release_pipe)(struct dc_state *context, + struct pipe_ctx *pipe, + const struct resource_pool *pool); + enum dc_status (*validate_plane)( const struct dc_plane_state *plane_state, struct dc_caps *caps); @@ -194,6 +205,7 @@ struct resource_funcs { void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); + void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); }; struct audio_support{ @@ -275,6 +287,7 @@ struct resource_pool { struct audio_support audio_support; struct dccg *dccg; + struct pg_cntl *pg_cntl; struct irq_service *irqs; struct abm *abm; @@ -296,6 +309,16 @@ struct dcn_fe_bandwidth { }; +/* Parameters needed to call set_disp_pattern_generator */ +struct test_pattern_params { + enum controller_dp_test_pattern test_pattern; + enum controller_dp_color_space color_space; + enum dc_color_depth color_depth; + int width; + int height; + int offset; +}; + struct stream_resource { struct output_pixel_processor *opp; struct display_stream_compressor *dsc; @@ -312,6 +335,8 @@ struct stream_resource { * otherwise it's using group number 'gsl_group-1' */ uint8_t gsl_group; + + struct test_pattern_params test_pattern_params; }; struct plane_resource { @@ -355,6 +380,7 @@ union pipe_update_flags { uint32_t plane_changed : 1; uint32_t det_size : 1; uint32_t unbounded_req : 1; + uint32_t test_pattern_changed : 1; } bits; uint32_t raw; }; @@ -409,6 +435,8 @@ struct pipe_ctx { union pipe_update_flags update_flags; struct tg_color visual_confirm_color; bool has_vactive_margin; + /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ + uint8_t subvp_index; }; /* Data used for dynamic link encoder assignment. @@ -434,6 +462,8 @@ struct resource_context { unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; bool is_mpc_3dlut_acquired[MAX_PIPES]; + /* solely used for build scalar data in dml2 */ + struct pipe_ctx temp_pipe; }; struct dce_bw_output { @@ -477,6 +507,7 @@ union bw_output { struct bw_context { union bw_output bw; struct display_mode_lib dml; + struct dml2_context *dml2; }; struct dc_dmub_cmd { @@ -549,6 +580,17 @@ struct dc_state { struct { unsigned int stutter_period_us; } perf_params; + + struct { + /* used to temporarily backup plane states of a stream during + * dc update. The reason is that plane states are overwritten + * with surface updates in dc update. Once they are overwritten + * current state is no longer valid. We want to temporarily + * store current value in plane states so we can still recover + * a valid current state during dc update. + */ + struct dc_plane_state plane_states[MAX_SURFACE_NUM]; + } scratch; }; struct replay_context { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index ecb7bcc394..55ded5fb8a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -45,11 +45,12 @@ struct dcn3_clk_internal { int dummy; - /*TODO: +// TODO: uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK1_CLK4_CURRENT_CNT; uint32_t CLK1_CLK3_DS_CNTL; //dcf_deep_sleep_divider uint32_t CLK1_CLK3_ALLOW_DS; //dcf_deep_sleep_allow @@ -57,7 +58,8 @@ struct dcn3_clk_internal { uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass - */ + + uint32_t CLK4_CLK0_CURRENT_CNT; //fclk }; struct dcn301_clk_internal { @@ -258,6 +260,10 @@ struct clk_mgr_funcs { int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr); void (*set_low_power_state)(struct clk_mgr *clk_mgr); + void (*exit_low_power_state)(struct clk_mgr *clk_mgr); + bool (*is_ips_supported)(struct clk_mgr *clk_mgr); + void (*set_idle_state)(struct clk_mgr *clk_mgr, bool allow_idle); + uint32_t (*get_idle_state)(struct clk_mgr *clk_mgr); void (*init_clocks)(struct clk_mgr *clk_mgr); @@ -308,6 +314,7 @@ struct clk_mgr { bool force_smu_not_present; bool dc_mode_softmax_enabled; int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes + int dp_dto_source_clock_in_khz; // Used to program DP DTO with ss adjustment on DCN314 int dentist_vco_freq_khz; struct clk_state_registers_and_bypass boot_snapshot; struct clk_bw_params *bw_params; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index cff5fd55a0..6f4c97543c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -73,7 +73,7 @@ enum dentist_divider_range { clk_mgr->base.ctx #define DC_LOGGER \ - clk_mgr->base.ctx->logger + dc->ctx->logger @@ -163,7 +163,13 @@ enum dentist_divider_range { CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \ CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \ CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \ - CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL) + CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL), \ + CLK_SR_DCN32(CLK1_CLK0_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK1_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK2_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK3_CURRENT_CNT), \ + CLK_SR_DCN32(CLK1_CLK4_CURRENT_CNT), \ + CLK_SR_DCN32(CLK4_CLK0_CURRENT_CNT) #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \ CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\ @@ -222,6 +228,8 @@ struct clk_mgr_registers { uint32_t CLK4_CLK2_CURRENT_CNT; uint32_t CLK4_CLK_PLL_REQ; + uint32_t CLK4_CLK0_CURRENT_CNT; + uint32_t CLK3_CLK2_DFS_CNTL; uint32_t CLK3_CLK_PLL_REQ; @@ -235,6 +243,12 @@ struct clk_mgr_registers { uint32_t CLK1_CLK3_DFS_CNTL; uint32_t CLK1_CLK4_DFS_CNTL; + uint32_t CLK1_CLK0_CURRENT_CNT; + uint32_t CLK1_CLK1_CURRENT_CNT; + uint32_t CLK1_CLK2_CURRENT_CNT; + uint32_t CLK1_CLK3_CURRENT_CNT; + uint32_t CLK1_CLK4_CURRENT_CNT; + uint32_t CLK0_CLK0_DFS_CNTL; uint32_t CLK0_CLK1_DFS_CNTL; uint32_t CLK0_CLK3_DFS_CNTL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 3e2f0f64c9..6b44557fcb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -56,6 +56,13 @@ enum dentist_dispclk_change_mode { DISPCLK_CHANGE_MODE_RAMPING, }; +struct dp_dto_params { + int otg_inst; + enum signal_type signal; + long long pixclk_hz; + long long refclk_hz; +}; + enum pixel_rate_div { PIXEL_RATE_DIV_BY_1 = 0, PIXEL_RATE_DIV_BY_2 = 1, @@ -134,6 +141,11 @@ struct dccg_funcs { enum physymclk_clock_source clk_src, bool force_enable); + void (*set_physymclk_root_clock_gating)( + struct dccg *dccg, + int phy_inst, + bool enable); + void (*set_dtbclk_dto)( struct dccg *dccg, const struct dtbclk_dto_params *params); @@ -182,6 +194,17 @@ struct dccg_funcs { struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); + void (*set_dp_dto)( + struct dccg *dccg, + const struct dp_dto_params *params); + void (*set_dtbclk_p_src)( + struct dccg *dccg, + enum streamclk_source src, + uint32_t otg_inst); + void (*set_dto_dscclk)( + struct dccg *dccg, + uint32_t dsc_inst); + void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); }; #endif //__DAL_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index f5677dbb4e..901891316d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -188,11 +188,13 @@ struct hubbub_funcs { * compressed or detiled buffers. */ void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte); + void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst); void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase); void (*init_crb)(struct hubbub *hubbub); void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow); void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); void (*dchubbub_init)(struct hubbub *hubbub); + void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h index d7b8d586b5..4b27f29d0d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h @@ -76,6 +76,8 @@ union dsc_enc_slice_caps { uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */ uint8_t NUM_SLICES_4 : 1; uint8_t NUM_SLICES_8 : 1; + uint8_t NUM_SLICES_12 : 1; + uint8_t NUM_SLICES_16 : 1; } bits; uint8_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 8d86159d9d..61a2406dcc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -91,6 +91,12 @@ enum mpcc_alpha_blend_mode { * @global_gain: used when blend mode considers both pixel alpha and plane * alpha value and assumes the global alpha value. * @global_alpha: plane alpha value + * @overlap_only: whether overlapping of different planes is allowed + * @bottom_gain_mode: blend mode for bottom gain setting + * @background_color_bpc: background color for bpc + * @top_gain: top gain setting + * @bottom_inside_gain: blend mode for bottom inside + * @bottom_outside_gain: blend mode for bottom outside */ struct mpcc_blnd_cfg { struct tg_color black_color; /* background color */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h new file mode 100644 index 0000000000..9a8bf6ec70 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * DOC: overview + * + * Output Pipe Timing Combiner (OPTC) includes two major functional blocks: + * Output Data Mapper (ODM) and Output Timing Generator (OTG). + * + * - ODM: It is Output Data Mapping block. It can combine input data from + * multiple OPP data pipes into one single data stream or split data from one + * OPP data pipe into multiple data streams or just bypass OPP data to DIO. + * - OTG: It is Output Timing Generator. It generates display timing signals to + * drive the display output. + */ + +#ifndef __DC_OPTC_H__ +#define __DC_OPTC_H__ + +#include "timing_generator.h" + +struct optc { + struct timing_generator base; + + const struct dcn_optc_registers *tg_regs; + const struct dcn_optc_shift *tg_shift; + const struct dcn_optc_mask *tg_mask; + + int opp_count; + + uint32_t max_h_total; + uint32_t max_v_total; + + uint32_t min_h_blank; + + uint32_t min_h_sync_width; + uint32_t min_v_sync_width; + uint32_t min_v_blank; + uint32_t min_v_blank_interlace; + + int vstartup_start; + int vupdate_offset; + int vupdate_width; + int vready_offset; + struct dc_crtc_timing orginal_patched_timing; + enum signal_type signal; +}; + +struct dcn_otg_state { + uint32_t v_blank_start; + uint32_t v_blank_end; + uint32_t v_sync_a_pol; + uint32_t v_total; + uint32_t v_total_max; + uint32_t v_total_min; + uint32_t v_total_min_sel; + uint32_t v_total_max_sel; + uint32_t v_sync_a_start; + uint32_t v_sync_a_end; + uint32_t h_blank_start; + uint32_t h_blank_end; + uint32_t h_sync_a_start; + uint32_t h_sync_a_end; + uint32_t h_sync_a_pol; + uint32_t h_total; + uint32_t underflow_occurred_status; + uint32_t otg_enabled; + uint32_t blank_enabled; + uint32_t vertical_interrupt1_en; + uint32_t vertical_interrupt1_line; + uint32_t vertical_interrupt2_en; + uint32_t vertical_interrupt2_line; +}; + +void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s); + +bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing); + +bool optc1_validate_timing(struct timing_generator *optc, + const struct dc_crtc_timing *timing); + +void optc1_program_timing(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width, + const enum signal_type signal, + bool use_vbios); + +void optc1_setup_vertical_interrupt0(struct timing_generator *optc, + uint32_t start_line, + uint32_t end_line); + +void optc1_setup_vertical_interrupt1(struct timing_generator *optc, + uint32_t start_line); + +void optc1_setup_vertical_interrupt2(struct timing_generator *optc, + uint32_t start_line); + +void optc1_program_global_sync(struct timing_generator *optc, + int vready_offset, + int vstartup_start, + int vupdate_offset, + int vupdate_width); + +bool optc1_disable_crtc(struct timing_generator *optc); + +bool optc1_is_counter_moving(struct timing_generator *optc); + +void optc1_get_position(struct timing_generator *optc, + struct crtc_position *position); + +uint32_t optc1_get_vblank_counter(struct timing_generator *optc); + +void optc1_get_crtc_scanoutpos(struct timing_generator *optc, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + +void optc1_set_early_control(struct timing_generator *optc, + uint32_t early_cntl); + +void optc1_wait_for_state(struct timing_generator *optc, + enum crtc_state state); + +void optc1_set_blank(struct timing_generator *optc, + bool enable_blanking); + +bool optc1_is_blanked(struct timing_generator *optc); + +void optc1_program_blank_color(struct timing_generator *optc, + const struct tg_color *black_color); + +bool optc1_did_triggered_reset_occur(struct timing_generator *optc); + +void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); + +void optc1_disable_reset_trigger(struct timing_generator *optc); + +void optc1_lock(struct timing_generator *optc); + +void optc1_unlock(struct timing_generator *optc); + +void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); + +void optc1_set_drr(struct timing_generator *optc, + const struct drr_params *params); + +void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); + +void optc1_set_static_screen_control(struct timing_generator *optc, + uint32_t event_triggers, + uint32_t num_frames); + +void optc1_program_stereo(struct timing_generator *optc, + const struct dc_crtc_timing *timing, + struct crtc_stereo_flags *flags); + +bool optc1_is_stereo_left_eye(struct timing_generator *optc); + +void optc1_clear_optc_underflow(struct timing_generator *optc); + +void optc1_tg_init(struct timing_generator *optc); + +bool optc1_is_tg_enabled(struct timing_generator *optc); + +bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); + +void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); + +void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); + +bool optc1_get_otg_active_size(struct timing_generator *optc, + uint32_t *otg_active_width, + uint32_t *otg_active_height); + +void optc1_enable_crtc_reset(struct timing_generator *optc, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); + +bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params); + +bool optc1_get_crc(struct timing_generator *optc, + uint32_t *r_cr, + uint32_t *g_y, + uint32_t *b_cb); + +bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); + +void optc1_set_vtg_params(struct timing_generator *optc, + const struct dc_crtc_timing *dc_crtc_timing, + bool program_fp2); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h index 248adc1705..660897e12a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/panel_cntl.h @@ -56,7 +56,7 @@ struct panel_cntl_funcs { struct panel_cntl_init_data { struct dc_context *ctx; uint32_t inst; - uint32_t pwrseq_inst; + uint32_t eng_id; }; struct panel_cntl { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h new file mode 100644 index 0000000000..b9812afb88 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h @@ -0,0 +1,54 @@ +/* Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_PG_CNTL_H__ +#define __DC_PG_CNTL_H__ + +#include "dc.h" +#include "dc_types.h" +#include "hw_shared.h" + +struct pg_cntl { + struct dc_context *ctx; + const struct pg_cntl_funcs *funcs; + bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; + bool pg_res_enable[PG_HW_RESOURCES_NUM_ELEMENT]; +}; + +struct pg_cntl_funcs { + void (*dsc_pg_control)(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); + void (*hubp_dpp_pg_control)(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on); + void (*hpo_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*io_clk_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*plane_otg_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on); + void (*opp_pg_control)(struct pg_cntl *pg_cntl, unsigned int opp_inst, bool power_on); + void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on); + void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on); + void (*init_pg_status)(struct pg_cntl *pg_cntl); + + void (*set_force_poweron_domain22)(struct pg_cntl *pg_cntl, bool power_on); +}; + +#endif //__DC_PG_CNTL_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index a6dedf3c7d..a15efadb91 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -226,6 +226,11 @@ struct stream_encoder_funcs { struct stream_encoder *enc, int tg_inst); + void (*dig_stream_enable)( + struct stream_encoder *enc, + enum signal_type signal, + bool enable); + void (*hdmi_reset_stream_attribute)( struct stream_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index c21e7ffd5b..9a00a99317 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -309,6 +309,7 @@ struct timing_generator_funcs { */ void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, struct dc_crtc_timing *timing); + void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); void (*set_gsl_source_select)(struct timing_generator *optc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h deleted file mode 100644 index 66e680902c..0000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HW_SEQUENCER_H__ -#define __DC_HW_SEQUENCER_H__ -#include "dc_types.h" -#include "clock_source.h" -#include "inc/hw/timing_generator.h" -#include "inc/hw/opp.h" -#include "inc/hw/link_encoder.h" -#include "core_status.h" - -struct pipe_ctx; -struct dc_state; -struct dc_stream_status; -struct dc_writeback_info; -struct dchub_init_data; -struct dc_static_screen_params; -struct resource_pool; -struct dc_phy_addr_space_config; -struct dc_virtual_addr_space_config; -struct dpp; -struct dce_hwseq; -struct link_resource; -struct dc_dmub_cmd; - -struct subvp_pipe_control_lock_fast_params { - struct dc *dc; - bool lock; - struct pipe_ctx *pipe_ctx; -}; - -struct pipe_control_lock_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; - bool lock; -}; - -struct set_flip_control_gsl_params { - struct pipe_ctx *pipe_ctx; - bool flip_immediate; -}; - -struct program_triplebuffer_params { - const struct dc *dc; - struct pipe_ctx *pipe_ctx; - bool enableTripleBuffer; -}; - -struct update_plane_addr_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; -}; - -struct set_input_transfer_func_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; - struct dc_plane_state *plane_state; -}; - -struct program_gamut_remap_params { - struct pipe_ctx *pipe_ctx; -}; - -struct program_manual_trigger_params { - struct pipe_ctx *pipe_ctx; -}; - -struct send_dmcub_cmd_params { - struct dc_context *ctx; - union dmub_rb_cmd *cmd; - enum dm_dmub_wait_type wait_type; -}; - -struct setup_dpp_params { - struct pipe_ctx *pipe_ctx; -}; - -struct program_bias_and_scale_params { - struct pipe_ctx *pipe_ctx; -}; - -struct set_output_transfer_func_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; - const struct dc_stream_state *stream; -}; - -struct update_visual_confirm_params { - struct dc *dc; - struct pipe_ctx *pipe_ctx; - int mpcc_id; -}; - -struct power_on_mpc_mem_pwr_params { - struct mpc *mpc; - int mpcc_id; - bool power_on; -}; - -struct set_output_csc_params { - struct mpc *mpc; - int opp_id; - const uint16_t *regval; - enum mpc_output_csc_mode ocsc_mode; -}; - -struct set_ocsc_default_params { - struct mpc *mpc; - int opp_id; - enum dc_color_space color_space; - enum mpc_output_csc_mode ocsc_mode; -}; - -union block_sequence_params { - struct update_plane_addr_params update_plane_addr_params; - struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; - struct pipe_control_lock_params pipe_control_lock_params; - struct set_flip_control_gsl_params set_flip_control_gsl_params; - struct program_triplebuffer_params program_triplebuffer_params; - struct set_input_transfer_func_params set_input_transfer_func_params; - struct program_gamut_remap_params program_gamut_remap_params; - struct program_manual_trigger_params program_manual_trigger_params; - struct send_dmcub_cmd_params send_dmcub_cmd_params; - struct setup_dpp_params setup_dpp_params; - struct program_bias_and_scale_params program_bias_and_scale_params; - struct set_output_transfer_func_params set_output_transfer_func_params; - struct update_visual_confirm_params update_visual_confirm_params; - struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; - struct set_output_csc_params set_output_csc_params; - struct set_ocsc_default_params set_ocsc_default_params; -}; - -enum block_sequence_func { - DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, - OPTC_PIPE_CONTROL_LOCK, - HUBP_SET_FLIP_CONTROL_GSL, - HUBP_PROGRAM_TRIPLEBUFFER, - HUBP_UPDATE_PLANE_ADDR, - DPP_SET_INPUT_TRANSFER_FUNC, - DPP_PROGRAM_GAMUT_REMAP, - OPTC_PROGRAM_MANUAL_TRIGGER, - DMUB_SEND_DMCUB_CMD, - DPP_SETUP_DPP, - DPP_PROGRAM_BIAS_AND_SCALE, - DPP_SET_OUTPUT_TRANSFER_FUNC, - MPC_UPDATE_VISUAL_CONFIRM, - MPC_POWER_ON_MPC_MEM_PWR, - MPC_SET_OUTPUT_CSC, - MPC_SET_OCSC_DEFAULT, -}; - -struct block_sequence { - union block_sequence_params params; - enum block_sequence_func func; -}; - -struct hw_sequencer_funcs { - void (*hardware_release)(struct dc *dc); - /* Embedded Display Related */ - void (*edp_power_control)(struct dc_link *link, bool enable); - void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); - void (*edp_wait_for_T12)(struct dc_link *link); - - /* Pipe Programming Related */ - void (*init_hw)(struct dc *dc); - void (*power_down_on_boot)(struct dc *dc); - void (*enable_accelerated_mode)(struct dc *dc, - struct dc_state *context); - enum dc_status (*apply_ctx_to_hw)(struct dc *dc, - struct dc_state *context); - void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); - void (*apply_ctx_for_surface)(struct dc *dc, - const struct dc_stream_state *stream, - int num_planes, struct dc_state *context); - void (*program_front_end_for_ctx)(struct dc *dc, - struct dc_state *context); - void (*wait_for_pending_cleared)(struct dc *dc, - struct dc_state *context); - void (*post_unlock_program_front_end)(struct dc *dc, - struct dc_state *context); - void (*update_plane_addr)(const struct dc *dc, - struct pipe_ctx *pipe_ctx); - void (*update_dchub)(struct dce_hwseq *hws, - struct dchub_init_data *dh_data); - void (*wait_for_mpcc_disconnect)(struct dc *dc, - struct resource_pool *res_pool, - struct pipe_ctx *pipe_ctx); - void (*edp_backlight_control)( - struct dc_link *link, - bool enable); - void (*program_triplebuffer)(const struct dc *dc, - struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); - void (*update_pending_status)(struct pipe_ctx *pipe_ctx); - void (*power_down)(struct dc *dc); - void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); - - /* Pipe Lock Related */ - void (*pipe_control_lock)(struct dc *dc, - struct pipe_ctx *pipe, bool lock); - void (*interdependent_update_lock)(struct dc *dc, - struct dc_state *context, bool lock); - void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, - bool flip_immediate); - void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); - - /* Timing Related */ - void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, - struct crtc_position *position); - int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); - void (*calc_vupdate_position)( - struct dc *dc, - struct pipe_ctx *pipe_ctx, - uint32_t *start_line, - uint32_t *end_line); - void (*enable_per_frame_crtc_position_reset)(struct dc *dc, - int group_size, struct pipe_ctx *grouped_pipes[]); - void (*enable_timing_synchronization)(struct dc *dc, - int group_index, int group_size, - struct pipe_ctx *grouped_pipes[]); - void (*enable_vblanks_synchronization)(struct dc *dc, - int group_index, int group_size, - struct pipe_ctx *grouped_pipes[]); - void (*setup_periodic_interrupt)(struct dc *dc, - struct pipe_ctx *pipe_ctx); - void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, - struct dc_crtc_timing_adjust adjust); - void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, - int num_pipes, - const struct dc_static_screen_params *events); -#ifndef TRIM_FSFT - bool (*optimize_timing_for_fsft)(struct dc *dc, - struct dc_crtc_timing *timing, - unsigned int max_input_rate_in_khz); -#endif - - /* Stream Related */ - void (*enable_stream)(struct pipe_ctx *pipe_ctx); - void (*disable_stream)(struct pipe_ctx *pipe_ctx); - void (*blank_stream)(struct pipe_ctx *pipe_ctx); - void (*unblank_stream)(struct pipe_ctx *pipe_ctx, - struct dc_link_settings *link_settings); - - /* Bandwidth Related */ - void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); - bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); - void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); - - /* Infopacket Related */ - void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); - void (*send_immediate_sdp_message)( - struct pipe_ctx *pipe_ctx, - const uint8_t *custom_sdp_message, - unsigned int sdp_message_size); - void (*update_info_frame)(struct pipe_ctx *pipe_ctx); - void (*set_dmdata_attributes)(struct pipe_ctx *pipe); - void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); - bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); - - /* Cursor Related */ - void (*set_cursor_position)(struct pipe_ctx *pipe); - void (*set_cursor_attribute)(struct pipe_ctx *pipe); - void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); - - /* Colour Related */ - void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); - void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, - enum dc_color_space colorspace, - uint16_t *matrix, int opp_id); - - /* VM Related */ - int (*init_sys_ctx)(struct dce_hwseq *hws, - struct dc *dc, - struct dc_phy_addr_space_config *pa_config); - void (*init_vm_ctx)(struct dce_hwseq *hws, - struct dc *dc, - struct dc_virtual_addr_space_config *va_config, - int vmid); - - /* Writeback Related */ - void (*update_writeback)(struct dc *dc, - struct dc_writeback_info *wb_info, - struct dc_state *context); - void (*enable_writeback)(struct dc *dc, - struct dc_writeback_info *wb_info, - struct dc_state *context); - void (*disable_writeback)(struct dc *dc, - unsigned int dwb_pipe_inst); - - bool (*mmhubbub_warmup)(struct dc *dc, - unsigned int num_dwb, - struct dc_writeback_info *wb_info); - - /* Clock Related */ - enum dc_status (*set_clock)(struct dc *dc, - enum dc_clock_type clock_type, - uint32_t clk_khz, uint32_t stepping); - void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, - struct dc_clock_config *clock_cfg); - void (*optimize_pwr_state)(const struct dc *dc, - struct dc_state *context); - void (*exit_optimized_pwr_state)(const struct dc *dc, - struct dc_state *context); - - /* Audio Related */ - void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); - void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); - - /* Stereo 3D Related */ - void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); - - /* HW State Logging Related */ - void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); - void (*get_hw_state)(struct dc *dc, char *pBuf, - unsigned int bufSize, unsigned int mask); - void (*clear_status_bits)(struct dc *dc, unsigned int mask); - - bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp); - - void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); - - void (*set_pipe)(struct pipe_ctx *pipe_ctx); - - void (*enable_dp_link_output)(struct dc_link *link, - const struct link_resource *link_res, - enum signal_type signal, - enum clock_source_id clock_source, - const struct dc_link_settings *link_settings); - void (*enable_tmds_link_output)(struct dc_link *link, - const struct link_resource *link_res, - enum signal_type signal, - enum clock_source_id clock_source, - enum dc_color_depth color_depth, - uint32_t pixel_clock); - void (*enable_lvds_link_output)(struct dc_link *link, - const struct link_resource *link_res, - enum clock_source_id clock_source, - uint32_t pixel_clock); - void (*disable_link_output)(struct dc_link *link, - const struct link_resource *link_res, - enum signal_type signal); - - void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); - - /* Idle Optimization Related */ - bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); - - bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane, - struct dc_cursor_attributes *cursor_attr); - - bool (*is_abm_supported)(struct dc *dc, - struct dc_state *context, struct dc_stream_state *stream); - - void (*set_disp_pattern_generator)(const struct dc *dc, - struct pipe_ctx *pipe_ctx, - enum controller_dp_test_pattern test_pattern, - enum controller_dp_color_space color_space, - enum dc_color_depth color_depth, - const struct tg_color *solid_color, - int width, int height, int offset); - - void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); - void (*z10_restore)(const struct dc *dc); - void (*z10_save_init)(struct dc *dc); - - void (*blank_phantom)(struct dc *dc, - struct timing_generator *tg, - int width, - int height); - - void (*update_visual_confirm_color)(struct dc *dc, - struct pipe_ctx *pipe_ctx, - int mpcc_id); - - void (*update_phantom_vp_position)(struct dc *dc, - struct dc_state *context, - struct pipe_ctx *phantom_pipe); - void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); - bool (*is_pipe_topology_transition_seamless)(struct dc *dc, - const struct dc_state *cur_ctx, - const struct dc_state *new_ctx); - - void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); - void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); - void (*subvp_pipe_control_lock)(struct dc *dc, - struct dc_state *context, - bool lock, - bool should_lock_all_pipes, - struct pipe_ctx *top_pipe_to_program, - bool subvp_prev_use); - -}; - -void color_space_to_black_color( - const struct dc *dc, - enum dc_color_space colorspace, - struct tg_color *black_color); - -bool hwss_wait_for_blank_complete( - struct timing_generator *tg); - -const uint16_t *find_color_matrix( - enum dc_color_space color_space, - uint32_t *array_size); - -void get_surface_visual_confirm_color( - const struct pipe_ctx *pipe_ctx, - struct tg_color *color); - -void get_subvp_visual_confirm_color( - struct dc *dc, - struct dc_state *context, - struct pipe_ctx *pipe_ctx, - struct tg_color *color); - -void get_hdr_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color); -void get_mpctree_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color); -void get_surface_tile_visual_confirm_color( - struct pipe_ctx *pipe_ctx, - struct tg_color *color); - -void get_mclk_switch_visual_confirm_color( - struct dc *dc, - struct dc_state *context, - struct pipe_ctx *pipe_ctx, - struct tg_color *color); - -void hwss_execute_sequence(struct dc *dc, - struct block_sequence block_sequence[], - int num_steps); - -void hwss_build_fast_sequence(struct dc *dc, - struct dc_dmub_cmd *dc_dmub_cmd, - unsigned int dmub_cmd_count, - struct block_sequence block_sequence[], - int *num_steps, - struct pipe_ctx *pipe_ctx); - -void hwss_send_dmcub_cmd(union block_sequence_params *params); - -void hwss_program_manual_trigger(union block_sequence_params *params); - -void hwss_setup_dpp(union block_sequence_params *params); - -void hwss_program_bias_and_scale(union block_sequence_params *params); - -void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); - -void hwss_set_output_csc(union block_sequence_params *params); - -void hwss_set_ocsc_default(union block_sequence_params *params); - -#endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h deleted file mode 100644 index 4ca4192c1e..0000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_HW_SEQUENCER_PRIVATE_H__ -#define __DC_HW_SEQUENCER_PRIVATE_H__ - -#include "dc_types.h" - -enum pipe_gating_control { - PIPE_GATING_CONTROL_DISABLE = 0, - PIPE_GATING_CONTROL_ENABLE, - PIPE_GATING_CONTROL_INIT -}; - -struct dce_hwseq_wa { - bool blnd_crtc_trigger; - bool DEGVIDCN10_253; - bool false_optc_underflow; - bool DEGVIDCN10_254; - bool DEGVIDCN21; - bool disallow_self_refresh_during_multi_plane_transition; - bool dp_hpo_and_otg_sequence; - bool wait_hubpret_read_start_during_mpo_transition; -}; - -struct hwseq_wa_state { - bool DEGVIDCN10_253_applied; - bool disallow_self_refresh_during_multi_plane_transition_applied; - unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame; -}; - -struct pipe_ctx; -struct dc_state; -struct dc_stream_status; -struct dc_writeback_info; -struct dchub_init_data; -struct dc_static_screen_params; -struct resource_pool; -struct resource_context; -struct stream_resource; -struct dc_phy_addr_space_config; -struct dc_virtual_addr_space_config; -struct hubp; -struct dpp; -struct dce_hwseq; -struct timing_generator; -struct tg_color; -struct output_pixel_processor; -struct mpcc_blnd_cfg; - -struct hwseq_private_funcs { - - void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*init_pipes)(struct dc *dc, struct dc_state *context); - void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context); - void (*update_plane_addr)(const struct dc *dc, - struct pipe_ctx *pipe_ctx); - void (*plane_atomic_disconnect)(struct dc *dc, - struct pipe_ctx *pipe_ctx); - void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx); - bool (*set_input_transfer_func)(struct dc *dc, - struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state); - bool (*set_output_transfer_func)(struct dc *dc, - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream); - void (*power_down)(struct dc *dc); - void (*enable_display_pipe_clock_gating)(struct dc_context *ctx, - bool clock_gating); - bool (*enable_display_power_gating)(struct dc *dc, - uint8_t controller_id, - struct dc_bios *dcb, - enum pipe_gating_control power_gating); - void (*blank_pixel_data)(struct dc *dc, - struct pipe_ctx *pipe_ctx, - bool blank); - enum dc_status (*enable_stream_timing)( - struct pipe_ctx *pipe_ctx, - struct dc_state *context, - struct dc *dc); - void (*edp_backlight_control)(struct dc_link *link, - bool enable); - void (*setup_vupdate_interrupt)(struct dc *dc, - struct pipe_ctx *pipe_ctx); - bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*init_blank)(struct dc *dc, struct timing_generator *tg); - void (*disable_vga)(struct dce_hwseq *hws); - void (*bios_golden_init)(struct dc *dc); - void (*plane_atomic_power_down)(struct dc *dc, - struct dpp *dpp, - struct hubp *hubp); - void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*enable_power_gating_plane)(struct dce_hwseq *hws, - bool enable); - void (*dpp_root_clock_control)( - struct dce_hwseq *hws, - unsigned int dpp_inst, - bool clock_on); - void (*dpp_pg_control)(struct dce_hwseq *hws, - unsigned int dpp_inst, - bool power_on); - void (*hubp_pg_control)(struct dce_hwseq *hws, - unsigned int hubp_inst, - bool power_on); - void (*dsc_pg_control)(struct dce_hwseq *hws, - unsigned int dsc_inst, - bool power_on); - bool (*dsc_pg_status)(struct dce_hwseq *hws, - unsigned int dsc_inst); - void (*update_odm)(struct dc *dc, struct dc_state *context, - struct pipe_ctx *pipe_ctx); - void (*program_all_writeback_pipes_in_tree)(struct dc *dc, - const struct dc_stream_state *stream, - struct dc_state *context); - bool (*s0i3_golden_init_wa)(struct dc *dc); - void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx); - void (*verify_allow_pstate_change_high)(struct dc *dc); - void (*program_pipe)(struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_state *context); - bool (*wait_for_blank_complete)(struct output_pixel_processor *opp); - void (*dccg_init)(struct dce_hwseq *hws); - bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state); - bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state); - bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state); - void (*PLAT_58856_wa)(struct dc_state *context, - struct pipe_ctx *pipe_ctx); - void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); -#ifdef CONFIG_DRM_AMD_DC_FP - void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); - void (*update_force_pstate)(struct dc *dc, struct dc_state *context); - void (*update_mall_sel)(struct dc *dc, struct dc_state *context); - unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx, - unsigned int *k1_div, - unsigned int *k2_div); - void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx); - void (*resync_fifo_dccg_dio)(struct dce_hwseq *hws, struct dc *dc, - struct dc_state *context); - bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx); -#endif -}; - -struct dce_hwseq { - struct dc_context *ctx; - const struct dce_hwseq_registers *regs; - const struct dce_hwseq_shift *shifts; - const struct dce_hwseq_mask *masks; - struct dce_hwseq_wa wa; - struct hwseq_wa_state wa_state; - struct hwseq_private_funcs funcs; - - PHYSICAL_ADDRESS_LOC fb_base; - PHYSICAL_ADDRESS_LOC fb_top; - PHYSICAL_ADDRESS_LOC fb_offset; - PHYSICAL_ADDRESS_LOC uma_top; -}; - -#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index e546b9c506..06ca8bfb91 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,6 +103,10 @@ enum dc_status resource_map_pool_resources( struct dc_state *context, struct dc_stream_state *stream); +void resource_build_test_pattern_params( + struct resource_context *res_ctx, + struct pipe_ctx *pipe_ctx); + bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( @@ -213,6 +217,21 @@ bool resource_attach_surfaces_to_context( * | | | | | * | 5 | (FREE) | | | * |________|_______________|___________|_____________| + * + * The following is a quick reference of the class relation: + * + * DC state ---1--------0..N--- streams + * + * stream ---1-----------1--- OTG Master pipe + * + * OTG Master pipe ---1--------1..N--- OPP Head pipes + * + * OPP Head pipe ---1--------0..N--- DPP pipes + * + * stream ---1--------0..N--- Planes + * + * Plane ---1--------1..N--- DPP pipes + * */ enum pipe_type { /* free pipe - free pipe is an uninitialized pipe without a stream @@ -223,8 +242,8 @@ enum pipe_type { /* OTG master pipe - the master pipe of its OPP head pipes with a * functional OTG. It merges all its OPP head pipes pixel data in ODM - * block and output to backend DIG. OTG master pipe is responsible for - * generating entire crtc timing to backend DIG. An OTG master pipe may + * block and output to back end DIG. OTG master pipe is responsible for + * generating entire CRTC timing to back end DIG. An OTG master pipe may * or may not have a plane. If it has a plane it blends it as the left * most MPC slice of the top most layer. If it doesn't have a plane it * can output pixel data from its OPP head pipes' test pattern @@ -252,33 +271,210 @@ enum pipe_type { }; /* - * Determine if the input pipe ctx is of a pipe type. - * return - true if pipe ctx is of the input type. + * Determine if the input pipe_ctx is of a pipe type. + * return - true if pipe_ctx is of the input type. */ bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type); /* - * Determine if the input pipe ctx is used for rendering a plane with MPCC - * combine. MPCC combine is a hardware feature to combine multiple DPP pipes - * into a single plane. It is typically used for bypassing pipe bandwidth - * limitation for rendering a very large plane or saving power by reducing UCLK - * and DPPCLK speeds. + * Acquire a pipe as OTG master pipe and allocate pipe resources required to + * enable stream output. + */ +enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx, + const struct resource_pool *pool, + struct dc_stream_state *stream); + +/* + * Release pipe resources and the OTG master pipe associated with the stream + * The stream must have all planes removed and ODM/MPC slice counts are reset + * to 1 before invoking this interface. + */ +void resource_remove_otg_master_for_stream_output(struct dc_state *new_ctx, + const struct resource_pool *pool, + struct dc_stream_state *stream); + +/* + * Add plane to the bottom most layer in plane composition and allocate DPP pipe + * resources as needed. + * return - true if plane is added in plane composition, false otherwise. + */ +bool resource_append_dpp_pipes_for_plane_composition( + struct dc_state *new_ctx, + struct dc_state *cur_ctx, + struct resource_pool *pool, + struct pipe_ctx *otg_master_pipe, + struct dc_plane_state *plane_state); + +/* + * Add plane to the bottom most layer in plane composition and allocate DPP pipe + * resources as needed. + * return - true if plane is added in plane composition, false otherwise. + */ +void resource_remove_dpp_pipes_for_plane_composition( + struct dc_state *context, + const struct resource_pool *pool, + const struct dc_plane_state *plane_state); + +/* + * Update ODM slice count by acquiring or releasing pipes. If new slices need + * to be added, it is going to add them to the last ODM index. If existing + * slices need to be removed, it is going to remove them from the last ODM + * index. * - * For instance in the Inter-pipe Relation diagram shown below, both PIPE 0 and - * 1 are for MPCC combine for plane 0 + * return - true if ODM slices are updated and required pipes are acquired. All + * affected pipe parameters are updated. * - * Inter-pipe Relation - * __________________________________________________ - * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER | - * | | plane 0 | | | - * | 0 | -------------MPC----------------------- | - * | | plane 0 | | | | - * | 1 | ------------- | | | - * |________|_______________|___________|_____________| + * false if resource fails to complete this update. The function is not designed + * to recover the creation of invalid topologies. Returning false is typically + * an indication of insufficient validation in caller's stack. new_ctx will be + * invalid. Caller may attempt to restore new_ctx by calling this function + * again with original slice count. + */ +bool resource_update_pipes_for_stream_with_slice_count( + struct dc_state *new_ctx, + const struct dc_state *cur_ctx, + const struct resource_pool *pool, + const struct dc_stream_state *stream, + int new_slice_count); + +/* + * Update MPC slice count by acquiring or releasing DPP pipes. If new slices + * need to be added it is going to add to the last MPC index. If existing + * slices need to be removed, it is going to remove them from the last MPC + * index. + * + * @dpp_pipe - top most dpp pipe for MPCC combine. + * + * return - true if MPC slices are updated and required pipes are acquired. All + * affected pipe parameters are updated. + * + * false if resource fails to complete this update. The function is not designed + * to recover the creation of invalid topologies. Returning false is typically + * an indication of insufficient validation in caller's stack. new_ctx will be + * invalid. Caller may attempt to restore new_ctx by calling this function + * again with original slice count. + */ +bool resource_update_pipes_for_plane_with_slice_count( + struct dc_state *new_ctx, + const struct dc_state *cur_ctx, + const struct resource_pool *pool, + const struct dc_plane_state *plane, + int slice_count); + +/* + * Get the OTG master pipe in resource context associated with the stream. + * return - NULL if not found. Otherwise the OTG master pipe associated with the + * stream. + */ +struct pipe_ctx *resource_get_otg_master_for_stream( + struct resource_context *res_ctx, + const struct dc_stream_state *stream); + +/* + * Get an array of OPP heads in opp_heads ordered with index low to high for OTG + * master pipe in res_ctx. + * return - number of OPP heads in the array. If otg_master passed in is not + * an OTG master, the function returns 0. + */ +int resource_get_opp_heads_for_otg_master(const struct pipe_ctx *otg_master, + struct resource_context *res_ctx, + struct pipe_ctx *opp_heads[MAX_PIPES]); + +/* + * Get an array of DPP pipes in dpp_pipes ordered with index low to high for OPP + * head pipe in res_ctx. + * return - number of DPP pipes in the array. If opp_head passed in is not + * an OPP pipe, the function returns 0. + */ +int resource_get_dpp_pipes_for_opp_head(const struct pipe_ctx *opp_head, + struct resource_context *res_ctx, + struct pipe_ctx *dpp_pipes[MAX_PIPES]); + +/* + * Get an array of DPP pipes in dpp_pipes ordered with index low to high for + * plane in res_ctx. + * return - number of DPP pipes in the array. + */ +int resource_get_dpp_pipes_for_plane(const struct dc_plane_state *plane, + struct resource_context *res_ctx, + struct pipe_ctx *dpp_pipes[MAX_PIPES]); + +/* + * Get the OTG master pipe for the input pipe context. + * return - the OTG master pipe for the input pipe + * context. + */ +struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx); + +/* + * Get the OPP head pipe for the input pipe context. + * return - the OPP head pipe for the input pipe + * context. + */ +struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx); + +/* + * Get the DPP pipe allocated for MPC slice 0 and ODM slice 0 of the plane + * associated with dpp_pipe. + */ +struct pipe_ctx *resource_get_primary_dpp_pipe(const struct pipe_ctx *dpp_pipe); + +/* + * Get the MPC slice index counting from 0 from left most slice + * For example, if a DPP pipe is used as a secondary pipe in MPCC combine, MPC + * split index is greater than 0. + */ +int resource_get_mpc_slice_index(const struct pipe_ctx *dpp_pipe); + +/* + * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice + * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it + * will have 4 pieces of slice. + * return - 0 if pipe is not used for a plane with MPCC combine. otherwise + * the number of MPC "cuts" for the plane. + */ +int resource_get_mpc_slice_count(const struct pipe_ctx *opp_head); + +/* + * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice + * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it + * will have 4 pieces of slice. + * return - 0 if pipe is not used for ODM combine. otherwise + * the number of ODM "cuts" for the timing. + */ +int resource_get_odm_slice_count(const struct pipe_ctx *otg_master); + +/* Get the ODM slice index counting from 0 from left most slice */ +int resource_get_odm_slice_index(const struct pipe_ctx *opp_head); + +/* determine if pipe topology is changed between state a and state b */ +bool resource_is_pipe_topology_changed(const struct dc_state *state_a, + const struct dc_state *state_b); + +/* + * determine if the two OTG master pipes have the same ODM topology + * return + * false - if pipes passed in are not OTG masters or ODM topology is + * changed. + * true - otherwise + */ +bool resource_is_odm_topology_changed(const struct pipe_ctx *otg_master_a, + const struct pipe_ctx *otg_master_b); + +/* log the pipe topology update in state */ +void resource_log_pipe_topology_update(struct dc *dc, struct dc_state *state); + +/* + * Look for a free pipe in new resource context that is used as a secondary OPP + * head by cur_otg_master. * - * return - true if pipe ctx is used for mpcc combine. + * return - FREE_PIPE_INDEX_NOT_FOUND if free pipe is not found, otherwise + * pipe idx of the free pipe */ -bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx); +int resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master( + const struct resource_context *cur_res_ctx, + struct resource_context *new_res_ctx, + const struct pipe_ctx *cur_otg_master); /* * Look for a free pipe in new resource context that is used as a secondary DPP @@ -333,48 +529,6 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy( const struct resource_pool *pool, const struct pipe_ctx *primary_pipe); -/* - * Get number of MPC "cuts" of the plane associated with the pipe. MPC slice - * count is equal to MPC splits + 1. For example if a plane is cut 3 times, it - * will have 4 pieces of slice. - * return - 0 if pipe is not used for a plane with MPCC combine. otherwise - * the number of MPC "cuts" for the plane. - */ -int resource_get_num_mpc_splits(const struct pipe_ctx *pipe); - -/* - * Get number of ODM "cuts" of the timing associated with the pipe. ODM slice - * count is equal to ODM splits + 1. For example if a timing is cut 3 times, it - * will have 4 pieces of slice. - * return - 0 if pipe is not used for ODM combine. otherwise - * the number of ODM "cuts" for the timing. - */ -int resource_get_num_odm_splits(const struct pipe_ctx *pipe); - -/* - * Get the OTG master pipe in resource context associated with the stream. - * return - NULL if not found. Otherwise the OTG master pipe associated with the - * stream. - */ -struct pipe_ctx *resource_get_otg_master_for_stream( - struct resource_context *res_ctx, - struct dc_stream_state *stream); - -/* - * Get the OTG master pipe for the input pipe context. - * return - the OTG master pipe for the input pipe - * context. - */ -struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx); - -/* - * Get the OPP head pipe for the input pipe context. - * return - the OPP head pipe for the input pipe - * context. - */ -struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx); - - bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, @@ -439,7 +593,7 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link, bool is_h_timing_divisible_by_2(struct dc_stream_state *stream); -bool dc_resource_acquire_secondary_pipe_for_mpc_odm( +bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy( const struct dc *dc, struct dc_state *state, struct pipe_ctx *pri_pipe, @@ -454,4 +608,7 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm( enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); + +bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream); + #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ |