Adding upstream version 6.9.7.upstream/6.9.7

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

1 files changed, 51 insertions, 209 deletions

diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index 51c320a2e5..fbc27930e5 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -3,50 +3,27 @@
 
 /* Autogenerated file, DO NOT EDIT manually!
 
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml                     (    594 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml        (   1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml                (  91929 bytes, from 2023-02-28 23:52:27)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml       (  15434 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml          (  74995 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml                (  84231 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml                ( 113474 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml                ( 149590 bytes, from 2023-02-14 19:37:12)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml                ( 198949 bytes, from 2023-03-20 18:06:23)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml            (  11404 bytes, from 2023-03-10 18:32:53)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml               (   1773 bytes, from 2022-08-02 16:38:43)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml (   9055 bytes, from 2023-03-10 18:32:52)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml    (   2976 bytes, from 2023-03-10 18:32:52)
-
-Copyright (C) 2013-2023 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml (  15434 bytes, from Fri Jun  2 14:59:26 2023)
 */
 
+#ifdef __KERNEL__
+#include <linux/bug.h>
+#define assert(x) BUG_ON(!(x))
+#else
+#include <assert.h>
+#endif
+
+#ifdef __cplusplus
+#define __struct_cast(X)
+#else
+#define __struct_cast(X) (struct X)
+#endif
 
 enum chip {
 	A2XX = 2,
@@ -141,11 +118,13 @@ enum a3xx_rop_code {
 	ROP_COPY_INVERTED = 3,
 	ROP_AND_REVERSE = 4,
 	ROP_INVERT = 5,
+	ROP_XOR = 6,
 	ROP_NAND = 7,
 	ROP_AND = 8,
 	ROP_EQUIV = 9,
 	ROP_NOOP = 10,
 	ROP_OR_INVERTED = 11,
+	ROP_COPY = 12,
 	ROP_OR_REVERSE = 13,
 	ROP_OR = 14,
 	ROP_SET = 15,
@@ -258,7 +237,8 @@ static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT			2
 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
 {
-	return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
+	assert(!(val & 0x3));
+	return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
 }
 
 #define REG_AXXX_CP_RB_RPTR					0x000001c4
@@ -471,174 +451,34 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
 #define REG_AXXX_CP_IB2_BUFSZ					0x0000045b
 
 #define REG_AXXX_CP_STAT					0x0000047f
-#define AXXX_CP_STAT_CP_BUSY__MASK				0x80000000
-#define AXXX_CP_STAT_CP_BUSY__SHIFT				31
-static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK			0x40000000
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT			30
-static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK			0x20000000
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT			29
-static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK			0x10000000
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT			28
-static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK			0x08000000
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT			27
-static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK;
-}
-#define AXXX_CP_STAT_ME_BUSY__MASK				0x04000000
-#define AXXX_CP_STAT_ME_BUSY__SHIFT				26
-static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK			0x02000000
-#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT			25
-static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CP_3D_BUSY__MASK				0x00800000
-#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT				23
-static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CP_NRT_BUSY__MASK				0x00400000
-#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT				22
-static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK			0x00200000
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT			21
-static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK				0x00100000
-#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT			20
-static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK			0x00080000
-#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT			19
-static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK			0x00040000
-#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT			18
-static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK;
-}
-#define AXXX_CP_STAT_PFP_BUSY__MASK				0x00020000
-#define AXXX_CP_STAT_PFP_BUSY__SHIFT				17
-static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK;
-}
-#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK			0x00010000
-#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT			16
-static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK			0x00002000
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT		13
-static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK			0x00001000
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT		12
-static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK			0x00000800
-#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT			11
-static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_BUSY__MASK				0x00000400
-#define AXXX_CP_STAT_CSF_BUSY__SHIFT				10
-static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_ST_BUSY__MASK				0x00000200
-#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT				9
-static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK;
-}
-#define AXXX_CP_STAT_EVENT_BUSY__MASK				0x00000100
-#define AXXX_CP_STAT_EVENT_BUSY__SHIFT				8
-static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK			0x00000080
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT			7
-static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK			0x00000040
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT			6
-static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK;
-}
-#define AXXX_CP_STAT_CSF_RING_BUSY__MASK			0x00000020
-#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT			5
-static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RCIU_BUSY__MASK				0x00000010
-#define AXXX_CP_STAT_RCIU_BUSY__SHIFT				4
-static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK;
-}
-#define AXXX_CP_STAT_RBIU_BUSY__MASK				0x00000008
-#define AXXX_CP_STAT_RBIU_BUSY__SHIFT				3
-static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK			0x00000004
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT			2
-static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK;
-}
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK			0x00000002
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT			1
-static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
-{
-	return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK;
-}
+#define AXXX_CP_STAT_CP_BUSY					0x80000000
+#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY				0x40000000
+#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY				0x20000000
+#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY				0x10000000
+#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY				0x08000000
+#define AXXX_CP_STAT_ME_BUSY					0x04000000
+#define AXXX_CP_STAT_MIU_WR_C_BUSY				0x02000000
+#define AXXX_CP_STAT_CP_3D_BUSY					0x00800000
+#define AXXX_CP_STAT_CP_NRT_BUSY				0x00400000
+#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY				0x00200000
+#define AXXX_CP_STAT_RCIU_ME_BUSY				0x00100000
+#define AXXX_CP_STAT_RCIU_PFP_BUSY				0x00080000
+#define AXXX_CP_STAT_MEQ_RING_BUSY				0x00040000
+#define AXXX_CP_STAT_PFP_BUSY					0x00020000
+#define AXXX_CP_STAT_ST_QUEUE_BUSY				0x00010000
+#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY			0x00002000
+#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY			0x00001000
+#define AXXX_CP_STAT_RING_QUEUE_BUSY				0x00000800
+#define AXXX_CP_STAT_CSF_BUSY					0x00000400
+#define AXXX_CP_STAT_CSF_ST_BUSY				0x00000200
+#define AXXX_CP_STAT_EVENT_BUSY					0x00000100
+#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY				0x00000080
+#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY				0x00000040
+#define AXXX_CP_STAT_CSF_RING_BUSY				0x00000020
+#define AXXX_CP_STAT_RCIU_BUSY					0x00000010
+#define AXXX_CP_STAT_RBIU_BUSY					0x00000008
+#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY				0x00000004
+#define AXXX_CP_STAT_MIU_RD_REQ_BUSY				0x00000002
 #define AXXX_CP_STAT_MIU_WR_BUSY				0x00000001
 
 #define REG_AXXX_CP_SCRATCH_REG0				0x00000578
@@ -693,5 +533,7 @@ static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
 
 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA			0x00000614
 
+#ifdef __cplusplus
+#endif
 
 #endif /* ADRENO_COMMON_XML */