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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Universal Flash Storage (UFS) Controller
+
+maintainers:
+ - Li Wei <liwei213@huawei.com>
+
+# Select only our matches, not all jedec,ufs
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - hisilicon,hi3660-ufs
+ - hisilicon,hi3670-ufs
+ required:
+ - compatible
+
+allOf:
+ - $ref: ufs-common.yaml
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: hisilicon,hi3660-ufs
+ - const: jedec,ufs-1.1
+ - items:
+ - enum:
+ - hisilicon,hi3670-ufs
+ - const: jedec,ufs-2.1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: phy_clk
+
+ reg:
+ items:
+ - description: UFS register address space
+ - description: UFS SYS CTRL register address space
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: rst
+
+required:
+ - compatible
+ - reg
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/hi3670-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ufs@ff3c0000 {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ reg = <0x0 0xff3c0000 0x0 0x1000>,
+ <0x0 0xff3e0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>,
+ <0 0>;
+
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+ };