diff options
Diffstat (limited to 'arch/arm/boot')
214 files changed, 4784 insertions, 836 deletions
diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index eebb5a0c87..2d26c3397f 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -256,6 +256,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ + sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi index 4ef26d8f53..a5b1f1e390 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi @@ -338,6 +338,8 @@ resets = <&ccu RST_BUS_VE>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; allwinner,sram = <&ve_sram 1>; + interconnects = <&mbus 4>; + interconnect-names = "dma-mem"; }; mmc0: mmc@1c0f000 { diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts new file mode 100644 index 0000000000..f34dfdf156 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include "sun8i-v3s.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Anbernic RG Nano"; + compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; + + aliases { + rtc0 = &pcf8563; + rtc1 = &rtc; + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; + default-brightness-level = <11>; + power-supply = <®_vcc5v0>; + pwms = <&pwm 0 40000 1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + button-a { + gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + + button-b { + gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + + button-down { + gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-left { + gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-se { + gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-SELECT"; + linux,code = <BTN_SELECT>; + }; + + button-st { + gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-START"; + linux,code = <BTN_START>; + }; + + button-tl { + gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-L"; + linux,code = <BTN_TL>; + }; + + button-tr { + gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-R"; + linux,code = <BTN_TR>; + }; + + button-up { + gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + + button-y { + gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + }; +}; + +&codec { + allwinner,audio-routing = "Speaker", "HP", + "MIC1", "Mic", + "Mic", "HBIAS"; + allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ + vcc-supply = <®_vcc3v3>; + }; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +#include "axp209.dtsi" + +&battery_power_supply { + status = "okay"; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + spi0_no_miso_pins: spi0-no-miso-pins { + pins = "PC1", "PC2", "PC3"; + function = "spi0"; + }; +}; + +&pwm { + pinctrl-0 = <&pwm0_pin>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ +®_dcdc2 { + regulator-always-on; + regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1250000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 wired into every 3.3v input that isn't the RTC. */ +®_dcdc3 { + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */ +®_ldo1 { + regulator-always-on; + regulator-name = "vcc-rtc"; +}; + +/* LDO2 wired into VCC-PLL and audio codec. */ +®_ldo2 { + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc-pll"; +}; + +/* LDO3, LDO4, and LDO5 unused. */ +®_ldo3 { + status = "disabled"; +}; + +®_ldo4 { + status = "disabled"; +}; + +/* RTC uses internal oscillator */ +&rtc { + /delete-property/ clocks; +}; + +&spi0 { + pinctrl-0 = <&spi0_no_miso_pins>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; + reg = <0>; + backlight = <&backlight>; + dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ + reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + spi-max-frequency = <100000000>; + + height-mm = <39>; + width-mm = <39>; + + /* Set hb-porch to compensate for non-visible area */ + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <80>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index 3b9a282c27..e8a04476b7 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -319,6 +319,29 @@ #phy-cells = <1>; }; + ehci: usb@1c1a000 { + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci: usb@1c1a400 { + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-v3s-ccu"; reg = <0x01c20000 0x400>; @@ -414,6 +437,18 @@ bias-pull-up; }; + /omit-if-no-ref/ + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + /omit-if-no-ref/ + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; + spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 23cbc7203a..d3ac20e316 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-fuji.dtb \ aspeed-bmc-facebook-galaxy100.dtb \ aspeed-bmc-facebook-greatlakes.dtb \ + aspeed-bmc-facebook-minerva-cmc.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts index 0a51d2e32f..8ab5f301f9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts @@ -760,49 +760,63 @@ &gpio { gpio-line-names = - /*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","", - /*B0-B7*/ "BMC_SELECT_EEPROM","","","", - "POWER_BUTTON","","","", + /*A0-A7*/ "","","","host0-special-boot","","","","", + /*B0-B7*/ "i2c-backup-sel","","","", + "power-button","presence-cpu0","","", /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", - "S1_DDR_SAVE","","", - /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", - "","", - /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", - /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", - "","","","","", - /*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","", - "","","","", + /*F0-F7*/ "ps0-pgood","ps1-pgood","power-chassis-control","s0-ddr-save", + "power-chassis-good", "s1-ddr-save","","", + /*G0-G7*/ "host0-ready","host0-shd-req-n","host0-shd-ack-n", + "s0-overtemp-n","","","","", + /*H0-H7*/ "uart1-mode1","uart2-mode1","uart3-mode1","uart4-mode1", + "ps0-vin-good","ps1-vin-good","","i2c6-reset-n", + /*I0-I7*/ "presence-ps0","presence-ps1","s1-special-boot","","","","","", + /*J0-J7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", + "host0-reboot-ack-n","","","","", /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","", - /*M0-M7*/ "","","","","","","","", + /*L0-L7*/ "","","","host0-sysreset-n","s0-spi-auth-fail-n","","","", + /*M0-M7*/ "","","","","s0-i2c9-alert-n","s1-i2c9-alert-n","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","UID_BUTTON","","", - /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", - "OCP_MAIN_PWREN","RESET_BUTTON","","", - /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", + /*Q0-Q7*/ "","","","","","identify-button","led-identify","", + /*R0-R7*/ "","","ext-hightemp-n","","ocp-main-pwren","reset-button","","", + /*S0-S7*/ "s0-vr-hot-n","s1-vr-hot-n","","", + "rtc-battery-voltage-read-enable","vr-pmbus-sel-n","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", /*W0-W7*/ "","","","","","","","", /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","", - "S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","", + /*Y0-Y7*/ "","","","bmc-vga-en-n","","","","", + /*Z0-Z7*/ "s0-plimit","s1-fault-alert","s1-fw-boot-ok","s0-rtc-lock","", + "s1-sys-auth-failure-n","s1-overtemp-n","", /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR", - "S1_BMC_DDR_ADR","","","","", - /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", - "BMC_OCP_PG"; + /*AB0-AB7*/ "s1-hightemp-n","s1-plimit","s0-ddr-addr","s1-ddr-addr","","", + "","", + /*AC0-AC7*/ "sys-pwr-gd","","spi0-program-sel","spi0-backup-sel","bmc-ok", + "","presence-cpu1","ocp-pgood"; i2c4-o-en-hog { gpio-hog; gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; output-high; - line-name = "BMC_I2C4_O_EN"; + line-name = "i2c4-o-en"; + }; + + ocp-aux-pwren-hog { + gpio-hog; + gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ocp-aux-pwren"; + }; + + bmc-ready { + gpio-hog; + gpios = <ASPEED_GPIO(AC, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "bmc-ready"; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts index 0715cb9ab3..7b540880ce 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts @@ -14,6 +14,42 @@ aliases { serial7 = &uart8; serial8 = &uart9; + + /* + * I2C NVMe alias port + */ + i2c100 = &backplane_0; + i2c48 = &nvmeslot_0; + i2c49 = &nvmeslot_1; + i2c50 = &nvmeslot_2; + i2c51 = &nvmeslot_3; + i2c52 = &nvmeslot_4; + i2c53 = &nvmeslot_5; + i2c54 = &nvmeslot_6; + i2c55 = &nvmeslot_7; + + i2c101 = &backplane_1; + i2c56 = &nvmeslot_8; + i2c57 = &nvmeslot_9; + i2c58 = &nvmeslot_10; + i2c59 = &nvmeslot_11; + i2c60 = &nvmeslot_12; + i2c61 = &nvmeslot_13; + i2c62 = &nvmeslot_14; + i2c63 = &nvmeslot_15; + + i2c102 = &backplane_2; + i2c64 = &nvmeslot_16; + i2c65 = &nvmeslot_17; + i2c66 = &nvmeslot_18; + i2c67 = &nvmeslot_19; + i2c68 = &nvmeslot_20; + i2c69 = &nvmeslot_21; + i2c70 = &nvmeslot_22; + i2c71 = &nvmeslot_23; + + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; }; chosen { @@ -497,6 +533,11 @@ &i2c8 { status = "okay"; + temperature-sensor@48 { + compatible = "ti,tmp112"; + reg = <0x48>; + }; + gpio@77 { compatible = "nxp,pca9539"; reg = <0x77>; @@ -516,6 +557,237 @@ &i2c9 { status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + backplane_1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; + + tmp432@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + }; + + backplane_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; + + tmp432@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + }; + + backplane_0: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; + + tmp432@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; + }; + }; }; &i2c11 { @@ -546,20 +818,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; -}; - -&adc1 { - ref_voltage = <2500>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default - &pinctrl_adc10_default &pinctrl_adc11_default - &pinctrl_adc12_default &pinctrl_adc13_default - &pinctrl_adc14_default &pinctrl_adc15_default>; + &pinctrl_adc2_default>; }; &vhub { @@ -575,16 +834,17 @@ gpio-line-names = /*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n", /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","", - /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","", + /*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","bmc-debug-mode","", "irq-n","","vrd-sel","spd-sel", /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", "","bmc-ncsi-txen","","", - /*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","", + /*E0-E7*/ "","eth-phy-int-n","clk50m-bmc-ncsi","","","","","", /*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control", "cpu-bios-recover","s0-heartbeat","hs-csout-prochot", "s0-vr-hot-n","s1-vr-hot-n", /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","", - /*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","", + /*H0-H7*/ "jtag-program-sel","fpga-program-b","wd-disable-n", + "power-chassis-good","","","","", /*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -599,17 +859,17 @@ /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","identify-button","led-identify", - "s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1", + "s1-ddr-save","spi-nor-access","host0-ready","presence-cpu1", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", - "host0-reboot-ack-n","host0-ready","host0-shd-req-n", + "host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n", "host0-shd-ack-n","s0-overtemp-n", - /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","", + /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","s1-pcp-pgood", "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", - "s1-overtemp-n","s1-spi-auth-fail-n", + "s1-overtemp-n","cpld-s1-spi-auth-fail-n", /*Y0-Y7*/ "","","","","","","","host0-special-boot", /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index e899de681f..5be0e8fd26 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -45,8 +45,8 @@ num-chipselects = <1>; cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva-cmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva-cmc.dts new file mode 100644 index 0000000000..f04ef90635 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva-cmc.dts @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2023 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Minerva CMC"; + compatible = "facebook,minerva-cmc", "aspeed,ast2600"; + + aliases { + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial5:57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; +}; + +&uart6 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + use-ncsi; + mlx,multi-host; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&sgpiom1 { + status = "okay"; + ngpios = <128>; + bus-frequency = <2000000>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4B>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; +}; + +&i2c2 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9548"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + multi-master; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c15 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt = <2500000>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc10_default>; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index a677c827e7..5a8169bbda 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -80,8 +80,8 @@ gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; num-chipselects = <1>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts index d47ce4edc6..cad1b9aac9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts @@ -34,6 +34,11 @@ #size-cells = <1>; ranges; + event_log: tcg_event_log@b3d00000 { + no-map; + reg = <0xb3d00000 0x100000>; + }; + ramoops@b3e00000 { compatible = "ramoops"; reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ @@ -454,8 +459,9 @@ status = "okay"; tpm@2e { - compatible = "nuvoton,npct75x"; + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; reg = <0x2e>; + memory-region = <&event_log>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts index 3f6010ef2b..213023bc5a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-tacoma.dts @@ -456,7 +456,7 @@ status = "okay"; tpm: tpm@2e { - compatible = "tcg,tpm-tis-i2c"; + compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; reg = <0x2e>; }; }; diff --git a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi index 31590d3186..00e5887c92 100644 --- a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi @@ -35,8 +35,8 @@ gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; - tpmdev@0 { - compatible = "tcg,tpm_tis-spi"; + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <33000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi index 88fda18af1..d0d5f7e52a 100644 --- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -14,6 +14,13 @@ #address-cells = <1>; #size-cells = <1>; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + chipcommon-a-bus@18000000 { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x00001000>; @@ -320,6 +327,29 @@ #address-cells = <1>; }; + mdio-mux@18003000 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&mdio>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x18003000 0x4>; + mux-mask = <0x200>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_phy: usb3-phy@10 { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x10>; + usb3-dmp-syscon = <&usb3_dmp>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + rng: rng@18004000 { compatible = "brcm,bcm5301x-rng"; reg = <0x18004000 0x14>; @@ -460,6 +490,10 @@ brcm,nand-has-wp; }; + usb3_dmp: syscon@18105000 { + reg = <0x18105000 0x1000>; + }; + thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts index 4f44cb4df7..59400217f8 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts @@ -25,6 +25,12 @@ <0x88000000 0x08000000>; }; + nvram@1c080000 { + et1macaddr: et1macaddr { + #nvmem-cell-cells = <1>; + }; + }; + leds { compatible = "gpio-leds"; @@ -62,6 +68,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et1macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &usb3_phy { status = "okay"; }; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts index 99253fd7ad..2ba5adf2b7 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts @@ -47,3 +47,41 @@ &usb3_phy { status = "okay"; }; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan1"; + }; + + port@1 { + label = "lan2"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan4"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + status = "disabled"; + }; + + port@7 { + status = "disabled"; + }; + + port@8 { + label = "cpu"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts index 55fc9f44cb..127ca87412 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts @@ -229,10 +229,20 @@ port@5 { status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; port@7 { status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; port@8 { diff --git a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts index e6d2698786..c5099defe9 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts @@ -25,6 +25,15 @@ <0x88000000 0x08000000>; }; + nvram@1e3f0000 { + compatible = "brcm,nvram"; + reg = <0x1e3f0000 0x10000>; + + et2macaddr: et2macaddr { + #nvmem-cell-cells = <1>; + }; + }; + nand_controller: nand-controller@18028000 { nand@0 { partitions { @@ -112,6 +121,11 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&gmac0 { + nvmem-cells = <&et2macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + &spi_nor { status = "okay"; }; @@ -142,6 +156,8 @@ port@4 { label = "wan"; + nvmem-cells = <&et2macaddr 3>; + nvmem-cell-names = "mac-address"; }; port@5 { diff --git a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi index 600a1b54f2..f06a178a92 100644 --- a/arch/arm/boot/dts/broadcom/bcm5301x.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm5301x.dtsi @@ -26,13 +26,6 @@ }; }; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - clocks { #address-cells = <1>; #size-cells = <1>; @@ -69,33 +62,6 @@ }; }; - mdio-mux@18003000 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x18003000 0x4>; - mux-mask = <0x200>; - - mdio@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - usb3_phy: usb3-phy@10 { - compatible = "brcm,ns-ax-usb3-phy"; - reg = <0x10>; - usb3-dmp-syscon = <&usb3_dmp>; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb3_dmp: syscon@18105000 { - reg = <0x18105000 0x1000>; - }; - i2c0: i2c@18009000 { compatible = "brcm,iproc-i2c"; reg = <0x18009000 0x50>; diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile index 1a25ce3cf8..ab8525f1ea 100644 --- a/arch/arm/boot/dts/intel/ixp/Makefile +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp43x-gateworks-gw2358.dtb \ intel-ixp42x-netgear-wg302v1.dtb \ intel-ixp42x-arcom-vulcan.dtb \ - intel-ixp42x-gateway-7001.dtb + intel-ixp42x-gateway-7001.dtb \ + intel-ixp42x-usrobotics-usr8200.dtb diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts index b9d46eb065..fa133c9136 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts @@ -57,7 +57,7 @@ button-reset { wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts index 5a5e16cc73..73d3c11dd0 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts @@ -44,7 +44,7 @@ }; button-reset { wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts index 8da6823e1d..26f02dad6a 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts @@ -63,7 +63,7 @@ }; button-reset { wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts index da1e93212b..2eec5f63d3 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts @@ -65,7 +65,7 @@ }; button-reset { wakeup-source; - linux,code = <KEY_ESC>; + linux,code = <KEY_RESTART>; label = "reset"; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; }; @@ -101,6 +101,8 @@ flash@0,0 { compatible = "intel,ixp4xx-flash", "cfi-flash"; bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; /* * 8 MB of Flash in 0x20000 byte blocks * mapped in at CS0. diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts index 4aba9e0214..98275a363c 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts @@ -13,7 +13,7 @@ / { model = "Linksys WRV54G / Gemtek GTWX5715"; - compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x"; + compatible = "linksys,wrv54g", "intel,ixp42x"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts new file mode 100644 index 0000000000..2c89db34c8 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the USRobotics USR8200 firewall + * VPN and NAS. Based on know-how from Peter Denison. + * + * This machine is based on IXP422, the USR internal codename + * is "Jeeves". + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "USRobotics USR8200"; + compatible = "usr,usr8200", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* These are switched around */ + serial0 = &uart1; + serial1 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + ieee1394_led: led-1394 { + label = "usr8200:green:1394"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + usb1_led: led-usb1 { + label = "usr8200:green:usb1"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + usb2_led: led-usb2 { + label = "usr8200:green:usb2"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wireless_led: led-wireless { + /* + * This LED is mounted inside the case but cannot be + * seen from the outside: probably USR planned at one + * point for the device to have a wireless card, then + * changed their mind and didn't mount it, leaving the + * LED in place. + */ + label = "usr8200:green:wireless"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + pwr_led: led-pwr { + label = "usr8200:green:pwr"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + wakeup-source; + linux,code = <KEY_RESTART>; + label = "reset"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 16 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x1000000>; + + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x0fe0000 */ + fis-index-block = <0x7f>; + }; + }; + rtc@2,0 { + /* EPSON RTC7301 DG DIL-capsule */ + compatible = "epson,rtc7301dg"; + /* + * These timing settings were found in the boardfile patch: + * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN | + * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; + */ + intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase + intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase + intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase + intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase + intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase + intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle + intel,ixp4xx-eb-byte-access-on-halfword = <0>; + intel,ixp4xx-eb-mux-address-and-data = <0>; + intel,ixp4xx-eb-ahb-split-transfers = <0>; + intel,ixp4xx-eb-write-enable = <1>; + intel,ixp4xx-eb-byte-access = <1>; + /* 512 bytes at CS2 */ + reg = <2 0x00000000 0x0000200>; + reg-io-width = <1>; + native-endian; + /* FIXME: try to check if there is an IRQ for the RTC? */ + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from USR8200 boardfile from OpenWrt + * + * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16. + * We assume the same IRQ for all pins on the remaining slots, that + * is what the boardfile was doing. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 14 used for "Wireless" in the board file */ + <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ + /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */ + <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */ + /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */ + <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */ + <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */ + <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */ + }; + + gpio@c8004000 { + /* Enable clock out on GPIO 15 */ + intel,ixp4xx-gpio15-clkout; + }; + + /* EthB WAN */ + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy9>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* + * PHY 0..4 are internal to the MV88E6060 switch but appear + * as independent devices. + */ + phy0: ethernet-phy@0 { + reg = <0>; + }; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + + /* Altima AMI101L used by the WAN port */ + phy9: ethernet-phy@9 { + reg = <9>; + }; + + /* The switch uses MDIO addresses 16 thru 31 */ + switch@16 { + compatible = "marvell,mv88e6060"; + reg = <16>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-handle = <&phy0>; + }; + + port@1 { + reg = <1>; + label = "lan2"; + phy-handle = <&phy1>; + }; + + port@2 { + reg = <2>; + label = "lan3"; + phy-handle = <&phy2>; + }; + + port@3 { + reg = <3>; + label = "lan4"; + phy-handle = <&phy3>; + }; + + port@5 { + /* Port 5 is the CPU port according to the MV88E6060 datasheet */ + reg = <5>; + phy-mode = "rgmii-id"; + ethernet = <ðc>; + label = "cpu"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; + }; + + /* EthC LAN connected to the Marvell DSA Switch */ + ethc: ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/marvell/armada-370-rd.dts b/arch/arm/boot/dts/marvell/armada-370-rd.dts index b459a670f6..1b241da11e 100644 --- a/arch/arm/boot/dts/marvell/armada-370-rd.dts +++ b/arch/arm/boot/dts/marvell/armada-370-rd.dts @@ -149,39 +149,37 @@ }; }; - switch: switch@10 { + switch: ethernet-switch@10 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x10>; interrupt-controller; #interrupt-cells = <2>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan0"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan1"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan3"; }; - port@5 { + ethernet-port@5 { reg = <5>; ethernet = <ð1>; phy-mode = "rgmii-id"; @@ -196,25 +194,25 @@ #address-cells = <1>; #size-cells = <0>; - switchphy0: switchphy@0 { + switchphy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&switch>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy1: switchphy@1 { + switchphy1: ethernet-phy@1 { reg = <1>; interrupt-parent = <&switch>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy2: switchphy@2 { + switchphy2: ethernet-phy@2 { reg = <2>; interrupt-parent = <&switch>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; - switchphy3: switchphy@3 { + switchphy3: ethernet-phy@3 { reg = <3>; interrupt-parent = <&switch>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts index f4c4b213ef..5baf83e525 100644 --- a/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts @@ -77,51 +77,49 @@ pinctrl-0 = <&mdio_pins>; status = "okay"; - switch@0 { + ethernet-switch@0 { compatible = "marvell,mv88e6190"; - #address-cells = <1>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&switch_interrupt_pins>; pinctrl-names = "default"; - #size-cells = <0>; reg = <0>; mdio { #address-cells = <1>; #size-cells = <0>; - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg = <0x1>; }; - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg = <0x2>; }; - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg = <0x3>; }; - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg = <0x4>; }; - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg = <0x5>; }; - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg = <0x6>; }; - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg = <0x7>; }; - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg = <0x8>; }; }; @@ -142,11 +140,11 @@ }; }; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { ethernet = <ð0>; phy-mode = "rgmii"; reg = <0>; @@ -158,55 +156,55 @@ }; }; - port@1 { + ethernet-port@1 { label = "lan1"; phy-handle = <&switch0phy1>; reg = <1>; }; - port@2 { + ethernet-port@2 { label = "lan2"; phy-handle = <&switch0phy2>; reg = <2>; }; - port@3 { + ethernet-port@3 { label = "lan3"; phy-handle = <&switch0phy3>; reg = <3>; }; - port@4 { + ethernet-port@4 { label = "lan4"; phy-handle = <&switch0phy4>; reg = <4>; }; - port@5 { + ethernet-port@5 { label = "lan5"; phy-handle = <&switch0phy5>; reg = <5>; }; - port@6 { + ethernet-port@6 { label = "lan6"; phy-handle = <&switch0phy6>; reg = <6>; }; - port@7 { + ethernet-port@7 { label = "lan7"; phy-handle = <&switch0phy7>; reg = <7>; }; - port@8 { + ethernet-port@8 { label = "lan8"; phy-handle = <&switch0phy8>; reg = <8>; }; - port@9 { + ethernet-port@9 { /* 88X3310P external phy */ label = "lan9"; phy-handle = <&phy1>; @@ -214,7 +212,7 @@ reg = <9>; }; - port@a { + ethernet-port@a { /* 88X3310P external phy */ label = "lan10"; phy-handle = <&phy2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts index 1990f7d0cc..1707d1b015 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts @@ -7,66 +7,66 @@ }; &mdio { - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible = "marvell,mv88e6190"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cf_gtr_switch_reset_pins>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan8"; phy-handle = <&switch0phy0>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan7"; phy-handle = <&switch0phy1>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan6"; phy-handle = <&switch0phy2>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "lan5"; phy-handle = <&switch0phy3>; }; - port@5 { + ethernet-port@5 { reg = <5>; label = "lan4"; phy-handle = <&switch0phy4>; }; - port@6 { + ethernet-port@6 { reg = <6>; label = "lan3"; phy-handle = <&switch0phy5>; }; - port@7 { + ethernet-port@7 { reg = <7>; label = "lan2"; phy-handle = <&switch0phy6>; }; - port@8 { + ethernet-port@8 { reg = <8>; label = "lan1"; phy-handle = <&switch0phy7>; }; - port@10 { + ethernet-port@10 { reg = <10>; phy-mode = "2500base-x"; @@ -83,35 +83,35 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: switch0phy0@1 { + switch0phy0: ethernet-phy@1 { reg = <0x1>; }; - switch0phy1: switch0phy1@2 { + switch0phy1: ethernet-phy@2 { reg = <0x2>; }; - switch0phy2: switch0phy2@3 { + switch0phy2: ethernet-phy@3 { reg = <0x3>; }; - switch0phy3: switch0phy3@4 { + switch0phy3: ethernet-phy@4 { reg = <0x4>; }; - switch0phy4: switch0phy4@5 { + switch0phy4: ethernet-phy@5 { reg = <0x5>; }; - switch0phy5: switch0phy5@6 { + switch0phy5: ethernet-phy@6 { reg = <0x6>; }; - switch0phy6: switch0phy6@7 { + switch0phy6: ethernet-phy@7 { reg = <0x7>; }; - switch0phy7: switch0phy7@8 { + switch0phy7: ethernet-phy@8 { reg = <0x8>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts index b795ad5738..a7678a784c 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts @@ -11,42 +11,42 @@ }; &mdio { - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible = "marvell,mv88e6085"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&cf_gtr_switch_reset_pins>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan2"; phy-handle = <&switch0phy0>; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan1"; phy-handle = <&switch0phy1>; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan4"; phy-handle = <&switch0phy2>; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "lan3"; phy-handle = <&switch0phy3>; }; - port@5 { + ethernet-port@5 { reg = <5>; phy-mode = "2500base-x"; ethernet = <ð1>; @@ -63,19 +63,19 @@ #address-cells = <1>; #size-cells = <0>; - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg = <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg = <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg = <0x13>; }; - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg = <0x14>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi index fc8216fd9f..4116ed60f7 100644 --- a/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-linksys.dtsi @@ -158,42 +158,40 @@ &mdio { status = "okay"; - switch@0 { + ethernet-switch@0 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan4"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan3"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan1"; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "wan"; }; - port@5 { + ethernet-port@5 { reg = <5>; phy-mode = "sgmii"; ethernet = <ð2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 2d8d319bec..7b755bb4e4 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -435,12 +435,10 @@ }; /* Switch MV88E6176 at address 0x10 */ - switch@10 { + ethernet-switch@10 { pinctrl-names = "default"; pinctrl-0 = <&swint_pins>; compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; dsa,member = <0 0>; reg = <0x10>; @@ -448,36 +446,36 @@ interrupt-parent = <&gpio1>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - ports@0 { + ethernet-port@0 { reg = <0>; label = "lan0"; }; - ports@1 { + ethernet-port@1 { reg = <1>; label = "lan1"; }; - ports@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; }; - ports@3 { + ethernet-port@3 { reg = <3>; label = "lan3"; }; - ports@4 { + ethernet-port@4 { reg = <4>; label = "lan4"; }; - ports@5 { + ethernet-port@5 { reg = <5>; ethernet = <ð1>; phy-mode = "rgmii-id"; @@ -488,7 +486,7 @@ }; }; - ports@6 { + ethernet-port@6 { reg = <6>; ethernet = <ð0>; phy-mode = "rgmii-id"; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts index 32c569df14..3290ccad23 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog.dts @@ -92,44 +92,42 @@ &mdio { status = "okay"; - switch@4 { + ethernet-switch@4 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <4>; pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; pinctrl-names = "default"; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan5"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan4"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan3"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan2"; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "lan1"; }; - port@5 { + ethernet-port@5 { reg = <5>; ethernet = <ð1>; phy-mode = "1000base-x"; @@ -140,7 +138,7 @@ }; }; - port@6 { + ethernet-port@6 { /* 88E1512 external phy */ reg = <6>; label = "lan6"; diff --git a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts index 7a0614fd0c..ea859f7ea0 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts @@ -265,42 +265,40 @@ &mdio { status = "okay"; - switch@0 { + ethernet-switch@0 { compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - ports { + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + ethernet-port@0 { reg = <0>; label = "lan4"; }; - port@1 { + ethernet-port@1 { reg = <1>; label = "lan3"; }; - port@2 { + ethernet-port@2 { reg = <2>; label = "lan2"; }; - port@3 { + ethernet-port@3 { reg = <3>; label = "lan1"; }; - port@4 { + ethernet-port@4 { reg = <4>; label = "internet"; }; - port@5 { + ethernet-port@5 { reg = <5>; phy-mode = "rgmii-id"; ethernet = <ð0>; diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts index d1535f385f..9c7325f189 100644 --- a/arch/arm/boot/dts/mediatek/mt2701-evb.dts +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts @@ -244,7 +244,7 @@ &usb2 { status = "okay"; usb-role-switch; - connector{ + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; type = "micro"; id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi index 7fda40ab5f..c230c86511 100644 --- a/arch/arm/boot/dts/mediatek/mt6323.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi @@ -21,10 +21,10 @@ status = "disabled"; }; - mt6323regulator: mt6323regulator{ + mt6323regulator: mt6323regulator { compatible = "mediatek,mt6323-regulator"; - mt6323_vproc_reg: buck_vproc{ + mt6323_vproc_reg: buck_vproc { regulator-name = "vproc"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -33,7 +33,7 @@ regulator-boot-on; }; - mt6323_vsys_reg: buck_vsys{ + mt6323_vsys_reg: buck_vsys { regulator-name = "vsys"; regulator-min-microvolt = <1400000>; regulator-max-microvolt = <2987500>; @@ -42,13 +42,13 @@ regulator-boot-on; }; - mt6323_vpa_reg: buck_vpa{ + mt6323_vpa_reg: buck_vpa { regulator-name = "vpa"; regulator-min-microvolt = < 500000>; regulator-max-microvolt = <3650000>; }; - mt6323_vtcxo_reg: ldo_vtcxo{ + mt6323_vtcxo_reg: ldo_vtcxo { regulator-name = "vtcxo"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -57,28 +57,28 @@ regulator-boot-on; }; - mt6323_vcn28_reg: ldo_vcn28{ + mt6323_vcn28_reg: ldo_vcn28 { regulator-name = "vcn28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <185>; }; - mt6323_vcn33_bt_reg: ldo_vcn33_bt{ + mt6323_vcn33_bt_reg: ldo_vcn33_bt { regulator-name = "vcn33_bt"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; regulator-enable-ramp-delay = <185>; }; - mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{ + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi { regulator-name = "vcn33_wifi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; regulator-enable-ramp-delay = <185>; }; - mt6323_va_reg: ldo_va{ + mt6323_va_reg: ldo_va { regulator-name = "va"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -87,14 +87,14 @@ regulator-boot-on; }; - mt6323_vcama_reg: ldo_vcama{ + mt6323_vcama_reg: ldo_vcama { regulator-name = "vcama"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2800000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vio28_reg: ldo_vio28{ + mt6323_vio28_reg: ldo_vio28 { regulator-name = "vio28"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -103,7 +103,7 @@ regulator-boot-on; }; - mt6323_vusb_reg: ldo_vusb{ + mt6323_vusb_reg: ldo_vusb { regulator-name = "vusb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -111,7 +111,7 @@ regulator-boot-on; }; - mt6323_vmc_reg: ldo_vmc{ + mt6323_vmc_reg: ldo_vmc { regulator-name = "vmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -119,7 +119,7 @@ regulator-boot-on; }; - mt6323_vmch_reg: ldo_vmch{ + mt6323_vmch_reg: ldo_vmch { regulator-name = "vmch"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -127,7 +127,7 @@ regulator-boot-on; }; - mt6323_vemc3v3_reg: ldo_vemc3v3{ + mt6323_vemc3v3_reg: ldo_vemc3v3 { regulator-name = "vemc3v3"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -135,49 +135,49 @@ regulator-boot-on; }; - mt6323_vgp1_reg: ldo_vgp1{ + mt6323_vgp1_reg: ldo_vgp1 { regulator-name = "vgp1"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vgp2_reg: ldo_vgp2{ + mt6323_vgp2_reg: ldo_vgp2 { regulator-name = "vgp2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vgp3_reg: ldo_vgp3{ + mt6323_vgp3_reg: ldo_vgp3 { regulator-name = "vgp3"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vcn18_reg: ldo_vcn18{ + mt6323_vcn18_reg: ldo_vcn18 { regulator-name = "vcn18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vsim1_reg: ldo_vsim1{ + mt6323_vsim1_reg: ldo_vsim1 { regulator-name = "vsim1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vsim2_reg: ldo_vsim2{ + mt6323_vsim2_reg: ldo_vsim2 { regulator-name = "vsim2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3000000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vrtc_reg: ldo_vrtc{ + mt6323_vrtc_reg: ldo_vrtc { regulator-name = "vrtc"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -185,28 +185,28 @@ regulator-boot-on; }; - mt6323_vcamaf_reg: ldo_vcamaf{ + mt6323_vcamaf_reg: ldo_vcamaf { regulator-name = "vcamaf"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vibr_reg: ldo_vibr{ + mt6323_vibr_reg: ldo_vibr { regulator-name = "vibr"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <36>; }; - mt6323_vrf18_reg: ldo_vrf18{ + mt6323_vrf18_reg: ldo_vrf18 { regulator-name = "vrf18"; regulator-min-microvolt = <1825000>; regulator-max-microvolt = <1825000>; regulator-enable-ramp-delay = <187>; }; - mt6323_vm_reg: ldo_vm{ + mt6323_vm_reg: ldo_vm { regulator-name = "vm"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; @@ -215,7 +215,7 @@ regulator-boot-on; }; - mt6323_vio18_reg: ldo_vio18{ + mt6323_vio18_reg: ldo_vio18 { regulator-name = "vio18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -224,14 +224,14 @@ regulator-boot-on; }; - mt6323_vcamd_reg: ldo_vcamd{ + mt6323_vcamd_reg: ldo_vcamd { regulator-name = "vcamd"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <216>; }; - mt6323_vcamio_reg: ldo_vcamio{ + mt6323_vcamio_reg: ldo_vcamio { regulator-name = "vcamio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/mediatek/mt7623n.dtsi b/arch/arm/boot/dts/mediatek/mt7623n.dtsi index 3adab5cd1f..3e5cabf19c 100644 --- a/arch/arm/boot/dts/mediatek/mt7623n.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623n.dtsi @@ -116,8 +116,8 @@ "mediatek,mt2701-jpgdec"; reg = <0 0x15004000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; diff --git a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts index 84e14bee72..f24ebc2073 100644 --- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts @@ -168,7 +168,7 @@ i2c_pins: i2c-pins { mux { function = "i2c"; - groups = "i2c_0"; + groups = "i2c_0"; }; conf { diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 31e03747cd..efde9546c8 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -4,6 +4,7 @@ DTC_FLAGS_at91-sam9x60_curiosity := -@ DTC_FLAGS_at91-sam9x60ek := -@ DTC_FLAGS_at91-sama5d27_som1_ek := -@ DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ +DTC_FLAGS_at91-sama5d29_curiosity := -@ DTC_FLAGS_at91-sama5d2_icp := -@ DTC_FLAGS_at91-sama5d2_ptc_ek := -@ DTC_FLAGS_at91-sama5d2_xplained := -@ @@ -64,6 +65,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-nattis-2-natte-2.dtb \ at91-sama5d27_som1_ek.dtb \ at91-sama5d27_wlsom1_ek.dtb \ + at91-sama5d29_curiosity.dtb \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts index cb86a3a170..83372c1f29 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts @@ -439,6 +439,10 @@ status = "okay"; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc0 { bus-width = <4>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts new file mode 100644 index 0000000000..6b02b7bcfd --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d29_curiosity.dts - Device Tree file for SAMA5D29 Curiosity board + * + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Mihai Sain <mihai.sain@microchip.com> + * + */ +/dts-v1/; +#include "sama5d29.dtsi" +#include "sama5d2-pinfunc.h" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/mfd/atmel-flexcom.h> + +/ { + model = "Microchip SAMA5D29 Curiosity"; + compatible = "microchip,sama5d29-curiosity", "atmel,sama5d29", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; // debug + serial1 = &uart1; // RPi + serial2 = &uart3; // mikro BUS 2 + serial3 = &uart4; // mikro BUS 1 + serial4 = &uart6; // flx1 Bluetooth + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-1 { + label = "USER BUTTON"; + gpios = <&pioA PIN_PA17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_PROG1>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; + + led-red { + label = "red"; + gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioA PIN_PA9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x20000000>; + }; +}; + +&adc { + vddana-supply = <&vdd_3v3>; + vref-supply = <&vdd_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&flx1 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; + + uart6: serial@200 { + pinctrl-0 = <&pinctrl_flx1_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>; + status = "okay"; + + spi6: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rpi_spi>; + status = "okay"; + }; +}; + +&i2c0 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c0_default>; + pinctrl-1 = <&pinctrl_i2c0_gpio>; + sda-gpios = <&pioA PIN_PB31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PC0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-sda-hold-time-ns = <350>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddio_ddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1200000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + }; + + vdd_core: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vdd_ddr: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pioA { + pinctrl_adc_default: adc-default { + pinmux = <PIN_PD25__GPIO>, + <PIN_PD26__GPIO>; + bias-disable; + }; + + pinctrl_adtrg_default: adtrg-default { + pinmux = <PIN_PD31__ADTRG>; + bias-pull-up; + }; + + pinctrl_can0_default: can0-default { + pinmux = <PIN_PC10__CANTX0>, + <PIN_PC11__CANRX0>; + bias-disable; + }; + + pinctrl_can1_default: can1-default { + pinmux = <PIN_PC26__CANTX1>, + <PIN_PC27__CANRX1>; + bias-disable; + }; + + pinctrl_debug_uart: debug-uart { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_flx1_default: flx1-default { + pinmux = <PIN_PA24__FLEXCOM1_IO0>, + <PIN_PA23__FLEXCOM1_IO1>, + <PIN_PA25__FLEXCOM1_IO3>, + <PIN_PA26__FLEXCOM1_IO4>; + bias-disable; + }; + + pinctrl_i2c0_default: i2c0-default { + pinmux = <PIN_PB31__TWD0>, + <PIN_PC0__TWCK0>; + bias-disable; + }; + + pinctrl_i2c0_gpio: i2c0-gpio-default { + pinmux = <PIN_PB31__GPIO>, + <PIN_PC0__GPIO>; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1-default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-default { + pinmux = <PIN_PD4__GPIO>, + <PIN_PD5__GPIO>; + bias-disable; + }; + + pinctrl_key_gpio_default: key-gpio-default { + pinmux = <PIN_PA17__GPIO>; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = <PIN_PA7__GPIO>, + <PIN_PA8__GPIO>, + <PIN_PA9__GPIO>; + bias-pull-up; + }; + + pinctrl_mikrobus1_pwm: mikrobus1-pwm { + pinmux = <PIN_PA31__PWML0>; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2-pwm { + pinmux = <PIN_PB0__PWMH1>; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1-uart { + pinmux = <PIN_PB3__URXD4>, + <PIN_PB4__UTXD4>; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2-uart { + pinmux = <PIN_PB11__URXD3>, + <PIN_PB12__UTXD3>; + bias-disable; + }; + + pinctrl_qspi1_default: qspi1-default { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>, + <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-disable; + }; + + pinctrl_rpi_spi: rpi-spi { + pinmux = <PIN_PD12__FLEXCOM4_IO0>, + <PIN_PD13__FLEXCOM4_IO1>, + <PIN_PD14__FLEXCOM4_IO2>, + <PIN_PD15__FLEXCOM4_IO3>, + <PIN_PD16__FLEXCOM4_IO4>; + bias-disable; + }; + + pinctrl_rpi_uart: rpi-uart { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0-default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + + pinctrl_sdmmc1_default: sdmmc1-default { + pinmux = <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>, + <PIN_PA22__SDMMC1_CK>, + <PIN_PA28__SDMMC1_CMD>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + }; + + pinctrl_spi1_default: spi1-default { + pinmux = <PIN_PC1__SPI1_SPCK>, + <PIN_PC2__SPI1_MOSI>, + <PIN_PC3__SPI1_MISO>, + <PIN_PC4__SPI1_NPCS0>, + <PIN_PC5__SPI1_NPCS1>, + <PIN_PC6__SPI1_NPCS2>, + <PIN_PC7__SPI1_NPCS3>; + bias-disable; + }; + + pinctrl_usb_default: usb-default { + pinmux = <PIN_PA6__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba-vbus { + pinmux = <PIN_PB13__GPIO>; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + label = "atmel_qspi1"; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + disable-wp; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + disable-wp; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_debug_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rpi_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PB13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PA6 GPIO_ACTIVE_HIGH + 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi index 50650e2f42..58ceed9978 100644 --- a/arch/arm/boot/dts/microchip/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -694,7 +694,7 @@ clock-names = "aes_clk"; }; - tdes: crpyto@fc04c000 { + tdes: crypto@fc04c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc04c000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts index 9b1cc7f4ad..cd7843339c 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts @@ -146,7 +146,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - bmc@0{ + bmc@0 { label = "bmc"; reg = <0x000000 0x2000000>; }; @@ -155,7 +155,7 @@ reg = <0x0000000 0x80000>; read-only; }; - u-boot-env@100000{ + u-boot-env@100000 { label = "u-boot-env"; reg = <0x00100000 0x40000>; }; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts index 58329adbd9..5787ae95d3 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts @@ -397,7 +397,7 @@ reg = <0x0000000 0xC0000>; read-only; }; - u-boot-env@100000{ + u-boot-env@100000 { label = "u-boot-env"; reg = <0x00100000 0x40000>; }; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index 209fa34003..baa39d0c10 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -111,7 +111,7 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - bmc@0{ + bmc@0 { label = "bmc"; reg = <0x000000 0x2000000>; }; @@ -120,7 +120,7 @@ reg = <0x0000000 0x80000>; read-only; }; - u-boot-env@100000{ + u-boot-env@100000 { label = "u-boot-env"; reg = <0x00100000 0x40000>; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts index 486fd24429..a619ea83ed 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts @@ -65,7 +65,7 @@ rgb { status = "okay"; - port@0 { + port { lcd_output: endpoint { remote-endpoint = <&lvds_encoder_input>; bus-width = <18>; diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index a3757b7dae..e118809dc6 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -66,7 +66,7 @@ rgb { status = "okay"; - port@0 { + port { lcd_output: endpoint { remote-endpoint = <&lvds_encoder_input>; bus-width = <18>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi index bae09d8259..680edff0f2 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi @@ -10,7 +10,7 @@ rgb { status = "okay"; - port@0 { + port { dpi_output: endpoint { remote-endpoint = <&bridge_input>; bus-width = <24>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts index efde7dad71..9c480fde2e 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts @@ -15,7 +15,7 @@ rgb { status = "okay"; - port@0 { + port { dpi_output: endpoint { remote-endpoint = <&bridge_input>; bus-width = <24>; diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 3629e343d3..a724d1a7a9 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -47,6 +47,8 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-qsb.dtb \ imx53-qsrb.dtb \ imx53-sk-imx53.dtb \ + imx53-sk-imx53-atm0700d4-lvds.dtb \ + imx53-sk-imx53-atm0700d4-rgb.dtb \ imx53-smd.dtb \ imx53-tx53-x03x.dtb \ imx53-tx53-x13x.dtb \ @@ -244,6 +246,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-udoo.dtb \ imx6q-utilite-pro.dtb \ imx6q-var-dt6customboard.dtb \ + imx6q-var-mx6customboard.dtb \ imx6q-vicut1.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts index 5833fb6f15..2c817c4a4c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts @@ -65,7 +65,7 @@ pinctrl-0 = <&pinctrl_weim>; status = "okay"; - nor: nor@0,0 { + nor: flash@0,0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <4>; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts index 1f11e9542a..e66eef87a7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts @@ -45,7 +45,7 @@ pinctrl-0 = <&pinctrl_weim>; status = "okay"; - nor: nor@0,0 { + nor: flash@0,0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi index e312f1e74e..4aeb74479f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx1.dtsi @@ -268,9 +268,12 @@ status = "disabled"; }; - esram: esram@300000 { + esram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; + ranges = <0 0x00300000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi index 0703f62d10..93a6e4e680 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi @@ -27,7 +27,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pcf8563@51 { + rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts index fc8a502fc9..6cddb2cc36 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -16,7 +16,7 @@ bus-width = <18>; display-timings { native-mode = <&qvga_timings>; - qvga_timings: 320x240 { + qvga_timings: timing0 { clock-frequency = <6500000>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts index 80a7f96de4..64b2ffac46 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts @@ -16,7 +16,7 @@ bus-width = <18>; display-timings { native-mode = <&dvi_svga_timings>; - dvi_svga_timings: 800x600 { + dvi_svga_timings: timing0 { clock-frequency = <40000000>; hactive = <800>; vactive = <600>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts index 24027a1fb4..fb074bfdaa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts @@ -16,7 +16,7 @@ bus-width = <18>; display-timings { native-mode = <&dvi_vga_timings>; - dvi_vga_timings: 640x480 { + dvi_vga_timings: timing0 { clock-frequency = <31250000>; hactive = <640>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts index 04f4b127a1..e93bf3b711 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts @@ -68,7 +68,7 @@ bus-width = <18>; display-timings { native-mode = <&wvga_timings>; - wvga_timings: 640x480 { + wvga_timings: timing0 { hactive = <640>; vactive = <480>; hback-porch = <45>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi index 5f90d72b84..f65c7234f9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -529,7 +529,6 @@ compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 126>; - clock-names = ""; interrupts = <55>; }; @@ -543,7 +542,7 @@ }; iim: efuse@53ff0000 { - compatible = "fsl,imx25-iim", "fsl,imx27-iim"; + compatible = "fsl,imx25-iim"; reg = <0x53ff0000 0x4000>; interrupts = <19>; clocks = <&clks 99>; @@ -583,10 +582,9 @@ }; dryice@53ffc000 { - compatible = "fsl,imx25-dryice", "fsl,imx25-rtc"; + compatible = "fsl,imx25-rtc"; reg = <0x53ffc000 0x4000>; clocks = <&clks 81>; - clock-names = "ipg"; interrupts = <25 56>; }; }; @@ -594,6 +592,9 @@ iram: sram@78000000 { compatible = "mmio-sram"; reg = <0x78000000 0x20000>; + ranges = <0 0x78000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; emi@80000000 { diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts index a21f1f7c24..849306cb45 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts @@ -16,7 +16,7 @@ fsl,pcr = <0xfae80083>; /* non-standard but required */ display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing0 { clock-frequency = <33000033>; hactive = <800>; vactive = <480>; @@ -47,7 +47,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - user { + led-user { label = "Heartbeat"; gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi index 74110bbcd9..c7e9235848 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi @@ -33,7 +33,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pcf8563@51 { + rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -90,7 +90,7 @@ &weim { status = "okay"; - nor: nor@0,0 { + nor: flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts index 145e459625..d787936013 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts @@ -16,7 +16,7 @@ display-timings { native-mode = <&timing0>; - timing0: 320x240 { + timing0: timing0 { clock-frequency = <6500000>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts index 25442eba21..27c93b9fe0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts @@ -19,7 +19,7 @@ fsl,pcr = <0xf0c88080>; /* non-standard but required */ display-timings { native-mode = <&timing0>; - timing0: 640x480 { + timing0: timing0 { hactive = <640>; vactive = <480>; hback-porch = <112>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi index 303f920201..abc9233c5a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi @@ -34,7 +34,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - at24@52 { + eeprom@52 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x52>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts index 7f0cd4d3ec..67b235044b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts @@ -19,7 +19,7 @@ display-timings { native-mode = <&timing0>; - timing0: 240x320 { + timing0: timing0 { clock-frequency = <5500000>; hactive = <240>; vactive = <320>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi index 7191e10712..8d428c8446 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi @@ -180,7 +180,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - at24@52 { + eeprom@52 { compatible = "atmel,24c32"; pagesize = <32>; reg = <0x52>; @@ -314,7 +314,7 @@ &weim { status = "okay"; - nor: nor@0,0 { + nor: flash@0,0 { compatible = "cfi-flash"; reg = <0 0x00000000 0x02000000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi index faba12ee74..cac4b3d689 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi @@ -588,6 +588,9 @@ iram: sram@ffff4c00 { compatible = "mmio-sram"; reg = <0xffff4c00 0xb400>; + ranges = <0 0xffff4c00 0xb400>; + #address-cells = <1>; + #size-cells = <1>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts index 5d4b29d765..7cd17b43b4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts @@ -119,8 +119,8 @@ compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_swi2c>; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */ - <&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */ + sda-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <50>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi index 2b3195f5e3..c96d6311df 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -651,7 +651,7 @@ }; sahara: crypto@83ff8000 { - compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; + compatible = "fsl,imx53-sahara"; reg = <0x83ff8000 0x4000>; interrupts = <19 20>; clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-lvds.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-lvds.dts new file mode 100644 index 0000000000..b1c1e7c759 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-lvds.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 Linaro Ltd. + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include "imx53-sk-imx53-atm0700d4.dtsi" + +/ { + lvds-decoder { + compatible = "ti,sn65lvds94", "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_decoder_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_rgb_in>; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_spi_gpio: spigrp { + fsl,pins = < + MX53_PAD_EIM_A22__GPIO2_16 0x1f4 + MX53_PAD_EIM_A21__GPIO2_17 0x1f4 + MX53_PAD_EIM_A16__GPIO2_22 0x1f4 + MX53_PAD_EIM_A18__GPIO2_20 0x1f4 + >; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&lvds_decoder_in>; + }; + }; + }; +}; + +&panel_rgb_in { + remote-endpoint = <&lvds_decoder_out>; +}; + +&spi_ts { + pinctrl-0 = <&pinctrl_spi_gpio>; + pinctrl-names = "default"; + + sck-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; +}; + +&touchscreen { + interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_BOTH>; + pendown-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-rgb.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-rgb.dts new file mode 100644 index 0000000000..2559ada7e4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-rgb.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 Linaro Ltd. + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include "imx53-sk-imx53-atm0700d4.dtsi" + +/ { + display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-0 = <&pinctrl_rgb24>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_rgb_in>; + }; + }; + }; + +}; + +&iomuxc { + pinctrl_rgb24: rgb24grp { + fsl,pins = < + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_spi_gpio: spigrp { + fsl,pins = < + MX53_PAD_SD1_DATA1__GPIO1_17 0x1f4 + MX53_PAD_GPIO_7__GPIO1_7 0x1f4 + MX53_PAD_PATA_DATA3__GPIO2_3 0x1f4 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1f4 + >; + }; +}; + +&ipu_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&panel { + enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; +}; + +&panel_rgb_in { + remote-endpoint = <&display_out>; +}; + +&pwm1 { + status = "disabled"; +}; + +&spi_ts { + pinctrl-0 = <&pinctrl_spi_gpio>; + pinctrl-names = "default"; + + sck-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; +}; + +&touchscreen { + interrupts-extended = <&gpio2 6 IRQ_TYPE_EDGE_BOTH>; + pendown-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi new file mode 100644 index 0000000000..e395004e80 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 Linaro Ltd. + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include "imx53-sk-imx53.dts" + +/ { + panel: panel-rgb { + compatible = "powertip,ph800480t013-idf02"; + + port { + panel_rgb_in: endpoint { + }; + }; + }; + + spi_ts: spi { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + num-chipselects = <1>; + + touchscreen: touchscreen@0 { + reg = <0>; + compatible = "ti,ads7843"; + spi-max-frequency = <300000>; + + ti,vref-mv = /bits/ 16 <3300>; + ti,x-plate-ohms = /bits/ 16 <450>; + ti,y-plate-ohms = /bits/ 16 <250>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <0>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + touchscreen-swapped-x-y; + touchscreen-max-pressure = <100>; + + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi index 0ebc35e6e9..07658e4770 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53.dtsi @@ -275,7 +275,7 @@ ecspi1: spi@50010000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx53-ecspi"; reg = <0x50010000 0x4000>; interrupts = <36>; clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, @@ -701,7 +701,7 @@ ecspi2: spi@63fac000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx53-ecspi"; reg = <0x63fac000 0x4000>; interrupts = <37>; clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts index fa1a1df37c..b0d345f5d0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts @@ -98,8 +98,8 @@ }; &usbphy1 { - fsl,tx-cal-45-dn-ohms = <55>; - fsl,tx-cal-45-dp-ohms = <55>; + fsl,tx-cal-45-dn-ohms = <54>; + fsl,tx-cal-45-dp-ohms = <54>; fsl,tx-d-cal = <100>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts index fb9f320103..46c6b96d80 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -637,11 +637,11 @@ }; &usbphy1 { - fsl,tx-d-cal = <0x5>; + fsl,tx-d-cal = <79>; }; &usbphy2 { - fsl,tx-d-cal = <0x5>; + fsl,tx-d-cal = <79>; }; &usdhc1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts new file mode 100644 index 0000000000..6f9d094dd6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Carrier-board + * + * Copyright 2016 Variscite, Ltd. All Rights Reserved + * Copyright 2022 Bootlin + */ + +/dts-v1/; + +#include "imx6qdl-var-som.dtsi" +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board"; + compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q"; + + panel0: lvds-panel0 { + compatible = "panel-lvds"; + backlight = <&backlight_lvds>; + width-mm = <152>; + height-mm = <91>; + label = "etm070001adh6"; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <32000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <39>; + hfront-porch = <39>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <47>; + vsync-len = <2>; + }; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + panel1: lvds-panel1 { + compatible = "panel-lvds"; + width-mm = <152>; + height-mm = <91>; + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <38251000>; + hactive = <800>; + vactive = <600>; + hback-porch = <112>; + hfront-porch = <32>; + vback-porch = <3>; + vfront-porch = <17>; + hsync-len = <80>; + vsync-len = <4>; + }; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000 0>; + brightness-levels = <0 4 8 16 32 64 128 248>; + default-brightness-level = <7>; + power-supply = <®_3p3v>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + touchscreen-size-x = <880>; + touchscreen-size-y = <1280>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1800>; + touchscreen-size-y = <1000>; + }; +}; + +&iomuxc { + pinctrl_camera: cameragrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg_var: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 9594bc5745..1e723807ab 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -52,6 +52,11 @@ / { /* these are used by bootloader for disabling nodes */ aliases { + ethernet0 = &fec; + ethernet1 = &lan1; + ethernet2 = &lan2; + ethernet3 = &lan3; + ethernet4 = &lan4; led0 = &led0; led1 = &led1; led2 = &led2; @@ -212,28 +217,61 @@ compatible = "marvell,mv88e6085"; reg = <0>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + sw_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + sw_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + sw_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + lan4: port@0 { reg = <0>; label = "lan4"; + phy-handle = <&sw_phy0>; + phy-mode = "internal"; + local-mac-address = [00 00 00 00 00 00]; }; - port@1 { + lan3: port@1 { reg = <1>; label = "lan3"; + phy-handle = <&sw_phy1>; + phy-mode = "internal"; + local-mac-address = [00 00 00 00 00 00]; }; - port@2 { + lan2: port@2 { reg = <2>; label = "lan2"; + phy-handle = <&sw_phy2>; + phy-mode = "internal"; + local-mac-address = [00 00 00 00 00 00]; }; - port@3 { + lan1: port@3 { reg = <3>; label = "lan1"; + phy-handle = <&sw_phy3>; + phy-mode = "internal"; + local-mac-address = [00 00 00 00 00 00]; }; port@5 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi index 218d6e667e..424dc7fcd5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi @@ -326,7 +326,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio7>; interrupts = <13 0>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi index de5983cf78..49ea25c719 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi @@ -307,7 +307,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio7>; interrupts = <13 0>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index 763831dc0e..32a110a35b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -15,7 +15,7 @@ reg = <0x10000000 0xF0000000>; }; - reg_1p8v: regulator@0 { + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "1P8V"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi new file mode 100644 index 0000000000..a1ea33c4ee --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-MX6 Module + * + * Copyright 2011 Linaro Ltd. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Variscite, Ltd. + * Author: Donio Ron <ron.d@variscite.com> + * Copyright 2022 Bootlin + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include <dt-bindings/clock/imx6qdl-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Variscite VAR-SOM-MX6 module"; + compatible = "variscite,var-som-imx6q", "fsl,imx6q"; + + chosen { + stdout-path = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbud { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_wl18xx_vmmc: regulator-wl18xx { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + }; + + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "var-som-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_codec>; + simple-audio-card,frame-master = <&sound_codec>; + simple-audio-card,widgets = "Headphone", "Headphone Jack", + "Line", "Line In", "Microphone", "Mic Jack"; + simple-audio-card,routing = "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + sound_cpu: simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + sound_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&clks IMX6QDL_CLK_CKO>; + }; + }; + + rfkill { + compatible = "rfkill-gpio"; + name = "rfkill"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_SYN | + IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(2) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(2)) + IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-aud3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: ethernet-phy@7 { + reg = <7>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + tlv320aic3106: audio-codec@1b { + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + #sound-dai-cells = <0>; + DRVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <®_1p8v>; + ai3x-ocmv = <0>; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = < + 0 /* AIC3X_GPIO1_FUNC_DISABLED */ + 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ + >; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + /* Audio Clock */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + /* Bluetooth/wifi enable */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1 + /* Wifi Slow Clock */ + MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* CTW6120 IRQ */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0xb0b1 + /* SDMMC2 CD/WP */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + /* PMIC INT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17069 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17069 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17069 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17069 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17069 + /* WL_EN */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x13059 + /* WL_IRQ */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 + /* WL_EN */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130B9 + /* WL_IRQ */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130B9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 + /* WL_EN */ + MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130F9 + /* WL_IRQ */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130F9 + >; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +®_arm { + vin-supply = <&sw1a_reg>; +}; + +®_pu { + vin-supply = <&sw1c_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <&vgen5_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen5_reg>; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_var>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <0x5>; +}; + +&usbphy2 { + fsl,tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi: wifi@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + ref-clock-frequency = <38400000>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 6bd9047305..1db146ac1c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -114,10 +114,8 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio>; - gpios = < - &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ - &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ - >; + sda-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts index 919c0464d6..b2cdf48777 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-aster.dts @@ -12,6 +12,5 @@ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; compatible = "toradex,colibri-imx6ull-emmc-aster", "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts index 61b93cb040..2dc16c54fc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-eval-v3.dts @@ -12,6 +12,5 @@ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-emmc-eval", "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts index b9060c2f79..9bae08fb7f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris-v2.dts @@ -10,8 +10,7 @@ / { model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; - compatible = "toradex,colibri-imx6ull-iris-v2", + compatible = "toradex,colibri-imx6ull-emmc-iris-v2", "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts index 0ab71f2f5d..0b1603ff94 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-emmc-iris.dts @@ -12,6 +12,5 @@ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; compatible = "toradex,colibri-imx6ull-emmc-iris", "toradex,colibri-imx6ull-emmc", - "toradex,colibri-imx6ull", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts index d6da984e51..c5bc255b21 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-eval-v3.dts @@ -10,7 +10,7 @@ / { model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; + compatible = "toradex,colibri-imx6ull-eval", "toradex,colibri-imx6ull", "fsl,imx6ull"; }; &ad7879_ts { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts index c7da5b4196..d3bbd05da2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-aster.dts @@ -11,7 +11,7 @@ / { model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; compatible = "toradex,colibri-imx6ull-wifi-aster", - "toradex,colibri-imx6ull", + "toradex,colibri-imx6ull-wifi", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts index 917f5dbe64..0ac306c9ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-eval-v3.dts @@ -10,7 +10,7 @@ / { model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; - compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; + compatible = "toradex,colibri-imx6ull-wifi-eval", "toradex,colibri-imx6ull-wifi", "fsl,imx6ull"; }; &ad7879_ts { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts index 488da6df56..38cd52c454 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris-v2.dts @@ -11,7 +11,7 @@ / { model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; compatible = "toradex,colibri-imx6ull-wifi-iris-v2", - "toradex,colibri-imx6ull", + "toradex,colibri-imx6ull-wifi", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts index e632532547..5f60df64f1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-wifi-iris.dts @@ -11,7 +11,7 @@ / { model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; compatible = "toradex,colibri-imx6ull-wifi-iris", - "toradex,colibri-imx6ull", + "toradex,colibri-imx6ull-wifi", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts index 14adb87da9..1610f3892d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-emmc.dts @@ -9,8 +9,8 @@ / { model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-phygate-tauri-emmc", + compatible = "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-phygate-tauri", "phytec,imx6ull-pcl063", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts index ae396ac634..92e7d38d56 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri-nand.dts @@ -9,8 +9,8 @@ / { model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-phygate-tauri-nand", + compatible = "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-phygate-tauri", "phytec,imx6ull-pcl063", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index ea627638e4..d12fb44aeb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -9,11 +9,6 @@ #include "imx6ull-phytec-phycore-som.dtsi" / { - - model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; - compatible = "phytec,imx6ull-phygate-tauri", - "phytec,imx6ull-pcl063", "fsl,imx6ull"; - aliases { rtc0 = &i2c_rtc; rtc1 = &snvs_rtc; @@ -121,7 +116,7 @@ tpm_tis: tpm@1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm>; - compatible = "tcg,tpm_tis-spi"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <1>; spi-max-frequency = <20000000>; interrupt-parent = <&gpio5>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts index d9c7045a55..212e068558 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-aster.dts @@ -12,7 +12,6 @@ model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board"; compatible = "toradex,colibri-imx7d-emmc-aster", "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", "fsl,imx7d"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts index 96b599439d..1deece7e71 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-eval-v3.dts @@ -11,7 +11,6 @@ model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx7d-emmc-eval-v3", "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", "fsl,imx7d"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts index 5eccb837b1..22e7863c2e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris-v2.dts @@ -11,7 +11,6 @@ model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board"; compatible = "toradex,colibri-imx7d-emmc-iris-v2", "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", "fsl,imx7d"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts index ae10e8a66f..a3cf8f50e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-colibri-emmc-iris.dts @@ -11,7 +11,6 @@ model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board"; compatible = "toradex,colibri-imx7d-emmc-iris", "toradex,colibri-imx7d-emmc", - "toradex,colibri-imx7d", "fsl,imx7d"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts index 3a723843d5..9984b343cd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-flex-concentrator.dts @@ -130,7 +130,7 @@ * TCG specification - Section 6.4.1 Clocking: * TPM shall support a SPI clock frequency range of 10-24 MHz. */ - st33htph: tpm-tis@0 { + st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <24000000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts index f263e391e2..6222113133 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -61,6 +61,10 @@ }; }; +&usdhc1 { + status = "disabled"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi index 4b94b8afb5..0484e349e0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi @@ -217,9 +217,6 @@ }; &ca_funnel_in_ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { reg = <1>; ca_funnel_in_port1: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index bc79163c49..4569d2b8ed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -190,7 +190,11 @@ clock-names = "apb_pclk"; ca_funnel_in_ports: in-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; ca_funnel_in_port0: endpoint { remote-endpoint = <&etm0_out_port>; }; @@ -658,7 +662,6 @@ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <3>; interrupt-parent = <&intc>; - #power-domain-cells = <1>; pgc { #address-cells = <1>; @@ -800,10 +803,8 @@ compatible = "fsl,imx7-csi"; reg = <0x30710000 0x10000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CSI_MCLK_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "axi", "mclk", "dcic"; + clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>; + clock-names = "mclk"; status = "disabled"; port { @@ -814,7 +815,7 @@ }; lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; reg = <0x30730000 0x10000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, @@ -1278,7 +1279,7 @@ gpmi: nand-controller@33002000 { compatible = "fsl,imx7d-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x33002000 0x2000>, <0x33004000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index b01ddda7bd..ac338320ac 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -209,7 +209,7 @@ }; usbphy1: usb-phy@40350000 { - compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; + compatible = "fsl,imx7ulp-usbphy"; reg = <0x40350000 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index ebf97fcdd8..5a8b867d7d 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -35,22 +35,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buttons>; - button1 { + button-1 { label = "s14"; linux,code = <KEY_1>; gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + wakeup-source; }; - button2 { + button-2 { label = "s6"; linux,code = <KEY_2>; gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + wakeup-source; }; - button3 { + button-3 { label = "s7"; linux,code = <KEY_3>; gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + wakeup-source; }; power-button { diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts index 3b609d987d..7365fe4581 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-evk.dts @@ -137,7 +137,7 @@ backlight_display: backlight { compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; + pwms = <&pwm 2 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts index 46057d9bf5..b23e7ada9c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts @@ -166,7 +166,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; + pwms = <&pwm 2 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; @@ -175,10 +175,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; - gpios = < - &gpio1 24 0 /* SDA */ - &gpio1 22 0 /* SCL */ - >; + sda-gpios = <&gpio1 24 0>; + scl-gpios = <&gpio1 22 0>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ }; @@ -186,10 +184,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "i2c-gpio"; - gpios = < - &gpio0 31 0 /* SDA */ - &gpio0 30 0 /* SCL */ - >; + sda-gpios = <&gpio0 31 0>; + scl-gpios = <&gpio0 30 0>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ touch: touch@20 { diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts index b1d8210f3e..28341d8315 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts @@ -153,7 +153,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; + pwms = <&pwm 2 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi index 5eca942a52..9cba1d0224 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi @@ -412,7 +412,7 @@ status = "disabled"; }; - dma_apbx: dma-apbx@80024000 { + dma_apbx: dma-controller@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; interrupts = <7>, <5>, <9>, <26>, @@ -561,7 +561,7 @@ compatible = "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; clocks = <&clks 30>; - #pwm-cells = <2>; + #pwm-cells = <3>; fsl,pwm-number = <5>; status = "disabled"; }; @@ -598,7 +598,7 @@ reg = <0x80070000 0x2000>; interrupts = <0>; clocks = <&clks 32>, <&clks 16>; - clock-names = "uart", "apb_pclk"; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts index fd6fee63ad..6c87266eb1 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts @@ -39,7 +39,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 191000>; + pwms = <&pwm 3 191000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts index 953e3162d2..f0ce897b9d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts @@ -173,7 +173,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts index 70e225a99f..cb68edd610 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts @@ -39,7 +39,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts index 0be7356941..5875c3d7ba 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts @@ -26,7 +26,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; + pwms = <&pwm 4 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts index aae0f18014..b414e67ef3 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts @@ -26,7 +26,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi index 6633cde305..652fc9e57a 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi @@ -14,7 +14,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 4 1000000>; + pwms = <&pwm 4 1000000 0>; brightness-levels = <0 25 50 75 100 125 150 175 200 225 255>; default-brightness-level = <10>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts index 783abb82b2..9ebb7371e2 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts @@ -117,7 +117,7 @@ backlight_display: backlight { compatible = "pwm-backlight"; - pwms = <&pwm 2 5000000>; + pwms = <&pwm 2 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts index 8241c2d159..34b4d3246d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts @@ -17,7 +17,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 3 5000000>; + pwms = <&pwm 3 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts index 6bf26f386a..13070ca08c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts @@ -13,7 +13,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 4 5000000>; + pwms = <&pwm 4 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts index 23ad7cd0a1..153e401795 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -131,7 +131,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm 0 500000>; + pwms = <&pwm 0 500000 0>; /* * a silly way to create a 1:1 relationship between the * PWM value and the actual duty cycle @@ -652,6 +652,7 @@ vbus-supply = <®_usb0_vbus>; disable-over-current; dr_mode = "peripheral"; + phy_type = "utmi"; status = "okay"; }; @@ -659,19 +660,18 @@ vbus-supply = <®_usb1_vbus>; disable-over-current; dr_mode = "host"; + phy_type = "utmi"; status = "okay"; }; &usbphy0 { pinctrl-names = "default"; pinctrl-0 = <&tx28_usbphy0_pins>; - phy_type = "utmi"; status = "okay"; }; &usbphy1 { pinctrl-names = "default"; pinctrl-0 = <&tx28_usbphy1_pins>; - phy_type = "utmi"; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi index 763adeb995..37b9d409a5 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi @@ -990,7 +990,7 @@ status = "disabled"; }; - dma_apbx: dma-apbx@80024000 { + dma_apbx: dma-controller@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; interrupts = <78>, <79>, <66>, <0>, @@ -1003,7 +1003,7 @@ }; dcp: crypto@80028000 { - compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; + compatible = "fsl,imx28-dcp"; reg = <0x80028000 0x2000>; interrupts = <52>, <53>, <54>; status = "okay"; @@ -1185,7 +1185,7 @@ compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 0x2000>; clocks = <&clks 44>; - #pwm-cells = <2>; + #pwm-cells = <3>; fsl,pwm-number = <8>; status = "disabled"; }; @@ -1252,7 +1252,7 @@ reg = <0x80074000 0x1000>; interrupts = <47>; clocks = <&clks 45>, <&clks 26>; - clock-names = "uart", "apb_pclk"; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index d1095b700c..acccf9a3c8 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -111,8 +111,7 @@ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART0>; clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; + dmas = <&edma0 0 2>, <&edma0 0 3>; dma-names = "rx","tx"; status = "disabled"; }; @@ -123,8 +122,7 @@ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART1>; clock-names = "ipg"; - dmas = <&edma0 0 4>, - <&edma0 0 5>; + dmas = <&edma0 0 4>, <&edma0 0 5>; dma-names = "rx","tx"; status = "disabled"; }; @@ -135,8 +133,7 @@ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART2>; clock-names = "ipg"; - dmas = <&edma0 0 6>, - <&edma0 0 7>; + dmas = <&edma0 0 6>, <&edma0 0 7>; dma-names = "rx","tx"; status = "disabled"; }; @@ -147,8 +144,7 @@ interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_UART3>; clock-names = "ipg"; - dmas = <&edma0 0 8>, - <&edma0 0 9>; + dmas = <&edma0 0 8>, <&edma0 0 9>; dma-names = "rx","tx"; status = "disabled"; }; @@ -162,8 +158,7 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, - <&edma1 1 13>; + dmas = <&edma1 1 12>, <&edma1 1 13>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -177,8 +172,7 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, - <&edma1 1 15>; + dmas = <&edma1 1 14>, <&edma1 1 15>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,8 +420,7 @@ interrupts = <72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_I2C1>; clock-names = "ipg"; - dmas = <&edma0 0 52>, - <&edma0 0 53>; + dmas = <&edma0 0 52>, <&edma0 0 53>; dma-names = "rx","tx"; status = "disabled"; }; @@ -551,8 +544,7 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, - <&edma1 0 13>; + dmas = <&edma1 0 12>, <&edma1 0 13>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -719,8 +711,7 @@ interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks VF610_CLK_I2C3>; clock-names = "ipg"; - dmas = <&edma0 1 38>, - <&edma0 1 39>; + dmas = <&edma0 1 38>, <&edma0 1 39>; dma-names = "rx","tx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/pm8226.dtsi index 2413778f37..2413778f37 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom/pm8226.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom/pm8841.dtsi index 3bf2ce5c86..3bf2ce5c86 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom/pm8841.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/pm8941.dtsi index ed0ba591c7..ed0ba591c7 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom/pm8941.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/pma8084.dtsi index 2985f4805b..2985f4805b 100644 --- a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom/pma8084.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/pmx55.dtsi index da0851173c..da0851173c 100644 --- a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom/pmx55.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom/pmx65.dtsi index 1c7fdf59c1..1c7fdf59c1 100644 --- a/arch/arm/boot/dts/qcom/qcom-pmx65.dtsi +++ b/arch/arm/boot/dts/qcom/pmx65.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts index aa0e0e8d2a..a39f5a161b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-asus-sparrow.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" +#include "pm8226.dtsi" /delete-node/ &adsp_region; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts index de19640efe..59b218042d 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-huawei-sturgeon.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" +#include "pm8226.dtsi" #include <dt-bindings/input/ti-drv260x.h> /delete-node/ &adsp_region; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts index b887e5361e..feb78afef3 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-lg-lenok.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" +#include "pm8226.dtsi" /delete-node/ &adsp_region; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts index f516e0426b..cffc069712 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -7,7 +7,7 @@ #include <dt-bindings/input/input.h> #include "qcom-msm8226.dtsi" -#include "qcom-pm8226.dtsi" +#include "pm8226.dtsi" /delete-node/ &adsp_region; /delete-node/ &smem_region; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts index db4c791b2e..94351c9bf9 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8060-dragonboard.dts @@ -24,7 +24,6 @@ regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; regulator-name = "VPH"; - regulator-type = "voltage"; regulator-always-on; regulator-boot-on; }; @@ -72,7 +71,7 @@ /* Trig on both edges - getting close or far away */ interrupts-extended = <&pm8058_gpio 34 IRQ_TYPE_EDGE_BOTH>; /* MPP05 analog input to the XOADC */ - io-channels = <&xoadc 0x00 0x05>; + io-channels = <&pm8058_xoadc 0x00 0x05>; io-channel-names = "aout"; pinctrl-names = "default"; pinctrl-0 = <&dragon_cm3605_gpios>, <&dragon_cm3605_mpps>; @@ -945,7 +944,7 @@ }; }; -&xoadc { +&pm8058_xoadc { /* Reference voltage 2.2 V */ xoadc-ref-supply = <&pm8058_l18>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index c57c27cd8a..c0dd6399f5 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -36,7 +36,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "ext_3p3v"; - regulator-type = "voltage"; startup-delay-us = <0>; gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; enable-active-high; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index 9630755052..b0c5e7bd5e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -58,7 +58,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "ext_3p3v"; - regulator-type = "voltage"; startup-delay-us = <0>; gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; enable-active-high; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 950adb63af..099a16c34e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1270,7 +1270,6 @@ dsi0: dsi@4700000 { compatible = "qcom,apq8064-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - label = "MDSS DSI CTRL->0"; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 6d1b2439ae..950fa652f9 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -4,8 +4,8 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" /delete-node/ &mpss_region; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts index 116e59a3b7..1df24c922b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" +#include "pma8084.dtsi" / { model = "Qualcomm APQ8084/IFC6540"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts index c6b6680248..d4e6aee034 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-apq8084.dtsi" -#include "qcom-pma8084.dtsi" +#include "pma8084.dtsi" / { model = "Qualcomm APQ 8084-MTP"; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts index 1796ded31d..12e806adcd 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -20,6 +20,33 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led-0 { + label = "rb3011:green:user"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + memory@42000000 { reg = <0x42000000 0x3e000000>; device_type = "memory"; @@ -302,34 +329,6 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - button { - label = "reset"; - linux,code = <KEY_RESTART>; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led-0 { - label = "rb3011:green:user"; - color = <LED_COLOR_ID_GREEN>; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi index 17f65e140e..49de975263 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi @@ -14,6 +14,67 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + button-1 { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + button-2 { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led-0 { + label = "led_usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led-1 { + label = "led_usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbdev"; + default-state = "off"; + }; + + led-2 { + label = "status_led_fail"; + function = LED_FUNCTION_STATUS; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "sata_led"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + label = "status_led_pass"; + function = LED_FUNCTION_STATUS; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + soc { gsbi@16300000 { qcom,mode = <GSBI_PROT_I2C_UART>; @@ -64,66 +125,5 @@ ports-implemented = <0x1>; status = "okay"; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - button-1 { - label = "reset"; - linux,code = <KEY_RESTART>; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - button-2 { - label = "wps"; - linux,code = <KEY_WPS_BUTTON>; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led-0 { - label = "led_usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led-1 { - label = "led_usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbdev"; - default-state = "off"; - }; - - led-2 { - label = "status_led_fail"; - function = LED_FUNCTION_STATUS; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - label = "sata_led"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-4 { - label = "status_led_pass"; - function = LED_FUNCTION_STATUS; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi index 92c8003dac..dac3aa793f 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi @@ -76,7 +76,7 @@ }; }; -&pmicgpio { +&pm8018_gpio { usb_vbus_5v_pins: usb-vbus-5v-state { pins = "gpio4"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 63e21aa236..c0a60bae70 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -261,7 +261,7 @@ reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; - pmicintc: pmic { + pm8018: pmic { compatible = "qcom,pm8018", "qcom,pm8921"; interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; @@ -272,38 +272,38 @@ pwrkey@1c { compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; reg = <0x1c>; - interrupt-parent = <&pmicintc>; + interrupt-parent = <&pm8018>; interrupts = <50 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>; debounce = <15625>; pull-up; }; - pmicmpp: mpps@50 { + pm8018_mpps: mpps@50 { compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp"; interrupt-controller; #interrupt-cells = <2>; reg = <0x50>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pmicmpp 0 0 6>; + gpio-ranges = <&pm8018_mpps 0 0 6>; }; rtc@11d { compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; + interrupt-parent = <&pm8018>; interrupts = <39 IRQ_TYPE_EDGE_RISING>; reg = <0x11d>; allow-set-time; }; - pmicgpio: gpio@150 { + pm8018_gpio: gpio@150 { compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; reg = <0x150>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; - gpio-ranges = <&pmicgpio 0 0 6>; + gpio-ranges = <&pm8018_gpio 0 0 6>; #gpio-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 78738371f6..5cd03ea7b0 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -56,6 +56,18 @@ rpm: remoteproc { compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; + master-stats { + compatible = "qcom,rpm-master-stats"; + qcom,rpm-msg-ram = <&apss_master_stats>, + <&mpss_master_stats>, + <&lpss_master_stats>, + <&pronto_master_stats>; + qcom,master-names = "APSS", + "MPSS", + "LPSS", + "PRONTO"; + }; + smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; @@ -230,6 +242,17 @@ status = "disabled"; }; + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + status = "disabled"; + }; + blsp1_uart3: serial@f991f000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991f000 0x1000>; @@ -313,6 +336,21 @@ #size-cells = <0>; }; + blsp1_i2c6: i2c@f9928000 { + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", + "iface"; + pinctrl-0 = <&blsp1_i2c6_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cci: cci@fda0c000 { compatible = "qcom,msm8226-cci"; #address-cells = <1>; @@ -460,6 +498,13 @@ bias-disable; }; + blsp1_i2c6_pins: blsp1-i2c6-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + cci_default: cci-default-state { pins = "gpio29", "gpio30"; function = "cci_i2c0"; @@ -742,6 +787,26 @@ rpm_msg_ram: sram@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfc428000 0x4000>; + + apss_master_stats: sram@150 { + reg = <0x150 0x14>; + }; + + mpss_master_stats: sram@b50 { + reg = <0xb50 0x14>; + }; + + lpss_master_stats: sram@1550 { + reg = <0x1550 0x14>; + }; + + pronto_master_stats: sram@1f50 { + reg = <0x1f50 0x14>; + }; }; tcsr_mutex: hwlock@fd484000 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index 78023ed2fd..9217ced108 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -80,13 +80,13 @@ */ iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&xoadc 0x00 0x01>, /* Battery */ - <&xoadc 0x00 0x02>, /* DC in (charger) */ - <&xoadc 0x00 0x04>, /* VPH the main system voltage */ - <&xoadc 0x00 0x0b>, /* Die temperature */ - <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ - <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ - <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ + io-channels = <&pm8058_xoadc 0x00 0x01>, /* Battery */ + <&pm8058_xoadc 0x00 0x02>, /* DC in (charger) */ + <&pm8058_xoadc 0x00 0x04>, /* VPH the main system voltage */ + <&pm8058_xoadc 0x00 0x0b>, /* Die temperature */ + <&pm8058_xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ + <&pm8058_xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ + <&pm8058_xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ }; soc: soc { @@ -390,7 +390,7 @@ row-hold = <91500>; }; - xoadc: xoadc@197 { + pm8058_xoadc: xoadc@197 { compatible = "qcom,pm8058-adc"; reg = <0x197>; interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 60bdfddeae..da99f770d4 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi index 68a2f9094e..23ae474698 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 706fef5376..0bc2e66d15 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -116,6 +116,18 @@ rpm: remoteproc { compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; + master-stats { + compatible = "qcom,rpm-master-stats"; + qcom,rpm-msg-ram = <&apss_master_stats>, + <&mpss_master_stats>, + <&lpss_master_stats>, + <&pronto_master_stats>; + qcom,master-names = "APSS", + "MPSS", + "LPSS", + "PRONTO"; + }; + smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; @@ -1067,6 +1079,26 @@ rpm_msg_ram: sram@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfc428000 0x4000>; + + apss_master_stats: sram@150 { + reg = <0x150 0x14>; + }; + + mpss_master_stats: sram@b50 { + reg = <0xb50 0x14>; + }; + + lpss_master_stats: sram@1550 { + reg = <0x1550 0x14>; + }; + + pronto_master_stats: sram@1f50 { + reg = <0x1f50 0x14>; + }; }; bimc: interconnect@fc380000 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts index 42d253b75d..6c4153689b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts index 8230d0e1d9..c0ca264d81 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts index 3e2c86591e..325feb89b3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pma8084.dtsi" +#include "pma8084.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/leds/common.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 11468d1409..0798cce3db 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts index 7e97ad5803..2470693619 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-mtp.dts @@ -9,7 +9,7 @@ #include "qcom-sdx55.dtsi" #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <arm64/qcom/pm8150b.dtsi> -#include "qcom-pmx55.dtsi" +#include "pmx55.dtsi" / { model = "Qualcomm Technologies, Inc. SDX55 MTP"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts index 51058b0652..082f7ed1a0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -8,7 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "qcom-sdx55.dtsi" -#include "qcom-pmx55.dtsi" +#include "pmx55.dtsi" / { model = "Thundercomm T55 Development Kit"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts index 8fadc6e706..e336a15b45 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts @@ -8,7 +8,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "qcom-sdx55.dtsi" -#include "qcom-pmx55.dtsi" +#include "pmx55.dtsi" / { model = "Telit FN980 TLB"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 5b86b4de1a..a976370264 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -379,7 +379,7 @@ power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; @@ -428,7 +428,7 @@ resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -436,20 +436,27 @@ status = "disabled"; }; - pcie_phy: phy@1c07000 { + pcie_phy: phy@1c06000 { compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x1c4>; + reg = <0x01c06000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", - "refgen"; + "refgen", + "pipe"; + + clock-output-names = "pcie_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; @@ -458,20 +465,6 @@ assigned-clock-rates = <100000000>; status = "disabled"; - - pcie_lane: lanes@1c06000 { - reg = <0x01c06000 0x104>, /* tx0 */ - <0x01c06200 0x328>, /* rx0 */ - <0x01c07200 0x1e8>, /* pcs */ - <0x01c06800 0x104>, /* tx1 */ - <0x01c06a00 0x328>, /* rx1 */ - <0x01c07600 0x800>; /* pcs_misc */ - clocks = <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - }; }; ipa: ipa@1e40000 { @@ -645,7 +638,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; tlmm: pinctrl@f100000 { diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts index fcf1c51c5e..07c10c84ee 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -4,11 +4,15 @@ */ /dts-v1/; +/* PM7250B is configured to use SID2/3 */ +#define PM7250B_SID 2 +#define PM7250B_SID1 3 + #include "qcom-sdx65.dtsi" #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <arm64/qcom/pmk8350.dtsi> #include <arm64/qcom/pm7250b.dtsi> -#include "qcom-pmx65.dtsi" +#include "pmx65.dtsi" / { model = "Qualcomm Technologies, Inc. SDX65 MTP"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 271899c861..27b7f50a18 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -466,9 +466,9 @@ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; status = "disabled"; }; @@ -544,7 +544,6 @@ #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <0>; - cell-index = <0>; qcom,channel = <0>; qcom,ee = <0>; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts index 1e8447176b..29ba098f5d 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -29,9 +29,33 @@ reg = <0x08000000 0x08000000>; }; - lbsc { + flash@18000000 { + compatible = "mtd-rom"; + reg = <0x18000000 0x08000000>; + bank-width = <4>; + device-width = <1>; + + clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; + power-domains = <&cpg_clocks>; + #address-cells = <1>; #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "user"; + reg = <0x00000000 0x04000000>; + }; + + partition@4000000 { + label = "user1"; + reg = <0x04000000 0x40000000>; + }; + }; }; leds { @@ -87,6 +111,62 @@ clock-frequency = <13330000>; }; +&bsc { + flash@0 { + compatible = "cfi-flash"; + reg = <0x00000000 0x04000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000000 0x00040000>; + }; + + partition@40000 { + label = "uboot-env"; + reg = <0x00040000 0x00020000>; + }; + + partition@60000 { + label = "flash"; + reg = <0x00060000 0x03fa0000>; + }; + }; + }; + + flash@4000000 { + compatible = "cfi-flash"; + reg = <0x04000000 0x04000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot1"; + reg = <0x00000000 0x00040000>; + }; + + partition@40000 { + label = "uboot-env1"; + reg = <0x00040000 0x00020000>; + }; + + partition@60000 { + label = "flash1"; + reg = <0x00060000 0x03fa0000>; + }; + }; + }; +}; + &usb_x1_clk { clock-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts index 105f9c71f9..9d29861f23 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts @@ -29,14 +29,8 @@ reg = <0x20000000 0x00a00000>; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - flash@18000000 { compatible = "mtd-rom"; - probe-type = "map_rom"; reg = <0x18000000 0x00800000>; bank-width = <4>; device-width = <1>; diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts index 1c5acf6944..b547216d48 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -29,6 +29,48 @@ reg = <0x08000000 0x02000000>; }; + flash@18000000 { + compatible = "mtd-rom"; + reg = <0x18000000 0x08000000>; + clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>; + power-domains = <&cpg_clocks>; + bank-width = <4>; + device-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000000 0x00080000>; + }; + + partition@80000 { + label = "uboot-env"; + reg = <0x00080000 0x00040000>; + }; + + partition@c0000 { + label = "dt"; + reg = <0x000c0000 0x00040000>; + }; + + partition@100000 { + label = "kernel"; + reg = <0x00100000 0x00280000>; + }; + + partition@400000 { + label = "rootfs"; + reg = <0x00400000 0x01c00000>; + }; + }; + }; + keyboard { compatible = "gpio-keys"; @@ -60,11 +102,6 @@ }; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - leds { compatible = "gpio-leds"; @@ -118,6 +155,30 @@ }; }; +&bsc { + flash@0 { + compatible = "cfi-flash"; + reg = <0x00000000 0x4000000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "apps"; + reg = <0x00000000 0x01000000>; + }; + + partition@1000000 { + label = "data"; + reg = <0x01000000 0x03000000>; + }; + }; + }; +}; + &usb_x1_clk { clock-frequency = <48000000>; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index b07b71307f..e6d8da6faf 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -36,6 +36,13 @@ clock-div = <3>; }; + bsc: bsc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x18000000>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts index 69a5a44b8a..cd2324b8e8 100644 --- a/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts @@ -63,11 +63,6 @@ }; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - leds { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts index e81a7213d3..ed75c01dbe 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts @@ -164,7 +164,7 @@ &bsc { flash@0 { - compatible = "cfi-flash", "mtd-rom"; + compatible = "cfi-flash"; reg = <0x0 0x08000000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/renesas/r8a7778-bockw.dts b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts index 9b65d246e5..a3f9d74e88 100644 --- a/arch/arm/boot/dts/renesas/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/renesas/r8a7778-bockw.dts @@ -62,6 +62,35 @@ }; &bsc { + flash@0 { + compatible = "cfi-flash"; + reg = <0x0 0x04000000>; + pinctrl-0 = <&flash_pins>; + pinctrl-names = "default"; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "uboot-env"; + reg = <0x00040000 0x00040000>; + read-only; + }; + partition@80000 { + label = "flash"; + reg = <0x00080000 0x03f80000>; + }; + }; + }; + ethernet@18300000 { compatible = "smsc,lan89218", "smsc,lan9115"; reg = <0x18300000 0x1000>; @@ -126,6 +155,11 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + flash_pins: flash { + groups = "lbsc_cs0"; + function = "lbsc"; + }; + scif0_pins: scif0 { groups = "scif0_data_a", "scif0_ctrl"; function = "scif0"; diff --git a/arch/arm/boot/dts/renesas/r8a7779-marzen.dts b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts index fd40890bd7..08ea149b1e 100644 --- a/arch/arm/boot/dts/renesas/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/renesas/r8a7779-marzen.dts @@ -52,21 +52,6 @@ states = <3300000 1>, <1800000 0>; }; - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0x18000000 0x100>; - pinctrl-0 = <ðernet_pins>; - pinctrl-names = "default"; - - phy-mode = "mii"; - interrupt-parent = <&irqpin0>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&fixedregulator3v3>; - vdd33a-supply = <&fixedregulator3v3>; - }; - keyboard-irq { compatible = "gpio-keys"; @@ -229,6 +214,23 @@ clock-frequency = <31250000>; }; +&lbsc { + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0x18000000 0x100>; + pinctrl-0 = <ðernet_pins>; + pinctrl-names = "default"; + + phy-mode = "mii"; + interrupt-parent = <&irqpin0>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + reg-io-width = <4>; + vddvario-supply = <&fixedregulator3v3>; + vdd33a-supply = <&fixedregulator3v3>; + }; +}; + &tmu0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi index 97b767d81d..7743af5e2a 100644 --- a/arch/arm/boot/dts/renesas/r8a7779.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -699,6 +699,13 @@ }; }; + lbsc: lbsc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x1c000000>; + }; + prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0xff000044 4>; diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 5ad5349a50..4d666ad8b1 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -73,11 +73,6 @@ reg = <1 0x40000000 0 0xc0000000>; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - keyboard { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index 26a40782cc..545515b41e 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -73,11 +73,6 @@ reg = <2 0x00000000 0 0x40000000>; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - keyboard { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index 6a83923aa4..e793134f32 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -39,21 +39,6 @@ regulator-always-on; }; - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - vga-encoder { compatible = "adi,adv7123"; @@ -196,6 +181,23 @@ clock-frequency = <48000000>; }; +&lbsc { + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0x18000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; +}; + &pfc { scif0_pins: scif0 { groups = "scif0_data"; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts index 434e4655be..f87e78fe3f 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -38,22 +38,6 @@ regulator-always-on; }; - ethernet@18000000 { - compatible = "smsc,lan89218", "smsc,lan9115"; - reg = <0 0x18000000 0 0x100>; - phy-mode = "mii"; - interrupt-parent = <&irqc>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - smsc,irq-push-pull; - smsc,save-mac-address; - reg-io-width = <4>; - vddvario-supply = <&d3_3v>; - vdd33a-supply = <&d3_3v>; - - pinctrl-0 = <&lan89218_pins>; - pinctrl-names = "default"; - }; - keyboard { compatible = "gpio-keys"; @@ -117,6 +101,24 @@ clock-frequency = <20000000>; }; +&lbsc { + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0x18000000 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + smsc,save-mac-address; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; +}; + &pfc { scif0_pins: scif0 { groups = "scif0_data"; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index a6d9367f8f..ecfab3ff59 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -84,6 +84,13 @@ clock-frequency = <0>; }; + lbsc: lbsc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x1c000000>; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index 4d93319674..08df031bc2 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -90,11 +90,6 @@ states = <3300000 1>, <1800000 0>; }; - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - keyboard { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 78686fc72c..c420c7c642 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -402,12 +402,20 @@ pinctrl-0 = <&hdmi_ctl>; status = "disabled"; - hdmi_in: port { + ports { #address-cells = <1>; #size-cells = <0>; - hdmi_in_vop: endpoint@0 { + + hdmi_in: port@0 { reg = <0>; - remote-endpoint = <&vop_out_hdmi>; + + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index 80d81af5fe..01edf244dd 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -27,6 +27,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; cpu0: cpu@f00 { device_type = "cpu"; @@ -34,10 +35,8 @@ reg = <0xf00>; clock-latency = <40000>; clocks = <&cru ARMCLK>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + resets = <&cru SRST_CORE0>; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ }; @@ -45,18 +44,59 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf01>; + resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@f02 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf02>; + resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@f03 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf03>; + resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1325000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <975000 975000 1325000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1075000 1075000 1325000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000 1200000 1325000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1325000 1325000 1325000>; }; }; @@ -77,6 +117,19 @@ #clock-cells = <0>; }; + imem: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; + }; + pmu: syscon@100a0000 { compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; reg = <0x100a0000 0x1000>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index ffc16d6b97..a721744cbf 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -215,9 +215,9 @@ power-domain@RK3228_PD_VOP { reg = <RK3228_PD_VOP>; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; + clocks = <&cru ACLK_VOP>, + <&cru DCLK_VOP>, + <&cru HCLK_VOP>; pm_qos = <&qos_vop>; #power-domain-cells = <0>; }; diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 3d587602e1..f09be84059 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -88,6 +88,10 @@ }; }; +&pwm11 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 554353e0a7..bb34b0c9cb 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -87,6 +87,22 @@ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_pin_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_pin_m0 */ + <3 RK_PA7 6 &pcfg_pull_none>; + }; + }; rgmii { /omit-if-no-ref/ rgmiim1_pins: rgmiim1-pins { diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9c918420ec..9ccd1bad62 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -247,6 +247,17 @@ status = "disabled"; }; + pwm2: pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + #pwm-cells = <3>; + status = "disabled"; + }; + pmucru: clock-controller@ff480000 { compatible = "rockchip,rv1126-pmucru"; reg = <0xff480000 0x1000>; @@ -276,6 +287,17 @@ clock-names = "apb_pclk"; }; + pwm11: pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x10>; + clock-names = "pwm", "pclk"; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@ff560000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff560000 0x100>; diff --git a/arch/arm/boot/dts/samsung/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi index f775b9377a..7f981b5c0d 100644 --- a/arch/arm/boot/dts/samsung/exynos4.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4.dtsi @@ -203,16 +203,16 @@ camera: camera@11800000 { compatible = "samsung,fimc"; + ranges = <0x0 0x11800000 0xa0000>; status = "disabled"; #address-cells = <1>; #size-cells = <1>; #clock-cells = <1>; clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - fimc_0: fimc@11800000 { + fimc_0: fimc@0 { compatible = "samsung,exynos4210-fimc"; - reg = <0x11800000 0x1000>; + reg = <0x0 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; @@ -223,9 +223,9 @@ status = "disabled"; }; - fimc_1: fimc@11810000 { + fimc_1: fimc@10000 { compatible = "samsung,exynos4210-fimc"; - reg = <0x11810000 0x1000>; + reg = <0x00010000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; @@ -236,9 +236,9 @@ status = "disabled"; }; - fimc_2: fimc@11820000 { + fimc_2: fimc@20000 { compatible = "samsung,exynos4210-fimc"; - reg = <0x11820000 0x1000>; + reg = <0x00020000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; @@ -249,9 +249,9 @@ status = "disabled"; }; - fimc_3: fimc@11830000 { + fimc_3: fimc@30000 { compatible = "samsung,exynos4210-fimc"; - reg = <0x11830000 0x1000>; + reg = <0x00030000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; @@ -262,9 +262,9 @@ status = "disabled"; }; - csis_0: csis@11880000 { + csis_0: csis@80000 { compatible = "samsung,exynos4210-csis"; - reg = <0x11880000 0x4000>; + reg = <0x00080000 0x4000>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; @@ -278,9 +278,9 @@ #size-cells = <0>; }; - csis_1: csis@11890000 { + csis_1: csis@90000 { compatible = "samsung,exynos4210-csis"; - reg = <0x11890000 0x4000>; + reg = <0x00090000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; diff --git a/arch/arm/boot/dts/samsung/exynos4210.dtsi b/arch/arm/boot/dts/samsung/exynos4210.dtsi index 0e27c3375e..510e8665d1 100644 --- a/arch/arm/boot/dts/samsung/exynos4210.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4210.dtsi @@ -391,8 +391,16 @@ }; &cpu_thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + /* + * Exynos 4210 supports thermal interrupts, but only for the rising + * threshold. This means that polling is not needed for preventing + * overheating, but only for decreasing cooling when possible. Hence we + * poll with a high delay. Ideally, we would disable polling for the + * first trip point, but this isn't really possible without outrageous + * hacks. + */ + polling-delay-passive = <5000>; + polling-delay = <5000>; }; &gic { diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index 39469b708f..e5254e32aa 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -300,34 +300,33 @@ mic-bias-supply = <&mic_bias_reg>; submic-bias-supply = <&submic_bias_reg>; - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", + audio-routing = "HP", "HPOUT1L", + "HP", "HPOUT1R", - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP", + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", - "HDMI", "LINEOUT1N", - "HDMI", "LINEOUT1P", + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", - "IN2LP:VXRN", "MICBIAS1", - "IN2LN", "MICBIAS1", - "Main Mic", "MICBIAS1", + "IN2LP:VXRN", "MICBIAS1", + "IN2LN", "MICBIAS1", + "Main Mic", "MICBIAS1", - "IN1RP", "MICBIAS2", - "IN1RN", "MICBIAS2", - "Sub Mic", "MICBIAS2", + "IN1RP", "MICBIAS2", + "IN1RN", "MICBIAS2", + "Sub Mic", "MICBIAS2", - "IN1LP", "Headset Mic", - "IN1LN", "Headset Mic"; + "IN1LP", "Headset Mic", + "IN1LN", "Headset Mic"; cpu { sound-dai = <&i2s0 0>; diff --git a/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi index 94122e9c66..54e1a57ae8 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-galaxy-s3.dtsi @@ -173,36 +173,35 @@ }; &sound { - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", + audio-routing = "HP", "HPOUT1L", + "HP", "HPOUT1R", - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP", + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", - "HDMI", "LINEOUT1N", - "HDMI", "LINEOUT1P", + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", - "IN1LP", "MICBIAS1", - "IN1LN", "MICBIAS1", - "Main Mic", "MICBIAS1", + "IN1LP", "MICBIAS1", + "IN1LN", "MICBIAS1", + "Main Mic", "MICBIAS1", - "IN1RP", "Sub Mic", - "IN1RN", "Sub Mic", + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", - "IN2LP:VXRN", "MICBIAS2", - "Headset Mic", "MICBIAS2", + "IN2LP:VXRN", "MICBIAS2", + "Headset Mic", "MICBIAS2", - "IN2RN", "FM In", - "IN2RP:VXRP", "FM In"; + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; }; &submic_bias_reg { diff --git a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi index 7daf258655..3d5aace668 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi @@ -137,21 +137,21 @@ key-down { gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; - linux,code = <114>; + linux,code = <KEY_VOLUMEDOWN>; label = "volume down"; debounce-interval = <10>; }; key-up { gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; - linux,code = <115>; + linux,code = <KEY_VOLUMEUP>; label = "volume up"; debounce-interval = <10>; }; key-power { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "power"; debounce-interval = <10>; wakeup-source; @@ -159,7 +159,7 @@ key-ok { gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; - linux,code = <139>; + linux,code = <KEY_OK>; label = "ok"; debounce-interval = <10>; wakeup-source; diff --git a/arch/arm/boot/dts/samsung/exynos4412-n710x.dts b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts index 9ae05b0d68..0a151437fc 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-n710x.dts @@ -76,34 +76,33 @@ }; &sound { - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", + audio-routing = "HP", "HPOUT1L", + "HP", "HPOUT1R", - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", - "HDMI", "LINEOUT1N", - "HDMI", "LINEOUT1P", + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", - "IN1LP", "MICBIAS2", - "IN1LN", "MICBIAS2", - "Headset Mic", "MICBIAS2", + "IN1LP", "MICBIAS2", + "IN1LN", "MICBIAS2", + "Headset Mic", "MICBIAS2", - "IN1RP", "Sub Mic", - "IN1RN", "Sub Mic", + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", - "IN2LP:VXRN", "Main Mic", - "IN2LN", "Main Mic", + "IN2LP:VXRN", "Main Mic", + "IN2LN", "Main Mic", - "IN2RN", "FM In", - "IN2RP:VXRP", "FM In"; + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; }; &submic_bias_reg { diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts index 42812da1f8..b1b0916b15 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-odroidu3.dts @@ -138,13 +138,12 @@ samsung,audio-widgets = "Headphone", "Headphone Jack", "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN1", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR"; + audio-routing = "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN1", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR"; }; &spi_1 { diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts index d5316cf2fb..0eb8a2680a 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-odroidx.dts @@ -135,9 +135,8 @@ "Headphone", "Headphone Jack", "Microphone", "Mic Jack", "Microphone", "DMIC"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "IN1", "Mic Jack", - "Mic Jack", "MICBIAS"; + audio-routing = "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "IN1", "Mic Jack", + "Mic Jack", "MICBIAS"; }; diff --git a/arch/arm/boot/dts/samsung/exynos4x12.dtsi b/arch/arm/boot/dts/samsung/exynos4x12.dtsi index 84c1db221c..83d9d0a0a6 100644 --- a/arch/arm/boot/dts/samsung/exynos4x12.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4x12.dtsi @@ -451,14 +451,15 @@ }; &camera { + ranges = <0x0 0x11800000 0xba1000>; clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { + fimc_lite_0: fimc-lite@b90000 { compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; + reg = <0x00b90000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; @@ -467,9 +468,9 @@ status = "disabled"; }; - fimc_lite_1: fimc-lite@123a0000 { + fimc_lite_1: fimc-lite@ba0000 { compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123a0000 0x1000>; + reg = <0x00ba0000 0x1000>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; @@ -478,9 +479,9 @@ status = "disabled"; }; - fimc_is: fimc-is@12000000 { + fimc_is: fimc-is@800000 { compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; + reg = <0x00800000 0x260000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_isp>; @@ -525,9 +526,9 @@ reg = <0x10020000 0x3000>; }; - i2c1_isp: i2c-isp@12140000 { + i2c1_isp: i2c-isp@940000 { compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; + reg = <0x00940000 0x100>; clocks = <&isp_clock CLK_ISP_I2C1_ISP>; clock-names = "i2c_isp"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi index 86b96f9706..52a1d8fd54 100644 --- a/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu3-audio.dtsi @@ -18,16 +18,15 @@ samsung,audio-widgets = "Headphone", "Headphone Jack", "Speakers", "Speakers"; - samsung,audio-routing = - "Headphone Jack", "HPL", - "Headphone Jack", "HPR", - "Headphone Jack", "MICBIAS", - "IN12", "Headphone Jack", - "Speakers", "SPKL", - "Speakers", "SPKR", - "I2S Playback", "Mixer DAI TX", - "HiFi Playback", "Mixer DAI TX", - "Mixer DAI RX", "HiFi Capture"; + audio-routing = "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Headphone Jack", "MICBIAS", + "IN12", "Headphone Jack", + "Speakers", "SPKL", + "Speakers", "SPKR", + "I2S Playback", "Mixer DAI TX", + "HiFi Playback", "Mixer DAI TX", + "Mixer DAI RX", "HiFi Capture"; cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; diff --git a/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts index f5fb617f46..363786f032 100644 --- a/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/samsung/exynos5422-odroidxu4.dts @@ -35,7 +35,7 @@ compatible = "samsung,odroid-xu3-audio"; model = "Odroid-XU4"; - samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; + audio-routing = "I2S Playback", "Mixer DAI TX"; cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; diff --git a/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts index eaa7c4f0e2..149e488f8e 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/samsung/s5pv210-fascinate4g.dts @@ -74,30 +74,29 @@ headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", + audio-routing = "HP", "HPOUT1L", + "HP", "HPOUT1R", - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", - "IN1LP", "Main Mic", - "IN1LN", "Main Mic", + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", - "IN1RP", "Headset Mic", - "IN1RN", "Headset Mic", + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", - "Modem Out", "Modem TX", - "Modem RX", "Modem In", + "Modem Out", "Modem TX", + "Modem RX", "Modem In", - "Bluetooth SPK", "TX", - "RX", "Bluetooth Mic"; + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; pinctrl-names = "default"; pinctrl-0 = <&headset_det &earpath_sel>; diff --git a/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts index 532d3f5bce..8792944123 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/samsung/s5pv210-galaxys.dts @@ -101,33 +101,32 @@ headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; - samsung,audio-routing = - "HP", "HPOUT1L", - "HP", "HPOUT1R", + audio-routing = "HP", "HPOUT1L", + "HP", "HPOUT1R", - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", - "RCV", "HPOUT2N", - "RCV", "HPOUT2P", + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", - "LINE", "LINEOUT2N", - "LINE", "LINEOUT2P", + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", - "IN1LP", "Main Mic", - "IN1LN", "Main Mic", + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", - "IN1RP", "Headset Mic", - "IN1RN", "Headset Mic", + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", - "IN2LN", "FM In", - "IN2RN", "FM In", + "IN2LN", "FM In", + "IN2RN", "FM In", - "Modem Out", "Modem TX", - "Modem RX", "Modem In", + "Modem Out", "Modem TX", + "Modem RX", "Modem In", - "Bluetooth SPK", "TX", - "RX", "Bluetooth Mic"; + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; pinctrl-names = "default"; pinctrl-0 = <&headset_det &earpath_sel>; diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi index f7de5b5f2f..ed560c9a3a 100644 --- a/arch/arm/boot/dts/samsung/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -549,17 +549,17 @@ camera: camera@fa600000 { compatible = "samsung,fimc"; + ranges = <0x0 0xfa600000 0xe01000>; clocks = <&clocks SCLK_CAM0>, <&clocks SCLK_CAM1>; clock-names = "sclk_cam0", "sclk_cam1"; #address-cells = <1>; #size-cells = <1>; #clock-cells = <1>; clock-output-names = "cam_a_clkout", "cam_b_clkout"; - ranges; - csis0: csis@fa600000 { + csis0: csis@0 { compatible = "samsung,s5pv210-csis"; - reg = <0xfa600000 0x4000>; + reg = <0x00000000 0x4000>; interrupt-parent = <&vic2>; interrupts = <29>; clocks = <&clocks CLK_CSIS>, @@ -572,9 +572,9 @@ #size-cells = <0>; }; - fimc0: fimc@fb200000 { + fimc0: fimc@c00000 { compatible = "samsung,s5pv210-fimc"; - reg = <0xfb200000 0x1000>; + reg = <0x00c00000 0x1000>; interrupts = <5>; interrupt-parent = <&vic2>; clocks = <&clocks CLK_FIMC0>, @@ -586,9 +586,9 @@ samsung,cam-if; }; - fimc1: fimc@fb300000 { + fimc1: fimc@d00000 { compatible = "samsung,s5pv210-fimc"; - reg = <0xfb300000 0x1000>; + reg = <0x00d00000 0x1000>; interrupt-parent = <&vic2>; interrupts = <6>; clocks = <&clocks CLK_FIMC1>, @@ -602,9 +602,9 @@ samsung,lcd-wb; }; - fimc2: fimc@fb400000 { + fimc2: fimc@e00000 { compatible = "samsung,s5pv210-fimc"; - reg = <0xfb400000 0x1000>; + reg = <0x00e00000 0x1000>; interrupt-parent = <&vic2>; interrupts = <7>; clocks = <&clocks CLK_FIMC2>, diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 44b264c399..7892ad69b4 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-lxa-tac-gen1.dtb \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ + stm32mp157c-osd32mp1-red.dtb \ stm32mp157c-phycore-stm32mp1-3.dtb dtb-$(CONFIG_ARCH_U8500) += \ ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/st/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts index 05408df382..18191a87f0 100644 --- a/arch/arm/boot/dts/st/spear1310-evb.dts +++ b/arch/arm/boot/dts/st/spear1310-evb.dts @@ -352,7 +352,6 @@ #size-cells = <0>; spi-max-frequency = <1000000>; spi-cpha; - pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable; pl022,com-mode = <0>; @@ -385,7 +384,6 @@ spi-max-frequency = <12000000>; spi-cpol; spi-cpha; - pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable; pl022,com-mode = <0x2>; diff --git a/arch/arm/boot/dts/st/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts index 7700f2afc1..cea624fc74 100644 --- a/arch/arm/boot/dts/st/spear1340-evb.dts +++ b/arch/arm/boot/dts/st/spear1340-evb.dts @@ -445,7 +445,6 @@ spi-max-frequency = <12000000>; spi-cpol; spi-cpha; - pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable; pl022,com-mode = <0x2>; @@ -461,7 +460,6 @@ spi-max-frequency = <1000000>; spi-cpha; reg = <1>; - pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable; pl022,com-mode = <0>; diff --git a/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi index 37e59403c0..7448135e25 100644 --- a/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/st/ste-href-tvk1281618-r2.dtsi @@ -192,7 +192,7 @@ #size-cells = <0>; reg = <0x4b>; vdd-supply = <&ab8500_ldo_aux1_reg>; - vddio-supply = <&db8500_vsmps2_reg>; + vio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&synaptics_tvk_mode>; interrupt-parent = <&gpio2>; @@ -200,7 +200,7 @@ rmi4-f01@1 { reg = <0x1>; - syna,nosleep = <1>; + syna,nosleep-mode = <1>; }; rmi4-f11@11 { reg = <0x11>; diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 3f58383a7b..29302e74aa 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -111,7 +111,6 @@ regulator-min-microvolt = <784000>; regulator-max-microvolt = <1299000>; regulator-always-on; - max-duty-cycle = <255>; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stih418-b2264.dts b/arch/arm/boot/dts/st/stih418-b2264.dts index fc32a03073..fdc16e9f58 100644 --- a/arch/arm/boot/dts/st/stih418-b2264.dts +++ b/arch/arm/boot/dts/st/stih418-b2264.dts @@ -69,19 +69,19 @@ }; aliases { - ttyAS0 = &sbc_serial0; + serial0 = &sbc_serial0; ethernet0 = ðernet0; }; - soc { - leds { - compatible = "gpio-leds"; - led-green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + default-state = "off"; }; + }; + soc { pin-controller-sbc@961f080 { gmac1 { rgmii1-0 { diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index a293e65141..e9ac37b6ec 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -188,9 +188,10 @@ status = "okay"; vmmc-supply = <&mmc_vcard>; broken-cd; - pinctrl-names = "default", "opendrain"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdio_pins_a>; pinctrl-1 = <&sdio_pins_od_a>; + pinctrl-2 = <&sdio_pins_sleep_a>; bus-width = <4>; }; diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi index 842f2b17c4..97fc3fb5a9 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -263,6 +263,17 @@ }; }; + sdio_pins_sleep_a: sdio-pins-sleep-a-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1 D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1 D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1 D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1 D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1 CLK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1 CMD */ + }; + }; + sdio_pins_b: sdio-pins-b-0 { pins { pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */ @@ -294,6 +305,17 @@ }; }; + sdio_pins_sleep_b: sdio-pins-sleep-b-0 { + pins { + pinmux = <STM32_PINMUX('G', 9, ANALOG)>, /* SDMMC2 D0 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* SDMMC2 D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2 D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2 D3 */ + <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC2 CLK */ + <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC2 CMD */ + }; + }; + can1_pins_a: can1-0 { pins1 { pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 37e3a905fc..087de6f096 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -164,9 +164,10 @@ status = "okay"; vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "opendrain"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdio_pins_a>; pinctrl-1 = <&sdio_pins_od_a>; + pinctrl-2 = <&sdio_pins_sleep_a>; bus-width = <4>; }; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index b038d0ed39..5d12ae25b3 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -131,9 +131,10 @@ vmmc-supply = <&mmc_vcard>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; broken-cd; - pinctrl-names = "default", "opendrain"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdio_pins_b>; pinctrl-1 = <&sdio_pins_od_b>; + pinctrl-2 = <&sdio_pins_sleep_b>; bus-width = <4>; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index ac90fcbf0c..b04d24c939 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1210,6 +1210,25 @@ }; }; + hash: hash@54003000 { + compatible = "st,stm32mp13-hash"; + reg = <0x54003000 0x400>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; + dma-names = "in"; + status = "disabled"; + }; + + rng: rng@54004000 { + compatible = "st,stm32mp13-rng"; + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 098153ee99..ae83e7b102 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + /omit-if-no-ref/ adc1_ain_pins_a: adc1-ain-0 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */ @@ -17,12 +18,14 @@ }; }; + /omit-if-no-ref/ adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>; }; }; + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ @@ -32,6 +35,7 @@ }; }; + /omit-if-no-ref/ adc12_ain_pins_b: adc12-ain-1 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ @@ -39,6 +43,7 @@ }; }; + /omit-if-no-ref/ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ @@ -46,6 +51,7 @@ }; }; + /omit-if-no-ref/ cec_pins_a: cec-0 { pins { pinmux = <STM32_PINMUX('A', 15, AF4)>; @@ -55,12 +61,14 @@ }; }; + /omit-if-no-ref/ cec_sleep_pins_a: cec-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ }; }; + /omit-if-no-ref/ cec_pins_b: cec-1 { pins { pinmux = <STM32_PINMUX('B', 6, AF5)>; @@ -70,24 +78,28 @@ }; }; + /omit-if-no-ref/ cec_sleep_pins_b: cec-sleep-1 { pins { pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ }; }; + /omit-if-no-ref/ dac_ch1_pins_a: dac-ch1-0 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>; }; }; + /omit-if-no-ref/ dac_ch2_pins_a: dac-ch2-0 { pins { pinmux = <STM32_PINMUX('A', 5, ANALOG)>; }; }; + /omit-if-no-ref/ dcmi_pins_a: dcmi-0 { pins { pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ @@ -109,6 +121,7 @@ }; }; + /omit-if-no-ref/ dcmi_sleep_pins_a: dcmi-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ @@ -129,6 +142,7 @@ }; }; + /omit-if-no-ref/ dcmi_pins_b: dcmi-1 { pins { pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ @@ -146,6 +160,7 @@ }; }; + /omit-if-no-ref/ dcmi_sleep_pins_b: dcmi-sleep-1 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ @@ -162,6 +177,7 @@ }; }; + /omit-if-no-ref/ dcmi_pins_c: dcmi-2 { pins { pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ @@ -181,6 +197,7 @@ }; }; + /omit-if-no-ref/ dcmi_sleep_pins_c: dcmi-sleep-2 { pins { pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ @@ -199,6 +216,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -230,6 +248,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ @@ -250,6 +269,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_pins_b: rgmii-1 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -281,6 +301,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ @@ -301,6 +322,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_pins_c: rgmii-2 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -332,6 +354,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ @@ -352,6 +375,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_pins_d: rgmii-3 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -382,6 +406,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 { pins1 { pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ @@ -402,6 +427,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_pins_e: rgmii-4 { pins1 { pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ @@ -425,6 +451,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 { pins1 { pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ @@ -442,6 +469,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ @@ -462,6 +490,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { pins1 { pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ @@ -476,6 +505,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_pins_b: rmii-1 { pins1 { pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ @@ -503,6 +533,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { pins1 { pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ @@ -517,6 +548,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_pins_c: rmii-2 { pins1 { pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ @@ -537,6 +569,7 @@ }; }; + /omit-if-no-ref/ ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { pins1 { pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ @@ -551,6 +584,7 @@ }; }; + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -576,6 +610,7 @@ }; }; + /omit-if-no-ref/ fmc_sleep_pins_a: fmc-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ @@ -595,6 +630,7 @@ }; }; + /omit-if-no-ref/ fmc_pins_b: fmc-1 { pins { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -624,6 +660,7 @@ }; }; + /omit-if-no-ref/ fmc_sleep_pins_b: fmc-sleep-1 { pins { pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ @@ -650,6 +687,7 @@ }; }; + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -660,6 +698,7 @@ }; }; + /omit-if-no-ref/ i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ @@ -667,6 +706,7 @@ }; }; + /omit-if-no-ref/ i2c1_pins_b: i2c1-1 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ @@ -677,6 +717,7 @@ }; }; + /omit-if-no-ref/ i2c1_sleep_pins_b: i2c1-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ @@ -684,6 +725,7 @@ }; }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ @@ -694,6 +736,7 @@ }; }; + /omit-if-no-ref/ i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ @@ -701,6 +744,7 @@ }; }; + /omit-if-no-ref/ i2c2_pins_b1: i2c2-1 { pins { pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ @@ -710,12 +754,14 @@ }; }; + /omit-if-no-ref/ i2c2_sleep_pins_b1: i2c2-sleep-1 { pins { pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ }; }; + /omit-if-no-ref/ i2c2_pins_c: i2c2-2 { pins { pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ @@ -726,6 +772,7 @@ }; }; + /omit-if-no-ref/ i2c2_pins_sleep_c: i2c2-sleep-2 { pins { pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ @@ -733,6 +780,7 @@ }; }; + /omit-if-no-ref/ i2c5_pins_a: i2c5-0 { pins { pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ @@ -743,6 +791,7 @@ }; }; + /omit-if-no-ref/ i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ @@ -751,6 +800,7 @@ }; }; + /omit-if-no-ref/ i2c5_pins_b: i2c5-1 { pins { pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ @@ -761,6 +811,7 @@ }; }; + /omit-if-no-ref/ i2c5_sleep_pins_b: i2c5-sleep-1 { pins { pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ @@ -768,6 +819,7 @@ }; }; + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ @@ -779,6 +831,7 @@ }; }; + /omit-if-no-ref/ i2s2_sleep_pins_a: i2s2-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ @@ -787,6 +840,28 @@ }; }; + /omit-if-no-ref/ + i2s2_pins_b: i2s2-1 { + pins { + pinmux = <STM32_PINMUX('C', 3, AF5)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 12, AF5)>, /* I2S2_WS */ + <STM32_PINMUX('B', 13, AF5)>; /* I2S2_CK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + i2s2_sleep_pins_b: i2s2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* I2S2_SDO */ + <STM32_PINMUX('B', 12, ANALOG)>, /* I2S2_WS */ + <STM32_PINMUX('B', 13, ANALOG)>; /* I2S2_CK */ + }; + }; + + /omit-if-no-ref/ ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ @@ -823,6 +898,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ @@ -856,6 +932,7 @@ }; }; + /omit-if-no-ref/ ltdc_pins_b: ltdc-1 { pins { pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ @@ -892,6 +969,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_b: ltdc-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ @@ -925,6 +1003,7 @@ }; }; + /omit-if-no-ref/ ltdc_pins_c: ltdc-2 { pins1 { pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ @@ -960,6 +1039,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_c: ltdc-sleep-2 { pins1 { pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ @@ -987,6 +1067,7 @@ }; }; + /omit-if-no-ref/ ltdc_pins_d: ltdc-3 { pins1 { pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ @@ -1028,6 +1109,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_d: ltdc-sleep-3 { pins { pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ @@ -1061,6 +1143,84 @@ }; }; + /omit-if-no-ref/ + ltdc_pins_e: ltdc-4 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ + <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ + <STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */ + <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ + <STM32_PINMUX('E', 14, AF13)>, /* LTDC_G0 */ + <STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */ + <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */ + <STM32_PINMUX('H', 4, AF14)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */ + <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */ + <STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */ + <STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */ + <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ + <STM32_PINMUX('A', 3, AF14)>, /* LTDC_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */ + <STM32_PINMUX('D', 8, AF14)>, /* LTDC_B7 */ + <STM32_PINMUX('F', 10, AF14)>, /* LTDC_DE */ + <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_e: ltdc-sleep-4 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* LTDC_R0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* LTDC_R1 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* LTDC_R6 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* LTDC_B0 */ + <STM32_PINMUX('G', 12, ANALOG)>, /* LTDC_B1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* LTDC_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ + <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* LTDC_B5 */ + <STM32_PINMUX('B', 8, ANALOG)>, /* LTDC_B6 */ + <STM32_PINMUX('D', 8, ANALOG)>, /* LTDC_B7 */ + <STM32_PINMUX('E', 14, ANALOG)>, /* LTDC_G0 */ + <STM32_PINMUX('E', 6, ANALOG)>, /* LTDC_G1 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ + <STM32_PINMUX('H', 14, ANALOG)>, /* LTDC_G3 */ + <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G4 */ + <STM32_PINMUX('I', 0, ANALOG)>, /* LTDC_G5 */ + <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ + <STM32_PINMUX('I', 2, ANALOG)>, /* LTDC_G7 */ + <STM32_PINMUX('F', 10, ANALOG)>, /* LTDC_DE */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ + <STM32_PINMUX('G', 7, ANALOG)>; /* LTDC_CLK */ + }; + }; + + /omit-if-no-ref/ mco1_pins_a: mco1-0 { pins { pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ @@ -1070,12 +1230,14 @@ }; }; + /omit-if-no-ref/ mco1_sleep_pins_a: mco1-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ }; }; + /omit-if-no-ref/ mco2_pins_a: mco2-0 { pins { pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ @@ -1085,12 +1247,14 @@ }; }; + /omit-if-no-ref/ mco2_sleep_pins_a: mco2-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ }; }; + /omit-if-no-ref/ m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -1104,6 +1268,7 @@ }; }; + /omit-if-no-ref/ m_can1_sleep_pins_a: m_can1-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ @@ -1111,6 +1276,7 @@ }; }; + /omit-if-no-ref/ m_can1_pins_b: m-can1-1 { pins1 { pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ @@ -1124,6 +1290,7 @@ }; }; + /omit-if-no-ref/ m_can1_sleep_pins_b: m_can1-sleep-1 { pins { pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ @@ -1131,6 +1298,7 @@ }; }; + /omit-if-no-ref/ m_can1_pins_c: m-can1-2 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -1144,6 +1312,7 @@ }; }; + /omit-if-no-ref/ m_can1_sleep_pins_c: m_can1-sleep-2 { pins { pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ @@ -1151,6 +1320,29 @@ }; }; + /omit-if-no-ref/ + m_can1_pins_d: m-can1-3 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_d: m_can1-sleep-3 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ + }; + }; + + /omit-if-no-ref/ m_can2_pins_a: m-can2-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ @@ -1164,6 +1356,7 @@ }; }; + /omit-if-no-ref/ m_can2_sleep_pins_a: m_can2-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ @@ -1171,6 +1364,7 @@ }; }; + /omit-if-no-ref/ pwm1_pins_a: pwm1-0 { pins { pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ @@ -1182,6 +1376,7 @@ }; }; + /omit-if-no-ref/ pwm1_sleep_pins_a: pwm1-sleep-0 { pins { pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ @@ -1190,6 +1385,7 @@ }; }; + /omit-if-no-ref/ pwm1_pins_b: pwm1-1 { pins { pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ @@ -1199,12 +1395,14 @@ }; }; + /omit-if-no-ref/ pwm1_sleep_pins_b: pwm1-sleep-1 { pins { pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ }; }; + /omit-if-no-ref/ pwm1_pins_c: pwm1-2 { pins { pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */ @@ -1213,12 +1411,14 @@ }; }; + /omit-if-no-ref/ pwm1_sleep_pins_c: pwm1-sleep-2 { pins { pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */ }; }; + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -1228,12 +1428,14 @@ }; }; + /omit-if-no-ref/ pwm2_sleep_pins_a: pwm2-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ @@ -1243,12 +1445,14 @@ }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ }; }; + /omit-if-no-ref/ pwm3_pins_b: pwm3-1 { pins { pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ @@ -1258,12 +1462,14 @@ }; }; + /omit-if-no-ref/ pwm3_sleep_pins_b: pwm3-sleep-1 { pins { pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ }; }; + /omit-if-no-ref/ pwm4_pins_a: pwm4-0 { pins { pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ @@ -1274,6 +1480,7 @@ }; }; + /omit-if-no-ref/ pwm4_sleep_pins_a: pwm4-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ @@ -1281,6 +1488,7 @@ }; }; + /omit-if-no-ref/ pwm4_pins_b: pwm4-1 { pins { pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ @@ -1290,12 +1498,14 @@ }; }; + /omit-if-no-ref/ pwm4_sleep_pins_b: pwm4-sleep-1 { pins { pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ }; }; + /omit-if-no-ref/ pwm5_pins_a: pwm5-0 { pins { pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ @@ -1305,12 +1515,14 @@ }; }; + /omit-if-no-ref/ pwm5_sleep_pins_a: pwm5-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ }; }; + /omit-if-no-ref/ pwm5_pins_b: pwm5-1 { pins { pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ @@ -1322,6 +1534,7 @@ }; }; + /omit-if-no-ref/ pwm5_sleep_pins_b: pwm5-sleep-1 { pins { pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ @@ -1330,6 +1543,7 @@ }; }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ @@ -1339,12 +1553,14 @@ }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ }; }; + /omit-if-no-ref/ pwm8_pins_b: pwm8-1 { pins { pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */ @@ -1356,6 +1572,7 @@ }; }; + /omit-if-no-ref/ pwm8_sleep_pins_b: pwm8-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */ @@ -1365,6 +1582,7 @@ }; }; + /omit-if-no-ref/ pwm12_pins_a: pwm12-0 { pins { pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ @@ -1374,12 +1592,14 @@ }; }; + /omit-if-no-ref/ pwm12_sleep_pins_a: pwm12-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ }; }; + /omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 { pins { pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ @@ -1389,12 +1609,14 @@ }; }; + /omit-if-no-ref/ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ }; }; + /omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 { pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ @@ -1407,6 +1629,7 @@ }; }; + /omit-if-no-ref/ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ @@ -1416,6 +1639,7 @@ }; }; + /omit-if-no-ref/ qspi_bk2_pins_a: qspi-bk2-0 { pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ @@ -1428,6 +1652,7 @@ }; }; + /omit-if-no-ref/ qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ @@ -1437,6 +1662,7 @@ }; }; + /omit-if-no-ref/ qspi_cs1_pins_a: qspi-cs1-0 { pins { pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ @@ -1446,12 +1672,14 @@ }; }; + /omit-if-no-ref/ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ }; }; + /omit-if-no-ref/ qspi_cs2_pins_a: qspi-cs2-0 { pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ @@ -1461,12 +1689,14 @@ }; }; + /omit-if-no-ref/ qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ }; }; + /omit-if-no-ref/ sai2a_pins_a: sai2a-0 { pins { pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ @@ -1479,6 +1709,7 @@ }; }; + /omit-if-no-ref/ sai2a_sleep_pins_a: sai2a-sleep-0 { pins { pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ @@ -1488,6 +1719,7 @@ }; }; + /omit-if-no-ref/ sai2a_pins_b: sai2a-1 { pins1 { pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ @@ -1499,6 +1731,7 @@ }; }; + /omit-if-no-ref/ sai2a_sleep_pins_b: sai2a-sleep-1 { pins { pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ @@ -1507,6 +1740,7 @@ }; }; + /omit-if-no-ref/ sai2a_pins_c: sai2a-2 { pins { pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ @@ -1518,6 +1752,7 @@ }; }; + /omit-if-no-ref/ sai2a_sleep_pins_c: sai2a-sleep-2 { pins { pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ @@ -1526,6 +1761,7 @@ }; }; + /omit-if-no-ref/ sai2b_pins_a: sai2b-0 { pins1 { pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ @@ -1541,6 +1777,7 @@ }; }; + /omit-if-no-ref/ sai2b_sleep_pins_a: sai2b-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ @@ -1550,6 +1787,7 @@ }; }; + /omit-if-no-ref/ sai2b_pins_b: sai2b-1 { pins { pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ @@ -1557,12 +1795,14 @@ }; }; + /omit-if-no-ref/ sai2b_sleep_pins_b: sai2b-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ }; }; + /omit-if-no-ref/ sai2b_pins_c: sai2b-2 { pins1 { pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ @@ -1570,12 +1810,14 @@ }; }; + /omit-if-no-ref/ sai2b_sleep_pins_c: sai2b-sleep-2 { pins { pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ }; }; + /omit-if-no-ref/ sai2b_pins_d: sai2b-3 { pins1 { pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */ @@ -1591,6 +1833,7 @@ }; }; + /omit-if-no-ref/ sai2b_sleep_pins_d: sai2b-sleep-3 { pins1 { pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */ @@ -1600,6 +1843,7 @@ }; }; + /omit-if-no-ref/ sai4a_pins_a: sai4a-0 { pins { pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ @@ -1609,12 +1853,14 @@ }; }; + /omit-if-no-ref/ sai4a_sleep_pins_a: sai4a-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -1634,6 +1880,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -1658,6 +1905,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -1670,6 +1918,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ @@ -1681,6 +1930,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_b: sdmmc1-b4-1 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -1700,6 +1950,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -1724,6 +1975,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 { pins { pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ @@ -1735,6 +1987,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ @@ -1750,6 +2003,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ @@ -1761,6 +2015,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ @@ -1770,6 +2025,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_dir_pins_b: sdmmc1-dir-1 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ @@ -1785,6 +2041,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ @@ -1794,6 +2051,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -1813,6 +2071,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -1837,6 +2096,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ @@ -1848,6 +2108,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_pins_b: sdmmc2-b4-1 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -1867,6 +2128,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ @@ -1891,6 +2153,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -1903,6 +2166,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ @@ -1912,6 +2176,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_b: sdmmc2-d47-1 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -1924,6 +2189,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ @@ -1933,6 +2199,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_c: sdmmc2-d47-2 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -1945,6 +2212,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ @@ -1954,6 +2222,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_d: sdmmc2-d47-3 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -1963,6 +2232,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ @@ -1972,6 +2242,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_e: sdmmc2-d47-4 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -1984,6 +2255,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 { pins { pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ @@ -1993,6 +2265,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -2012,6 +2285,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -2036,6 +2310,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ @@ -2047,6 +2322,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_pins_b: sdmmc3-b4-1 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -2066,6 +2342,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -2090,6 +2367,7 @@ }; }; + /omit-if-no-ref/ sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ @@ -2101,6 +2379,7 @@ }; }; + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ @@ -2108,12 +2387,14 @@ }; }; + /omit-if-no-ref/ spdifrx_sleep_pins_a: spdifrx-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ }; }; + /omit-if-no-ref/ spi1_pins_b: spi1-1 { pins1 { pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ @@ -2129,6 +2410,7 @@ }; }; + /omit-if-no-ref/ spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ @@ -2144,6 +2426,7 @@ }; }; + /omit-if-no-ref/ spi2_pins_b: spi2-1 { pins1 { pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ @@ -2159,6 +2442,7 @@ }; }; + /omit-if-no-ref/ spi2_pins_c: spi2-2 { pins1 { pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ @@ -2173,6 +2457,7 @@ }; }; + /omit-if-no-ref/ spi4_pins_a: spi4-0 { pins { pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ @@ -2187,6 +2472,7 @@ }; }; + /omit-if-no-ref/ spi5_pins_a: spi5-0 { pins1 { pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */ @@ -2202,6 +2488,7 @@ }; }; + /omit-if-no-ref/ stusb1600_pins_a: stusb1600-0 { pins { pinmux = <STM32_PINMUX('I', 11, GPIO)>; @@ -2209,6 +2496,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ @@ -2222,6 +2510,7 @@ }; }; + /omit-if-no-ref/ uart4_idle_pins_a: uart4-idle-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ @@ -2232,6 +2521,7 @@ }; }; + /omit-if-no-ref/ uart4_sleep_pins_a: uart4-sleep-0 { pins { pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ @@ -2239,6 +2529,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_b: uart4-1 { pins1 { pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ @@ -2252,6 +2543,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_c: uart4-2 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ @@ -2265,6 +2557,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_d: uart4-3 { pins1 { pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ @@ -2278,6 +2571,7 @@ }; }; + /omit-if-no-ref/ uart4_idle_pins_d: uart4-idle-3 { pins1 { pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ @@ -2288,6 +2582,7 @@ }; }; + /omit-if-no-ref/ uart4_sleep_pins_d: uart4-sleep-3 { pins { pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ @@ -2295,6 +2590,7 @@ }; }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ @@ -2308,6 +2604,7 @@ }; }; + /omit-if-no-ref/ uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ @@ -2323,6 +2620,7 @@ }; }; + /omit-if-no-ref/ uart7_pins_b: uart7-1 { pins1 { pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ @@ -2336,6 +2634,7 @@ }; }; + /omit-if-no-ref/ uart7_pins_c: uart7-2 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ @@ -2349,6 +2648,7 @@ }; }; + /omit-if-no-ref/ uart7_idle_pins_c: uart7-idle-2 { pins1 { pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ @@ -2359,6 +2659,7 @@ }; }; + /omit-if-no-ref/ uart7_sleep_pins_c: uart7-sleep-2 { pins { pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ @@ -2366,6 +2667,7 @@ }; }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -2379,6 +2681,7 @@ }; }; + /omit-if-no-ref/ uart8_rtscts_pins_a: uart8rtscts-0 { pins { pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ @@ -2387,6 +2690,7 @@ }; }; + /omit-if-no-ref/ usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */ @@ -2400,6 +2704,7 @@ }; }; + /omit-if-no-ref/ usart1_idle_pins_a: usart1-idle-0 { pins1 { pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ @@ -2407,6 +2712,7 @@ }; }; + /omit-if-no-ref/ usart1_sleep_pins_a: usart1-sleep-0 { pins { pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */ @@ -2414,6 +2720,7 @@ }; }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ @@ -2429,6 +2736,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ @@ -2438,6 +2746,7 @@ }; }; + /omit-if-no-ref/ usart2_pins_b: usart2-1 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ @@ -2453,6 +2762,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_b: usart2-sleep-1 { pins { pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ @@ -2462,6 +2772,7 @@ }; }; + /omit-if-no-ref/ usart2_pins_c: usart2-2 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ @@ -2477,6 +2788,7 @@ }; }; + /omit-if-no-ref/ usart2_idle_pins_c: usart2-idle-2 { pins1 { pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ @@ -2494,6 +2806,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_c: usart2-sleep-2 { pins { pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ @@ -2503,6 +2816,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ @@ -2516,6 +2830,7 @@ }; }; + /omit-if-no-ref/ usart3_idle_pins_a: usart3-idle-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */ @@ -2526,6 +2841,7 @@ }; }; + /omit-if-no-ref/ usart3_sleep_pins_a: usart3-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2533,6 +2849,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_b: usart3-1 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -2548,6 +2865,7 @@ }; }; + /omit-if-no-ref/ usart3_idle_pins_b: usart3-idle-1 { pins1 { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2565,6 +2883,7 @@ }; }; + /omit-if-no-ref/ usart3_sleep_pins_b: usart3-sleep-1 { pins { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2574,6 +2893,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_c: usart3-2 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -2589,6 +2909,7 @@ }; }; + /omit-if-no-ref/ usart3_idle_pins_c: usart3-idle-2 { pins1 { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2606,6 +2927,7 @@ }; }; + /omit-if-no-ref/ usart3_sleep_pins_c: usart3-sleep-2 { pins { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2615,6 +2937,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_d: usart3-3 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -2630,6 +2953,7 @@ }; }; + /omit-if-no-ref/ usart3_idle_pins_d: usart3-idle-3 { pins1 { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2642,6 +2966,7 @@ }; }; + /omit-if-no-ref/ usart3_sleep_pins_d: usart3-sleep-3 { pins { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2651,6 +2976,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_e: usart3-4 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -2666,6 +2992,7 @@ }; }; + /omit-if-no-ref/ usart3_idle_pins_e: usart3-idle-4 { pins1 { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2683,6 +3010,7 @@ }; }; + /omit-if-no-ref/ usart3_sleep_pins_e: usart3-sleep-4 { pins { pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ @@ -2692,6 +3020,7 @@ }; }; + /omit-if-no-ref/ usart3_pins_f: usart3-5 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ @@ -2707,12 +3036,14 @@ }; }; + /omit-if-no-ref/ usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ }; }; + /omit-if-no-ref/ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { pins { pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ @@ -2722,6 +3053,7 @@ }; &pinctrl_z { + /omit-if-no-ref/ i2c2_pins_b2: i2c2-0 { pins { pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ @@ -2731,12 +3063,14 @@ }; }; + /omit-if-no-ref/ i2c2_sleep_pins_b2: i2c2-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ }; }; + /omit-if-no-ref/ i2c4_pins_a: i2c4-0 { pins { pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ @@ -2747,6 +3081,7 @@ }; }; + /omit-if-no-ref/ i2c4_sleep_pins_a: i2c4-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ @@ -2754,6 +3089,7 @@ }; }; + /omit-if-no-ref/ i2c6_pins_a: i2c6-0 { pins { pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ @@ -2764,6 +3100,7 @@ }; }; + /omit-if-no-ref/ i2c6_sleep_pins_a: i2c6-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ @@ -2771,6 +3108,7 @@ }; }; + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ @@ -2786,6 +3124,7 @@ }; }; + /omit-if-no-ref/ spi1_sleep_pins_a: spi1-sleep-0 { pins { pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */ @@ -2794,6 +3133,7 @@ }; }; + /omit-if-no-ref/ usart1_pins_b: usart1-1 { pins1 { pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */ @@ -2807,6 +3147,7 @@ }; }; + /omit-if-no-ref/ usart1_idle_pins_b: usart1-idle-1 { pins1 { pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */ @@ -2817,6 +3158,7 @@ }; }; + /omit-if-no-ref/ usart1_sleep_pins_b: usart1-sleep-1 { pins { pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */ diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts new file mode 100644 index 0000000000..bd67a1db91 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Geanix ApS 2023 - All Rights Reserved + * Author: Sean Nyekjaer <sean@geanix.com> + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +/ { + model = "Octavo OSD32MP1 RED board"; + compatible = "oct,stm32mp157c-osd32-red", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + label = "heartbeat"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@3 { + reg = <3>; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + status = "okay"; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + hdmi-transmitter@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_e>; + pinctrl-1 = <<dc_sleep_pins_e>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sii9022_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@3 { + reg = <3>; + sii9022_tx_endpoint: endpoint { + remote-endpoint = <&i2s2_endpoint>; + }; + }; + }; + }; +}; + +&i2s2 { + clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc CK_PER>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2_pins_b>; + pinctrl-1 = <&i2s2_sleep_pins_b>; + status = "okay"; + + i2s2_port: port { + i2s2_endpoint: endpoint { + remote-endpoint = <&sii9022_tx_endpoint>; + dai-format = "i2s"; + mclk-fs = <256>; + }; + }; +}; + +<dc { + status = "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_d>; + pinctrl-1 = <&m_can1_sleep_pins_d>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index 184b8bb4eb..f09b7c384b 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -597,10 +597,6 @@ baseboard_eeprom: &sip_eeprom { phy-supply = <&vdd_usb>; }; -&v3v3_hdmi { - /delete-property/regulator-always-on; -}; - &vrefbuf { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index a43965c86f..aeb71c41a7 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -117,18 +117,14 @@ regulator-name = "v1v8_audio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; interrupts = <IT_CURLIM_LDO1 0>; - }; v3v3_hdmi: ldo2 { regulator-name = "v3v3_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; interrupts = <IT_CURLIM_LDO2 0>; - }; vtt_ddr: ldo3 { @@ -156,9 +152,7 @@ regulator-name = "v1v2_hdmi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; interrupts = <IT_CURLIM_LDO6 0>; - }; vref_ddr: vref_ddr { diff --git a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi index b8730aa52c..a59331aa58 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-moxa-uc-2100-common.dtsi @@ -217,7 +217,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; - tpm_spi_tis@0 { + tpm@0 { compatible = "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <500000>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts index 5dfe4d4bab..78ce860e59 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pocketbeagle.dts @@ -8,6 +8,7 @@ #include "am33xx.dtsi" #include "am335x-osd335x-common.dtsi" +#include <dt-bindings/leds/common.h> / { model = "TI AM335x PocketBeagle"; @@ -25,6 +26,8 @@ led-usr0 { label = "beaglebone:green:usr0"; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; @@ -32,6 +35,8 @@ led-usr1 { label = "beaglebone:green:usr1"; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; @@ -39,6 +44,8 @@ led-usr2 { label = "beaglebone:green:usr2"; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_CPU; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; @@ -46,6 +53,8 @@ led-usr3 { label = "beaglebone:green:usr3"; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_INDICATOR; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -112,7 +121,7 @@ "P2.24", "P2.33", "P2.22", - "P2.18", + "P2.18 [PRU0.15i]", "NC", "NC", "P2.01 [PWM1A]", @@ -208,11 +217,6 @@ compatible = "pinconf-single"; pinctrl-names = "default"; - pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio - &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio - &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio - &P2_17_gpio >; - /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ P2_03_gpio: P2-03-gpio-pins { pinctrl-single,pins = < @@ -267,10 +271,10 @@ pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; }; - /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ - P2_18_gpio: P2-18-gpio-pins { + /* P2_20 (ZCZ ball T13) gpio2_00 0x888 */ + P2_20_gpio: P2-20-gpio-pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE7) >; pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; @@ -401,6 +405,27 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ >; }; + + pru0_pins: pinmux-pru0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE5)/* (D14) xdma_event_intr1.pr1_pru0_pru_r31_16 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE5)/* (A14) mcasp0_ahclkx.pr1_pru0_pru_r30_7 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (B12) mcasp0_acklr.pr1_pru0_pru_r30_4 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (B13) mcasp0_fsx.pr1_pru0_pru_r30_1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE6) /* (U13) gpmc_ad15.pr1_pru0_pru_r31_15 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (D13) mcasp0_axr1.pr1_pru0_pru_r30_6 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE5)/* (C12) mcasp0_ahclkr.pr1_pru0_pru_r30_3 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (D12) mcasp0_axr0.pr1_pru0_pru_r30_2 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (C13) mcasp0_fsr.pr1_pru0_pru_r30_5 */ + >; + }; + + pru1_pins: pinmux-pru1-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE5)/*(R6) lcd_ac_bias_en.pr1_pru1_pru_r30_11 */ + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE5) /* (V5) lcd_pclk.pr1_pru1_pru_r30_10 */ + >; + }; }; &epwmss0 { @@ -482,3 +507,17 @@ &usb1 { dr_mode = "host"; }; + +&pruss_tm { + status = "okay"; +}; + +&pru0 { + pinctrl-names = "default"; + pinctrl-0 = <&pru0_pins>; +}; + +&pru1 { + pinctrl-names = "default"; + pinctrl-0 = <&pru1_pins>; +}; diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts index 866f68c5b5..40f15da810 100644 --- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts @@ -172,11 +172,24 @@ &davinci_emac { pinctrl-names = "default"; pinctrl-0 = <ðernet_pins>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; status = "okay"; }; &davinci_mdio { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + ethphy0: ethernet-phy@0 { + pinctrl-names = "default"; + pinctrl-0 = <&enet_phy_pins>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; /* gpio_58 */ + }; }; &dss { @@ -257,6 +270,12 @@ >; }; + enet_phy_pins: ethernet-phy-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20bc, PIN_INPUT | MUX_MODE4) /* gpmc_ncs7.gpio_57 */ + >; + }; + i2c2_pins: i2c2-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ diff --git a/arch/arm/boot/dts/ti/omap/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi index fbfc956f4e..77e58e686f 100644 --- a/arch/arm/boot/dts/ti/omap/am3517.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517.dtsi @@ -15,6 +15,7 @@ aliases { serial3 = &uart4; can = &hecc; + ethernet = &davinci_emac; }; cpus { diff --git a/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi index d2d516d113..a2bb3609c9 100644 --- a/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi @@ -67,7 +67,8 @@ fsusb1_phy: usb-phy@1 { compatible = "motorola,mapphone-mdm6600"; pinctrl-0 = <&usb_mdm6600_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&usb_mdm6600_sleep_pins>; + pinctrl-names = "default", "sleep"; enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; /* gpio_95 */ power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54 */ reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; /* gpio_49 */ @@ -476,6 +477,23 @@ >; }; + /* Modem sleep pins to keep gpio_49 high with internal pull */ + usb_mdm6600_sleep_pins: usb-mdm6600-sleep-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3) + OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x072, PIN_INPUT_PULLUP | MUX_MODE7) /* Keep gpio_49 reset high */ + OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3) + OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3) + OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) + OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) + OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) + OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3) + >; + }; + usb_ulpi_pins: usb-ulpi-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x196, MUX_MODE7) diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi index 3b9838f1bb..07d5894ebb 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi @@ -275,8 +275,8 @@ ethernet@6,0 { compatible = "davicom,dm9000"; - reg = <6 0x000 2 - 6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + reg = <6 0x000 2>, + <6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ bank-width = <2>; interrupt-parent = <&gpio1>; interrupts = <25 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi index b6b27e9385..3661340009 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi @@ -11,7 +11,7 @@ / { model = "OMAP3 GTA04"; - compatible = "goldelico,gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "goldelico,gta04", "ti,omap3630", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index e119e2cccc..01d783826d 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/input/input.h> #include "omap4460.dtsi" @@ -188,15 +189,6 @@ pinctrl-0 = <&mpu9150h_pins>; interrupt-parent = <&gpio2>; interrupt = <19 IRQ_TYPE_LEVEL_HIGH>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - magnetometer@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - }; - }; }; }; @@ -206,7 +198,31 @@ clock-frequency = <100000>; - /* TODO: BD2606MVV at 0x66 */ + led-controller@66 { + compatible = "rohm,bd2606mvv"; + reg = <0x66>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + }; + }; }; &i2c4 { @@ -227,7 +243,16 @@ reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; - /* TODO: mpu9150 at control unit, seems to require quirks */ + mpu9150: imu@68 { + compatible = "invensense,mpu9150"; + reg = <0x68>; + + pinctrl-names = "default"; + pinctrl-0 = <&mpu9150_pins>; + interrupt-parent = <&gpio2>; + interrupt = <7 IRQ_TYPE_LEVEL_HIGH>; + invensense,level-shifter; + }; }; &keypad { @@ -362,6 +387,12 @@ >; }; + mpu9150_pins: pinmux-mpu9150-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x5e, PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; + mpu9150h_pins: pinmux-mpu9150h-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x76, PIN_INPUT_PULLUP | MUX_MODE3) @@ -410,7 +441,7 @@ >; }; - wl12xx_gpio: pinmux-wl12xx-gpio { + wl12xx_gpio: pinmux-wl12xx-gpio-pins { pinctrl-single,pins = < OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE3) /* gpio_24 / WLAN_EN */ >; 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