diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 561 |
1 files changed, 558 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 60abcb636c..663ae52b48 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "imx8mm.dtsi" @@ -28,6 +29,73 @@ chosen { stdout-path = &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VCC_SDIO_B"; + }; }; &A53_0 { @@ -96,6 +164,79 @@ }; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names = "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -205,22 +346,86 @@ }; }; + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + address-width = <16>; + pagesize = <32>; + size = <8192>; + }; + rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; - trickle-diode-disable; }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + vbus-supply = <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + vbus-supply = <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -233,6 +438,26 @@ status = "okay"; }; +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply = <®_usdhc3_vcc>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -241,6 +466,12 @@ }; &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -250,6 +481,106 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TXD2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 @@ -257,22 +588,149 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_SCL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_SDA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; @@ -327,6 +785,103 @@ >; }; + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |