diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm6375.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6375.dtsi | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index e56f7ea4eb..a74472ac61 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -916,6 +916,36 @@ drive-strength = <6>; bias-disable; }; + + qup_uart1_default: qup-uart1-default-state { + cts-pins { + pins = "gpio61"; + function = "qup01"; + drive-strength = <2>; + bias-pull-down; + }; + + rts-pins { + pins = "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio63"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio64"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1400000 { @@ -1138,6 +1168,19 @@ status = "disabled"; }; + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a88000 0x0 0x4000>; @@ -1516,7 +1559,7 @@ compatible = "qcom,sm6375-adsp-pas"; reg = <0 0x0a400000 0 0x100>; - interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, |