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-rw-r--r--sound/soc/amd/acp/acp-i2s.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/sound/soc/amd/acp/acp-i2s.c b/sound/soc/amd/acp/acp-i2s.c
index df35001496..60cbc881be 100644
--- a/sound/soc/amd/acp/acp-i2s.c
+++ b/sound/soc/amd/acp/acp-i2s.c
@@ -20,10 +20,55 @@
#include <sound/soc.h>
#include <sound/soc-dai.h>
#include <linux/dma-mapping.h>
+#include <linux/bitfield.h>
#include "amd.h"
#define DRV_NAME "acp_i2s_playcap"
+#define I2S_MASTER_MODE_ENABLE 1
+#define LRCLK_DIV_FIELD GENMASK(10, 2)
+#define BCLK_DIV_FIELD GENMASK(23, 11)
+#define ACP63_LRCLK_DIV_FIELD GENMASK(12, 2)
+#define ACP63_BCLK_DIV_FIELD GENMASK(23, 13)
+
+static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
+{
+ u32 i2s_clk_reg, val;
+ struct acp_chip_info *chip;
+ struct device *dev;
+
+ dev = adata->dev;
+ chip = dev_get_platdata(dev);
+ switch (dai_id) {
+ case I2S_SP_INSTANCE:
+ i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
+ break;
+ case I2S_BT_INSTANCE:
+ i2s_clk_reg = ACP_I2STDM1_MSTRCLKGEN;
+ break;
+ case I2S_HS_INSTANCE:
+ i2s_clk_reg = ACP_I2STDM2_MSTRCLKGEN;
+ break;
+ default:
+ i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
+ break;
+ }
+
+ val = I2S_MASTER_MODE_ENABLE;
+ if (adata->tdm_mode)
+ val |= BIT(1);
+
+ switch (chip->acp_rev) {
+ case ACP63_DEV:
+ val |= FIELD_PREP(ACP63_LRCLK_DIV_FIELD, adata->lrclk_div);
+ val |= FIELD_PREP(ACP63_BCLK_DIV_FIELD, adata->bclk_div);
+ break;
+ default:
+ val |= FIELD_PREP(LRCLK_DIV_FIELD, adata->lrclk_div);
+ val |= FIELD_PREP(BCLK_DIV_FIELD, adata->bclk_div);
+ }
+ writel(val, adata->acp_base + i2s_clk_reg);
+}
static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)