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Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json | 152 |
1 files changed, 152 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json new file mode 100644 index 0000000000..6c92b2be2d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -0,0 +1,152 @@ +[ + { + "BriefDescription": "DTLB load misses", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "DTLB load miss large page walks", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "DTLB load miss caused by low part of address", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "DTLB second level hit", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "DTLB load miss page walks complete", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "DTLB load miss page walk cycles", + "EventCode": "0x8", + "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "DTLB misses", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "DTLB miss large page walks", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "DTLB first level misses but second level hit", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "DTLB miss page walks", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "DTLB miss page walk cycles", + "EventCode": "0x49", + "EventName": "DTLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Extended Page Table walk cycles", + "EventCode": "0x4F", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "ITLB flushes", + "EventCode": "0xAE", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "ITLB miss", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "ITLB miss large page walks", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "ITLB miss page walks", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "ITLB miss page walk cycles", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", + "EventCode": "0xC", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x1" + } +] |