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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda Highbank L2 cache ECC
description: |
Binding for the Calxeda Highbank L2 cache controller ECC device.
This does not cover the actual L2 cache controller control registers,
but just the error reporting functionality.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
reg:
maxItems: 1
interrupts:
items:
- description: single bit error interrupt
- description: double bit error interrupt
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
interrupts = <0 71 4>, <0 72 4>;
};
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