blob: c29d250a6d7724c1f4bd063a7792586a6b0fc94d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: CCI Interconnect Bus Masters
maintainers:
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
description: |
Masters in the device tree connected to a CCI port (inclusive of CPUs
and their cpu nodes).
select: true
properties:
cci-control-port:
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: true
examples:
- |
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
cci-control-port = <&cci_control1>;
reg = <0>;
};
};
...
|