1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8195
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
description:
The clock architecture in Mediatek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices except apusys_pll provide clock gate control in different IP blocks.
The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
properties:
compatible:
items:
- enum:
- mediatek,mt8195-scp_adsp
- mediatek,mt8195-imp_iic_wrap_s
- mediatek,mt8195-imp_iic_wrap_w
- mediatek,mt8195-mfgcfg
- mediatek,mt8195-wpesys
- mediatek,mt8195-wpesys_vpp0
- mediatek,mt8195-wpesys_vpp1
- mediatek,mt8195-imgsys
- mediatek,mt8195-imgsys1_dip_top
- mediatek,mt8195-imgsys1_dip_nr
- mediatek,mt8195-imgsys1_wpe
- mediatek,mt8195-ipesys
- mediatek,mt8195-camsys
- mediatek,mt8195-camsys_rawa
- mediatek,mt8195-camsys_yuva
- mediatek,mt8195-camsys_rawb
- mediatek,mt8195-camsys_yuvb
- mediatek,mt8195-camsys_mraw
- mediatek,mt8195-ccusys
- mediatek,mt8195-vdecsys_soc
- mediatek,mt8195-vdecsys
- mediatek,mt8195-vdecsys_core1
- mediatek,mt8195-vencsys
- mediatek,mt8195-vencsys_core1
- mediatek,mt8195-apusys_pll
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0x10720000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_s: clock-controller@11d03000 {
compatible = "mediatek,mt8195-imp_iic_wrap_s";
reg = <0x11d03000 0x1000>;
#clock-cells = <1>;
};
- |
imp_iic_wrap_w: clock-controller@11e05000 {
compatible = "mediatek,mt8195-imp_iic_wrap_w";
reg = <0x11e05000 0x1000>;
#clock-cells = <1>;
};
- |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8195-mfgcfg";
reg = <0x13fbf000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0x14e00000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp0: clock-controller@14e02000 {
compatible = "mediatek,mt8195-wpesys_vpp0";
reg = <0x14e02000 0x1000>;
#clock-cells = <1>;
};
- |
wpesys_vpp1: clock-controller@14e03000 {
compatible = "mediatek,mt8195-wpesys_vpp1";
reg = <0x14e03000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0x15000000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0x15110000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0x15130000 0x1000>;
#clock-cells = <1>;
};
- |
imgsys1_wpe: clock-controller@15220000 {
compatible = "mediatek,mt8195-imgsys1_wpe";
reg = <0x15220000 0x1000>;
#clock-cells = <1>;
};
- |
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0x15330000 0x1000>;
#clock-cells = <1>;
};
- |
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0x16000000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0x1604f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8195-camsys_yuva";
reg = <0x1606f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8195-camsys_rawb";
reg = <0x1608f000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8195-camsys_yuvb";
reg = <0x160af000 0x1000>;
#clock-cells = <1>;
};
- |
camsys_mraw: clock-controller@16140000 {
compatible = "mediatek,mt8195-camsys_mraw";
reg = <0x16140000 0x1000>;
#clock-cells = <1>;
};
- |
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0x17200000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0x1800f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0x1802f000 0x1000>;
#clock-cells = <1>;
};
- |
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0x1803f000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys: clock-controller@1a000000 {
compatible = "mediatek,mt8195-vencsys";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
};
- |
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0x1b000000 0x1000>;
#clock-cells = <1>;
};
- |
apusys_pll: clock-controller@190f3000 {
compatible = "mediatek,mt8195-apusys_pll";
reg = <0x190f3000 0x1000>;
#clock-cells = <1>;
};
|
