blob: 68a60cdc19af39670f20cefbc8fd3bb05a643bb3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
maintainers:
- Jacky Bai <ping.bai@nxp.com>
description: |
On i.MX8ULP, The clock sources generation, distribution and management is
under the control of several CGCs & PCCs modules. The CGC modules generate
and distribute clocks on the device.
properties:
compatible:
enum:
- fsl,imx8ulp-cgc1
- fsl,imx8ulp-cgc2
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
# Clock Generation & Control Module node:
- |
clock-controller@292c0000 {
compatible = "fsl,imx8ulp-cgc1";
reg = <0x292c0000 0x10000>;
#clock-cells = <1>;
};
|