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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/G2L MIPI DSI Encoder
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
This binding describes the MIPI DSI encoder embedded in the Renesas
RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
up to four data lanes.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
properties:
compatible:
items:
- enum:
- renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
- renesas,r9a07g054-mipi-dsi # RZ/V2L
- const: renesas,rzg2l-mipi-dsi
reg:
maxItems: 1
interrupts:
items:
- description: Sequence operation channel 0 interrupt
- description: Sequence operation channel 1 interrupt
- description: Video-Input operation channel 1 interrupt
- description: DSI Packet Receive interrupt
- description: DSI Fatal Error interrupt
- description: DSI D-PHY PPI interrupt
- description: Debug interrupt
interrupt-names:
items:
- const: seq0
- const: seq1
- const: vin1
- const: rcv
- const: ferr
- const: ppi
- const: debug
clocks:
items:
- description: DSI D-PHY PLL multiplied clock
- description: DSI D-PHY system clock
- description: DSI AXI bus clock
- description: DSI Register access clock
- description: DSI Video clock
- description: DSI D-PHY Escape mode transmit clock
clock-names:
items:
- const: pllclk
- const: sysclk
- const: aclk
- const: pclk
- const: vclk
- const: lpclk
resets:
items:
- description: MIPI_DSI_CMN_RSTB
- description: MIPI_DSI_ARESET_N
- description: MIPI_DSI_PRESET_N
reset-names:
items:
- const: rst
- const: arst
- const: prst
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Parallel input port
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: DSI output port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- data-lanes
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- resets
- reset-names
- power-domains
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r9a07g044-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dsi0: dsi@10850000 {
compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
reg = <0x10850000 0x20000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "seq0", "seq1", "vin1", "rcv",
"ferr", "ppi", "debug";
clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
<&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
<&cpg R9A07G044_MIPI_DSI_ARESET_N>,
<&cpg R9A07G044_MIPI_DSI_PRESET_N>;
reset-names = "rst", "arst", "prst";
power-domains = <&cpg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi0>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7535_in>;
};
};
};
};
...
|
