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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/renesas,shmobile-lcdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas SH-Mobile LCD Controller (LCDC)
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
enum:
- renesas,r8a7740-lcdc # R-Mobile A1
- renesas,sh73a0-lcdc # SH-Mobile AG5
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
description:
Only the functional clock is mandatory.
Some of the optional clocks are model-dependent (e.g. "video" (a.k.a.
"vou" or "dv_clk") is available on R-Mobile A1 only).
clock-names:
minItems: 1
items:
- const: fck
- enum: [ media, lclk, hdmi, video ]
- enum: [ media, lclk, hdmi, video ]
- enum: [ media, lclk, hdmi, video ]
- enum: [ media, lclk, hdmi, video ]
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: LCD port (R-Mobile A1 and SH-Mobile AG5)
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI port (R-Mobile A1 LCDC1 and SH-Mobile AG5)
unevaluatedProperties: false
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: MIPI-DSI port (SH-Mobile AG5)
unevaluatedProperties: false
required:
- port@0
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- ports
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r8a7740-lcdc
then:
properties:
ports:
properties:
port@2: false
- if:
properties:
compatible:
contains:
const: renesas,sh73a0-lcdc
then:
properties:
ports:
required:
- port@1
- port@2
examples:
- |
#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
lcd-controller@fe940000 {
compatible = "renesas,r8a7740-lcdc";
reg = <0xfe940000 0x4000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_LCDC0>,
<&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>,
<&vou_clk>;
clock-names = "fck", "media", "lclk", "video";
power-domains = <&pd_a4lc>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lcdc0_rgb: endpoint {
};
};
};
};
|
