blob: 6c84d8b7eb7b4205690a7beb6d6dd7c6fa6879a6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra TV Encoder Output
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
$nodename:
pattern: "^tvo@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-tvo
- nvidia,tegra30-tvo
- nvidia,tegra114-tvo
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
operating-points-v2: true
power-domains:
items:
- description: phandle to the core power domain
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
examples:
- |
#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tvo@542c0000 {
compatible = "nvidia,tegra20-tvo";
reg = <0x542c0000 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_TVO>;
};
|