summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
blob: 04dcadc2c20e9c1d8a3491025d4485ae0e664f38 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq FPGA Manager

maintainers:
  - Michal Simek <michal.simek@amd.com>

properties:
  compatible:
    const: xlnx,zynq-devcfg-1.0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ref_clk

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to syscon block which provide access to SLCR registers

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - syscon

additionalProperties: false

examples:
  - |
    devcfg: devcfg@f8007000 {
      compatible = "xlnx,zynq-devcfg-1.0";
      reg = <0xf8007000 0x100>;
      interrupts = <0 8 4>;
      clocks = <&clkc 12>;
      clock-names = "ref_clk";
      syscon = <&slcr>;
    };