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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SelectMAP FPGA interface
maintainers:
- Charles Perry <charles.perry@savoirfairelinux.com>
description: |
Xilinx 7 Series FPGAs support a method of loading the bitstream over a
parallel port named the SelectMAP interface in the documentation. Only
the x8 mode is supported where data is loaded at one byte per rising edge of
the clock, with the MSB of each byte presented to the D0 pin.
Datasheets:
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
allOf:
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
properties:
compatible:
enum:
- xlnx,fpga-xc7s-selectmap
- xlnx,fpga-xc7a-selectmap
- xlnx,fpga-xc7k-selectmap
- xlnx,fpga-xc7v-selectmap
reg:
description:
At least 1 byte of memory mapped IO
maxItems: 1
prog-gpios:
description:
config pin (referred to as PROGRAM_B in the manual)
maxItems: 1
done-gpios:
description:
config status pin (referred to as DONE in the manual)
maxItems: 1
init-gpios:
description:
initialization status and configuration error pin
(referred to as INIT_B in the manual)
maxItems: 1
csi-gpios:
description:
chip select pin (referred to as CSI_B in the manual)
Optional gpio for if the bus controller does not provide a chip select.
maxItems: 1
rdwr-gpios:
description:
read/write select pin (referred to as RDWR_B in the manual)
Optional gpio for if the bus controller does not provide this pin.
maxItems: 1
required:
- compatible
- reg
- prog-gpios
- done-gpios
- init-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
fpga-mgr@8000000 {
compatible = "xlnx,fpga-xc7s-selectmap";
reg = <0x8000000 0x4>;
prog-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
init-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
csi-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
rdwr-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
};
...
|
