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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Slave Serial SPI FPGA
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
over what is referred to as slave serial interface.The slave serial link is
not technically SPI, and might require extra circuits in order to play nicely
with other SPI slaves on the same bus.
Datasheets:
https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
compatible:
enum:
- xlnx,fpga-slave-serial
spi-cpha: true
spi-max-frequency:
maximum: 60000000
reg:
maxItems: 1
prog_b-gpios:
description:
config pin (referred to as PROGRAM_B in the manual)
maxItems: 1
done-gpios:
description:
config status pin (referred to as DONE in the manual)
maxItems: 1
init-b-gpios:
description:
initialization status and configuration error pin
(referred to as INIT_B in the manual)
maxItems: 1
required:
- compatible
- reg
- prog_b-gpios
- done-gpios
- init-b-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
...
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