summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
blob: f1bd1e6b2e1f8d66cb26724a2e33cc207133cf83 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell EBU GPIO controller

maintainers:
  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  - Andrew Lunn <andrew@lunn.ch>

properties:
  compatible:
    oneOf:
      - enum:
          - marvell,armada-8k-gpio
          - marvell,orion-gpio

      - items:
          - enum:
              - marvell,mv78200-gpio
              - marvell,armada-370-gpio
          - const: marvell,orion-gpio

      - description: Deprecated binding
        items:
          - const: marvell,armadaxp-gpio
          - const: marvell,orion-gpio
        deprecated: true

  reg:
    description: |
      Address and length of the register set for the device. Not used for
      marvell,armada-8k-gpio.

      A second entry can be provided, for the PWM function using the GPIO Blink
      Counter on/off registers.
    minItems: 1
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: pwm
    minItems: 1

  offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the gpio registers (in bytes)

  interrupts:
    description: |
      The list of interrupts that are used for all the pins managed by this
      GPIO bank. There can be more than one interrupt (example: 1 interrupt
      per 8 pins on Armada XP, which means 4 interrupts per bank of 32
      GPIOs).
    minItems: 1
    maxItems: 4

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  gpio-controller: true

  ngpios:
    minimum: 1
    maximum: 32

  "#gpio-cells":
    const: 2

  marvell,pwm-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the pwm registers (in bytes)

  "#pwm-cells":
    description:
      The first cell is the GPIO line number. The second cell is the period
      in nanoseconds.
    const: 2

  clocks:
    description:
      Clock(s) used for PWM function.
    items:
      - description: Core clock
      - description: AXI bus clock
    minItems: 1

  clock-names:
    items:
      - const: core
      - const: axi
    minItems: 1

required:
  - compatible
  - gpio-controller
  - ngpios
  - "#gpio-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: marvell,armada-8k-gpio
    then:
      required:
        - offset
    else:
      required:
        - reg

unevaluatedProperties: true

examples:
  - |
    gpio@d0018100 {
      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
      ngpios = <32>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <16>, <17>, <18>, <19>;
    };

  - |
    gpio@18140 {
      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
      reg = <0x18140 0x40>, <0x181c8 0x08>;
      reg-names = "gpio", "pwm";
      ngpios = <17>;
      gpio-controller;
      #gpio-cells = <2>;
      #pwm-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <87>, <88>, <89>;
      clocks = <&coreclk 0>;
    };