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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
The Messaging Unit module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status
and control) through the MU interface. The MU also provides the ability
for one processor (A side) to signal the other processor (B side) using
interrupts.
Because the MU manages the messaging between processors, the MU uses
different clocks (from each side of the different peripheral buses).
Therefore, the MU must synchronize the accesses from one side to the
other. The MU accomplishes synchronization using two sets of matching
registers (Processor A-side, Processor B-side).
MU can work as msi interrupt controller to do doorbell
allOf:
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
enum:
- fsl,imx6sx-mu-msi
- fsl,imx7ulp-mu-msi
- fsl,imx8ulp-mu-msi
- fsl,imx8ulp-mu-msi-s4
reg:
items:
- description: a side register base address
- description: b side register base address
reg-names:
items:
- const: processor-a-side
- const: processor-b-side
interrupts:
description: a side interrupt number.
maxItems: 1
clocks:
maxItems: 1
power-domains:
items:
- description: a side power domain
- description: b side power domain
power-domain-names:
items:
- const: processor-a-side
- const: processor-b-side
interrupt-controller: true
msi-controller: true
"#msi-cells":
const: 0
required:
- compatible
- reg
- interrupts
- interrupt-controller
- msi-controller
- "#msi-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/firmware/imx/rsrc.h>
msi-controller@5d270000 {
compatible = "fsl,imx6sx-mu-msi";
msi-controller;
#msi-cells = <0>;
interrupt-controller;
reg = <0x5d270000 0x10000>, /* A side */
<0x5d300000 0x10000>; /* B side */
reg-names = "processor-a-side", "processor-b-side";
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd IMX_SC_R_MU_12A>,
<&pd IMX_SC_R_MU_12B>;
power-domain-names = "processor-a-side", "processor-b-side";
};
|
